Doc: Added info about backward incompatibilities in CMSIS-Core (4dbea3d8) · Commits · Wenxi XU / Cmsis 6

CMSIS/Documentation/Doxygen/Core/src/history.md

+104 −1

Original line number	Diff line number	Diff line
		@@ -14,7 +14,8 @@ The table below provides information about the changes delivered with specific v
		<td>
		<ul>
		<li>Core(M) and Core(A) joined into single Core component</li>
		<li>Core header files reworked, aligned with TRMs</li>
		<li>Core header files reworked, aligned with Cortex-M Technical Reference Manuals (TRMs).
		<br/>See \ref core6_changes "Breaking changes in CMSIS-Core v6 header files" for details, and [GitHub issue #122](https://github.com/ARM-software/CMSIS_6/issues/122).</li>
		<li>Previously deprecated features removed</li>
		<li>Dropped support for Arm Compiler 5</li>
		</ul>
		@@ -366,3 +367,105 @@ The table below provides information about the changes delivered with specific v
		</td>
		</tr>
		</table>


		\anchor core6_changes
		<h1>Breaking changes in CMSIS-Core v6 header files</h1>

		\ref cmsis_standard_files in CMSIS-Core v6.0.0 have received a number of changes that are incompatible with CMSIS-Core v5.6.0.

		In summary, following types of incompatible changes are present:
		- struct member is renamed in an existing structure (e.g. NVIC->PR -> NVIC->IPR)
		- struct name is changed (e.g. CoreDebug_Type -> DCB_Type)
		- define name is changed (e.g. CoreDebug_DEMCR_TRCENA_Msk -> DCB_DEMCR_TRCENA_Msk)

		[GitHub issue #122](https://github.com/ARM-software/CMSIS_6/issues/122) discusses how to resolve such incompatibilities.

		Below is detailed information about the changes relevant for each Cortex-M core.

		Cortex-M0, Cortex-M0+, Cortex-M1:
		- struct NVIC_Type
		- member IP renamed to IPR
		- struct SCB_Type
		- member SHP renamed to SHPR


		Cortex-M3, Cortex-M4:
		- struct NVIC_Type
		- member IP renamed to IPR
		- struct SCB_Type
		- member SHP renamed to SHPR
		- member PFR renamed to ID_PFR
		- member PFR renamed to ID_PFR
		- member DFR renamed to ID_PFR
		- member ADR renamed to ID_AFR
		- member MMFR renamed to ID_MMFR
		- member ISAR renamed to ID_ISAR
		- member STIR added
		- struct ITM_Type:
		- members PIDx and CIDx removed
		- define names for ITM_TCR_* changed
		- define names for ITM_LSR_* changed
		- struct TPI_Type renamed to TPIU_Type
		- define names for TPI_* renamed to TPIU_*
		- define names for FPU_MVFR0/1_* changed (Cortex-M4)
		- struct CoreDebug_Type renamed to DCB_Type
		- defines for CoreDebug_* renamed to DCB_*


		Cortex-M7:
		- struct NVIC_Type
		- member IP renamed to IPR
		- struct SCB_Type
		- member ID_MFR renamed to ID_MMFR
		- struct ITM_Type:
		- members PIDx and CIDx removed
		- define names for ITM_TCR_* changed
		- define names for ITM_LSR_* changed
		- struct TPI_Type renamed to TPIU_Type
		- define names for TPI_* renamed to TPIU_*
		- define names for FPU_MVFR0/1_* changed
		- struct CoreDebug_Type renamed to DCB_Type
		- defines for CoreDebug_* renamed to DCB_*


		Cortex-M23:
		- struct DWT_Type
		- member RESERVED0[6] replaced by CYCCNT, CPICNT, EXCCNT, SLEEPCNT, LSUCNT, FOLDCNT
		- other RESERVED members mainly removed
		- struct TPI_Type renamed to TPIU_Type
		- define names for TPI_* renamed to TPIU_*
		- struct CoreDebug_Type removed (struct DCB_Type already existed)
		- defines CoreDebug_ removed (defines DCB_ already existed)


		Cortex-M33:
		- struct ITM_Type:
		- members LAR, LSR removed
		- members PIDx and CIDx removed
		- struct TPI_Type renamed to TPIU_Type
		- define names for TPI_* renamed to TPIU_*
		- define names for FPU_MVFR0/1_* changed
		- struct CoreDebug_Type removed (struct DCB_Type already existed)
		- defines CoreDebug_ removed (defines DCB_ already existed)


		Cortex-M55, Cortex-M85:
		- struct ITM_Type:
		- members LAR, LSR removed
		- members PIDx and CIDx removed
		- struct DWT_Type:
		- members PIDx and CIDx removed
		- struct EWIC_Type
		- all members renamed
		- define names EWIC_* changed
		- struct TPI_Type renamed to TPIU_Type
		- members LAR, LSR replaced
		- define names for TPI_* renamed to TPIU_*
		- struct PMU_Type
		- members PIDx and CIDx removed
		- struct CoreDebug_Type removed (struct DCB_Type already existed)
		- defines CoreDebug_ removed (defines DCB_ already existed)
		- struct DIB_Type
		- members DLAR, DLSR removed (replaced by RESERVED0[2])
		- defines for DIB_DLAR_* and DIB_DLSR_* removed

CMSIS/Documentation/Doxygen/Core/src/ref_data_structs.txt

+131 −48

Original line number	Diff line number	Diff line
		/************************** Data Structures *********************************************/
		/** \brief Union type to access the Application Program Status Register (APSR).
		/**
		\brief Union type to access the Application Program Status Register (APSR).
		*/
		typedef union
		{
		@@ -23,7 +24,8 @@ typedef union


		/**************************************************************************************************/
		/** \brief Union type to access the Interrupt Program Status Register (IPSR).
		/**
		\brief Union type to access the Interrupt Program Status Register (IPSR).
		*/
		typedef union
		{
		@@ -37,7 +39,8 @@ typedef union


		/**************************************************************************************************/
		/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
		/**
		\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
		*/
		typedef union
		{
		@@ -64,7 +67,8 @@ typedef union


		/**************************************************************************************************/
		/** \brief Union type to access the Control Registers (CONTROL).
		/**
		\brief Union type to access the Control Registers (CONTROL).
		*/
		typedef union
		{
		@@ -80,7 +84,8 @@ typedef union


		/**************************************************************************************************/
		/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
		/**
		\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
		*/
		typedef struct
		{
		@@ -94,14 +99,15 @@ typedef struct
		uint32_t RESERVED3[24]; ///< Reserved
		__IOM uint32_t IABR[8]; ///< Offset: 0x200 (R/W) Interrupt Active bit Register
		uint32_t RESERVED4[56]; ///< Reserved
		__IOM uint8_t IP[240]; ///< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
		__IOM uint8_t IPR[240]; ///< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
		uint32_t RESERVED5[644]; ///< Reserved
		__OM uint32_t STIR; ///< Offset: 0xE00 ( /W) Software Trigger Interrupt Register
		} NVIC_Type;


		/**************************************************************************************************/
		/** \brief Structure type to access the System Control Block (SCB).
		/**
		\brief Structure type to access the System Control Block (SCB).
		*/
		typedef struct
		{
		@@ -111,7 +117,7 @@ typedef struct
		__IOM uint32_t AIRCR; ///< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
		__IOM uint32_t SCR; ///< Offset: 0x010 (R/W) System Control Register
		__IOM uint32_t CCR; ///< Offset: 0x014 (R/W) Configuration Control Register
		__IOM uint8_t SHP[12]; ///< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
		__IOM uint8_t SHPR[12U]; ///< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
		__IOM uint32_t SHCSR; ///< Offset: 0x024 (R/W) System Handler Control and State Register
		__IOM uint32_t CFSR; ///< Offset: 0x028 (R/W) Configurable Fault Status Register
		__IOM uint32_t HFSR; ///< Offset: 0x02C (R/W) HardFault Status Register
		@@ -119,18 +125,21 @@ typedef struct
		__IOM uint32_t MMFAR; ///< Offset: 0x034 (R/W) MemManage Fault Address Register
		__IOM uint32_t BFAR; ///< Offset: 0x038 (R/W) BusFault Address Register
		__IOM uint32_t AFSR; ///< Offset: 0x03C (R/W) Auxiliary Fault Status Register
		__IM uint32_t PFR[2]; ///< Offset: 0x040 (R/ ) Processor Feature Register
		__IM uint32_t DFR; ///< Offset: 0x048 (R/ ) Debug Feature Register
		__IM uint32_t ADR; ///< Offset: 0x04C (R/ ) Auxiliary Feature Register
		__IM uint32_t MMFR[4]; ///< Offset: 0x050 (R/ ) Memory Model Feature Register
		__IM uint32_t ISAR[5]; ///< Offset: 0x060 (R/ ) Instruction Set Attributes Register
		uint32_t RESERVED0[5]; ///< Reserved
		__IM uint32_t ID_PFR[2U]; ///< Offset: 0x040 (R/ ) Processor Feature Register
		__IM uint32_t ID_DFR; ///< Offset: 0x048 (R/ ) Debug Feature Register
		__IM uint32_t ID_AFR; ///< Offset: 0x04C (R/ ) Auxiliary Feature Register
		__IM uint32_t ID_MMFR[4U]; ///< Offset: 0x050 (R/ ) Memory Model Feature Register
		__IM uint32_t ID_ISAR[5U]; ///< Offset: 0x060 (R/ ) Instruction Set Attributes Register
		// uint32_t RESERVED0[5U];
		__IOM uint32_t CPACR; ///< Offset: 0x088 (R/W) Coprocessor Access Control Register
		// uint32_t RESERVED3[93U];
		__OM uint32_t STIR; ///< Offset: 0x200 ( /W) Software Triggered Interrupt Register
		} SCB_Type;


		/**************************************************************************************************/
		/** \brief Structure type to access the System Control and ID Register not in the SCB.
		/**
		\brief Structure type to access the System Control and ID Register not in the SCB.
		*/
		typedef struct
		{
		@@ -145,7 +154,8 @@ typedef struct


		/**************************************************************************************************/
		/** \brief Structure type to access the Implementation Control Block Register (ICB).
		/**
		\brief Structure type to access the Implementation Control Block Register (ICB).
		\note replaces SCnSCB_Type (only on Cortex-M55/M85)
		*/
		typedef struct
		@@ -170,7 +180,8 @@ typedef struct


		/**************************************************************************************************/
		/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
		/**
		\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
		*/
		typedef struct
		{
		@@ -196,23 +207,12 @@ typedef struct
		// uint32_t RESERVED5[1U];
		__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only) /
		// uint32_t RESERVED6[4U];
		__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
		__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
		__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
		__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
		__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
		__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
		__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
		__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
		__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
		__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
		__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
		__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
		} ITM_Type;


		/**************************************************************************************************/
		/** \brief Structure type to access the Memory Protection Unit (MPU).
		/**
		\brief Structure type to access the Memory Protection Unit (MPU).
		*/
		typedef struct
		{
		@@ -231,11 +231,12 @@ typedef struct


		/**************************************************************************************************/
		/** \brief Structure type to access the Floating Point Unit (FPU).
		/**
		\brief Structure type to access the Floating Point Unit (FPU).
		*/
		typedef struct
		{
		uint32_t RESERVED0[1]; ///< Reserved
		// uint32_t RESERVED0[1]; ///< Reserved
		__IOM uint32_t FPCCR; ///< Offset: 0x004 (R/W) Floating-Point Context Control Register
		__IOM uint32_t FPCAR; ///< Offset: 0x008 (R/W) Floating-Point Context Address Register
		__IOM uint32_t FPDSCR; ///< Offset: 0x00C (R/W) Floating-Point Default Status Control Register
		@@ -245,7 +246,8 @@ typedef struct


		/**************************************************************************************************/
		/** \brief Structure type to access the Core Debug Register (CoreDebug).
		/**
		\brief Structure type to access the Debug Control Block Registers (DCB).
		*/
		typedef struct
		{
		@@ -253,11 +255,15 @@ typedef struct
		__OM uint32_t DCRSR; ///< Offset: 0x004 ( /W) Debug Core Register Selector Register
		__IOM uint32_t DCRDR; ///< Offset: 0x008 (R/W) Debug Core Register Data Register
		__IOM uint32_t DEMCR; ///< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register
		} CoreDebug_Type;
		__OM uint32_t DSCEMCR; ///< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register (Armv8.1-M only)
		__IOM uint32_t DAUTHCTRL; ///< Offset: 0x014 (R/W) Debug Authentication Control Register (Armv8-M only)
		__IOM uint32_t DSCSR; ///< Offset: 0x018 (R/W) Debug Security Control and Status Register (Armv8-M only)
		} DCB_Type;


		/**************************************************************************************************/
		/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
		/**
		\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
		*/
		typedef struct
		{
		@@ -272,15 +278,15 @@ typedef struct
		__IOM uint32_t COMP0; ///< Offset: 0x020 (R/W) Comparator Register 0
		__IOM uint32_t MASK0; ///< Offset: 0x024 (R/W) Mask Register 0
		__IOM uint32_t FUNCTION0; ///< Offset: 0x028 (R/W) Function Register 0
		uint32_t RESERVED0[1]; ///< Reserved
		// uint32_t RESERVED0[1]; ///< Reserved
		__IOM uint32_t COMP1; ///< Offset: 0x030 (R/W) Comparator Register 1
		__IOM uint32_t MASK1; ///< Offset: 0x034 (R/W) Mask Register 1
		__IOM uint32_t FUNCTION1; ///< Offset: 0x038 (R/W) Function Register 1
		uint32_t RESERVED1[1]; ///< Reserved
		// uint32_t RESERVED1[1]; ///< Reserved
		__IOM uint32_t COMP2; ///< Offset: 0x040 (R/W) Comparator Register 2
		__IOM uint32_t MASK2; ///< Offset: 0x044 (R/W) Mask Register 2
		__IOM uint32_t FUNCTION2; ///< Offset: 0x048 (R/W) Function Register 2
		uint32_t RESERVED2[1]; ///< Reserved
		// uint32_t RESERVED2[1]; ///< Reserved
		__IOM uint32_t COMP3; ///< Offset: 0x050 (R/W) Comparator Register 3
		__IOM uint32_t MASK3; ///< Offset: 0x054 (R/W) Mask Register 3
		__IOM uint32_t FUNCTION3; ///< Offset: 0x058 (R/W) Function Register 3
		@@ -288,32 +294,109 @@ typedef struct


		/**************************************************************************************************/
		/** \brief Structure type to access the Trace Port Interface Register (TPI).
		/**
		\brief Structure type to access the Trace Port Interface Register (TPI).
		*/
		typedef struct
		{
		__IOM uint32_t SSPSR; ///< Offset: 0x000 (R/ ) Supported Parallel Port Size Register
		__IOM uint32_t CSPSR; ///< Offset: 0x004 (R/W) Current Parallel Port Size Register
		uint32_t RESERVED0[2]; ///< Reserved
		// uint32_t RESERVED0[2]; ///< Reserved
		__IOM uint32_t ACPR; ///< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register
		uint32_t RESERVED1[55]; ///< Reserved
		// uint32_t RESERVED1[55]; ///< Reserved
		__IOM uint32_t SPPR; ///< Offset: 0x0F0 (R/W) Selected Pin Protocol Register
		uint32_t RESERVED2[131]; ///< Reserved
		// uint32_t RESERVED2[131]; ///< Reserved
		__IM uint32_t FFSR; ///< Offset: 0x300 (R/ ) Formatter and Flush Status Register
		__IOM uint32_t FFCR; ///< Offset: 0x304 (R/W) Formatter and Flush Control Register
		__IM uint32_t FSCR; ///< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register
		uint32_t RESERVED3[759]; ///< Reserved
		// uint32_t RESERVED3[759]; ///< Reserved
		__IM uint32_t TRIGGER; ///< Offset: 0xEE8 (R/ ) TRIGGER
		__IM uint32_t FIFO0; ///< Offset: 0xEEC (R/ ) Integration ETM Data
		__IM uint32_t ITATBCTR2; ///< Offset: 0xEF0 (R/ ) ITATBCTR2
		uint32_t RESERVED4[1]; ///< Reserved
		// uint32_t RESERVED4[1]; ///< Reserved
		__IM uint32_t ITATBCTR0; ///< Offset: 0xEF8 (R/ ) ITATBCTR0
		__IM uint32_t FIFO1; ///< Offset: 0xEFC (R/ ) Integration ITM Data
		__IOM uint32_t ITCTRL; ///< Offset: 0xF00 (R/W) Integration Mode Control
		uint32_t RESERVED5[39]; ///< Reserved
		// uint32_t RESERVED5[39]; ///< Reserved
		__IOM uint32_t CLAIMSET; ///< Offset: 0xFA0 (R/W) Claim tag set
		__IOM uint32_t CLAIMCLR; ///< Offset: 0xFA4 (R/W) Claim tag clear
		uint32_t RESERVED7[8]; ///< Reserved
		// uint32_t RESERVED7[8]; ///< Reserved
		__IM uint32_t DEVID; ///< Offset: 0xFC8 (R/ ) TPIU_DEVID
		__IM uint32_t DEVTYPE; ///< Offset: 0xFCC (R/ ) TPIU_DEVTYPE
		} TPI_Type;
		} TPIU_Type;


		/**************************************************************************************************/
		/**
		\brief Structure type to access the Performance Monitoring Unit (PMU).
		*/
		typedef struct
		{
		__IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; ///< Offset: 0x0 (R/W) Event Counter Registers
		//#if __PMU_NUM_EVENTCNT<31
		// uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
		//#endif
		__IOM uint32_t CCNTR; ///< Offset: 0x7C (R/W) Cycle Counter Register
		// uint32_t RESERVED1[224];
		__IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; ///< Offset: 0x400 (R/W) Event Type and Filter Registers
		//#if __PMU_NUM_EVENTCNT<31
		// uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
		//#endif
		__IOM uint32_t CCFILTR; ///< Offset: 0x47C (R/W) Cycle Counter Filter Register
		// uint32_t RESERVED3[480];
		__IOM uint32_t CNTENSET; ///< Offset: 0xC00 (R/W) Count Enable Set Register
		// uint32_t RESERVED4[7];
		__IOM uint32_t CNTENCLR; ///< Offset: 0xC20 (R/W) Count Enable Clear Register
		// uint32_t RESERVED5[7];
		__IOM uint32_t INTENSET; ///< Offset: 0xC40 (R/W) Interrupt Enable Set Register
		// uint32_t RESERVED6[7];
		__IOM uint32_t INTENCLR; ///< Offset: 0xC60 (R/W) Interrupt Enable Clear Register
		// uint32_t RESERVED7[7];
		__IOM uint32_t OVSCLR; ///< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register
		// uint32_t RESERVED8[7];
		__IOM uint32_t SWINC; ///< Offset: 0xCA0 (R/W) Software Increment Register
		// uint32_t RESERVED9[7];
		__IOM uint32_t OVSSET; ///< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register
		// uint32_t RESERVED10[79];
		__IOM uint32_t TYPE; ///< Offset: 0xE00 (R/W) Type Register
		__IOM uint32_t CTRL; ///< Offset: 0xE04 (R/W) Control Register
		// uint32_t RESERVED11[108];
		__IOM uint32_t AUTHSTATUS; ///< Offset: 0xFB8 (R/W) Authentication Status Register
		__IOM uint32_t DEVARCH; ///< Offset: 0xFBC (R/W) Device Architecture Register
		// uint32_t RESERVED12[3];
		__IOM uint32_t DEVTYPE; ///< Offset: 0xFCC (R/W) Device Type Register
		} PMU_Type;


		/**************************************************************************************************/
		/**
		\brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
		*/
		typedef struct
		{
		__IOM uint32_t EWIC_CR; ///< Offset: 0x000 (R/W) EWIC Control Register
		__IOM uint32_t EWIC_ASCR; ///< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register
		__OM uint32_t EWIC_CLRMASK; ///< Offset: 0x008 ( /W) EWIC Clear Mask Register
		__IM uint32_t EWIC_NUMID; ///< Offset: 0x00C (R/ ) EWIC Event Number ID Register
		// uint32_t RESERVED0[124U];
		__IOM uint32_t EWIC_MASKA; ///< Offset: 0x200 (R/W) EWIC MaskA Register
		__IOM uint32_t EWIC_MASKn[15]; ///< Offset: 0x204 (R/W) EWIC Maskn Registers
		// uint32_t RESERVED1[112U];
		__IM uint32_t EWIC_PENDA; ///< Offset: 0x400 (R/ ) EWIC PendA Event Register
		__IOM uint32_t EWIC_PENDn[15]; ///< Offset: 0x404 (R/W) EWIC Pendn Event Registers
		// uint32_t RESERVED2[112U];
		__IM uint32_t EWIC_PSR; ///< Offset: 0x600 (R/ ) EWIC Pend Summary Register
		} EWIC_Type;


		/**
		\brief Structure type to access the Debug Identification Block Registers (DIB).
		*/
		typedef struct
		{
		// uint32_t RESERVED0[2U];
		__IM uint32_t DAUTHSTATUS; ///< Offset: 0x008 (R/ ) Debug Authentication Status Register
		__IM uint32_t DDEVARCH; ///< Offset: 0x00C (R/ ) SCS Device Architecture Register
		// uint32_t RESERVED1[3U];
		__IM uint32_t DDEVTYPE; ///< Offset: 0x01C (R/ ) SCS Device Type Register
		} DIB_Type;

CMSIS/Documentation/Doxygen/General/src/mainpage.md

+3 −0

Original line number	Diff line number	Diff line
		@@ -152,6 +152,9 @@ While use of CMSIS-Pack concept greatly helps to abstract many of this changes f
		- [Migrating CMSIS-based projects from CMSIS v5 to CMSIS v6](https://learn.arm.com/learning-paths/microcontrollers/project-migration-cmsis-v6)
		- [CMSIS-Pack Migration Guide](https://learn.arm.com/learning-paths/microcontrollers/pack-migration-cmsis-v6)

		> Note
		> - In the version 6.0.0, the CMSIS-Core header files for Cortex-M devices have received some modifications that are incompatible with previous CMSIS-Core versions. Refer to the [CMSIS-Core Revision History](../Core/core_revisionHistory.html) for more information.

		## License {#License}

		CMSIS is provided free of charge by Arm under the [Apache 2.0 License](https://raw.githubusercontent.com/ARM-software/CMSIS_6/main/LICENSE).

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