* Top-level compiler headers will exist in the core folder (no separate compiler folder is needed). (4d18b8de) · Commits · Wenxi XU / Cmsis 6

CMSIS/Core/Include/a-profile/cmsis_armclang_a.h

+11 −448

Original line number	Diff line number	Diff line
		@@ -25,367 +25,9 @@

		#pragma clang system_header /* treat file as system include file */

		/* CMSIS compiler specific defines */
		#ifndef __ASM
		#define __ASM __asm
		#ifndef __CMSIS_ARMCLANG_H
		#error "This file must not be included directly"
		#endif
		#ifndef __INLINE
		#define __INLINE inline
		#endif
		#ifndef __STATIC_INLINE
		#define __STATIC_INLINE static inline
		#endif
		#ifndef __STATIC_FORCEINLINE
		#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
		#endif
		#ifndef __NO_RETURN
		#define __NO_RETURN __attribute__((__noreturn__))
		#endif
		#ifndef __USED
		#define __USED __attribute__((used))
		#endif
		#ifndef __WEAK
		#define __WEAK __attribute__((weak))
		#endif
		#ifndef __PACKED
		#define __PACKED __attribute__((packed, aligned(1)))
		#endif
		#ifndef __PACKED_STRUCT
		#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
		#endif
		#ifndef __PACKED_UNION
		#define __PACKED_UNION union __attribute__((packed, aligned(1)))
		#endif
		#ifndef __UNALIGNED_UINT16_WRITE
		#pragma clang diagnostic push
		#pragma clang diagnostic ignored "-Wpacked"
		__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
		#pragma clang diagnostic pop
		#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
		#endif
		#ifndef __UNALIGNED_UINT16_READ
		#pragma clang diagnostic push
		#pragma clang diagnostic ignored "-Wpacked"
		__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
		#pragma clang diagnostic pop
		#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
		#endif
		#ifndef __UNALIGNED_UINT32_WRITE
		#pragma clang diagnostic push
		#pragma clang diagnostic ignored "-Wpacked"
		__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
		#pragma clang diagnostic pop
		#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
		#endif
		#ifndef __UNALIGNED_UINT32_READ
		#pragma clang diagnostic push
		#pragma clang diagnostic ignored "-Wpacked"
		__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
		#pragma clang diagnostic pop
		#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
		#endif
		#ifndef __ALIGNED
		#define __ALIGNED(x) __attribute__((aligned(x)))
		#endif
		#ifndef __RESTRICT
		#define __RESTRICT __restrict
		#endif
		#ifndef __COMPILER_BARRIER
		#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
		#endif


		/* ########################## Core Instruction Access ######################### */
		/**
		\brief No Operation
		\details No Operation does nothing. This instruction can be used for code alignment purposes.
		*/
		#define __NOP __builtin_arm_nop


		/**
		\brief Wait For Interrupt
		\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
		*/
		#define __WFI __builtin_arm_wfi


		/**
		\brief Wait For Event
		\details Wait For Event is a hint instruction that permits the processor to enter
		a low-power state until one of a number of events occurs.
		*/
		#define __WFE __builtin_arm_wfe


		/**
		\brief Send Event
		\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
		*/
		#define __SEV __builtin_arm_sev


		/**
		\brief Instruction Synchronization Barrier
		\details Instruction Synchronization Barrier flushes the pipeline in the processor,
		so that all instructions following the ISB are fetched from cache or memory,
		after the instruction has been completed.
		*/
		#define __ISB() __builtin_arm_isb(0xF)


		/**
		\brief Data Synchronization Barrier
		\details Acts as a special kind of Data Memory Barrier.
		It completes when all explicit memory accesses before this instruction complete.
		*/
		#define __DSB() __builtin_arm_dsb(0xF)


		/**
		\brief Data Memory Barrier
		\details Ensures the apparent order of the explicit memory operations before
		and after the instruction, without ensuring their completion.
		*/
		#define __DMB() __builtin_arm_dmb(0xF)


		/**
		\brief Reverse byte order (32 bit)
		\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
		\param [in] value Value to reverse
		\return Reversed value
		*/
		#define __REV(value) __builtin_bswap32(value)


		/**
		\brief Reverse byte order (16 bit)
		\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
		\param [in] value Value to reverse
		\return Reversed value
		*/
		#define __REV16(value) __ROR(__REV(value), 16)


		/**
		\brief Reverse byte order (16 bit)
		\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
		\param [in] value Value to reverse
		\return Reversed value
		*/
		#define __REVSH(value) (int16_t)__builtin_bswap16(value)


		/**
		\brief Rotate Right in unsigned value (32 bit)
		\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
		\param [in] op1 Value to rotate
		\param [in] op2 Number of Bits to rotate
		\return Rotated value
		*/
		__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
		{
		op2 %= 32U;
		if (op2 == 0U)
		{
		return op1;
		}
		return (op1 >> op2) \| (op1 << (32U - op2));
		}


		/**
		\brief Breakpoint
		\details Causes the processor to enter Debug state.
		Debug tools can use this to investigate system state when the instruction at a particular address is reached.
		\param [in] value is ignored by the processor.
		If required, a debugger can use it to store additional information about the breakpoint.
		*/
		#define __BKPT(value) __ASM volatile ("bkpt "#value)


		/**
		\brief Reverse bit order of value
		\details Reverses the bit order of the given value.
		\param [in] value Value to reverse
		\return Reversed value
		*/
		#define __RBIT __builtin_arm_rbit


		/**
		\brief Count leading zeros
		\details Counts the number of leading zeros of a data value.
		\param [in] value Value to count the leading zeros
		\return number of leading zeros in value
		*/
		__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
		{
		/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
		__builtin_clz(0) is undefined behaviour, so handle this case specially.
		This guarantees ARM-compatible results if happening to compile on a non-ARM
		target, and ensures the compiler doesn't decide to activate any
		optimisations using the logic "value was passed to __builtin_clz, so it
		is non-zero".
		ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
		single CLZ instruction.
		*/
		if (value == 0U)
		{
		return 32U;
		}
		return __builtin_clz(value);
		}


		/**
		\brief Signed Saturate
		\details Saturates a signed value.
		\param [in] value Value to be saturated
		\param [in] sat Bit position to saturate to (1..32)
		\return Saturated value
		*/
		#define __SSAT __builtin_arm_ssat


		/**
		\brief Unsigned Saturate
		\details Saturates an unsigned value.
		\param [in] value Value to be saturated
		\param [in] sat Bit position to saturate to (0..31)
		\return Saturated value
		*/
		#define __USAT __builtin_arm_usat


		/**
		\brief Remove the exclusive lock
		\details Removes the exclusive lock which is created by LDREX.
		*/
		#define __CLREX __builtin_arm_clrex


		/**
		\brief LDR Exclusive (8 bit)
		\details Executes a exclusive LDR instruction for 8 bit value.
		\param [in] ptr Pointer to data
		\return value of type uint8_t at (*ptr)
		*/
		#define __LDREXB (uint8_t)__builtin_arm_ldrex


		/**
		\brief LDR Exclusive (16 bit)
		\details Executes a exclusive LDR instruction for 16 bit values.
		\param [in] ptr Pointer to data
		\return value of type uint16_t at (*ptr)
		*/
		#define __LDREXH (uint16_t)__builtin_arm_ldrex


		/**
		\brief LDR Exclusive (32 bit)
		\details Executes a exclusive LDR instruction for 32 bit values.
		\param [in] ptr Pointer to data
		\return value of type uint32_t at (*ptr)
		*/
		#define __LDREXW (uint32_t)__builtin_arm_ldrex


		/**
		\brief STR Exclusive (8 bit)
		\details Executes a exclusive STR instruction for 8 bit values.
		\param [in] value Value to store
		\param [in] ptr Pointer to location
		\return 0 Function succeeded
		\return 1 Function failed
		*/
		#define __STREXB (uint32_t)__builtin_arm_strex


		/**
		\brief STR Exclusive (16 bit)
		\details Executes a exclusive STR instruction for 16 bit values.
		\param [in] value Value to store
		\param [in] ptr Pointer to location
		\return 0 Function succeeded
		\return 1 Function failed
		*/
		#define __STREXH (uint32_t)__builtin_arm_strex


		/**
		\brief STR Exclusive (32 bit)
		\details Executes a exclusive STR instruction for 32 bit values.
		\param [in] value Value to store
		\param [in] ptr Pointer to location
		\return 0 Function succeeded
		\return 1 Function failed
		*/
		#define __STREXW (uint32_t)__builtin_arm_strex


		/**
		\brief Rotate Right with Extend (32 bit)
		\details Moves each bit of a bitstring right by one bit.
		The carry input is shifted in at the left end of the bitstring.
		\param [in] value Value to rotate
		\return Rotated value
		*/
		__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
		{
		uint32_t result;

		__ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
		return (result);
		}


		/**
		\brief LDRT Unprivileged (8 bit)
		\details Executes a Unprivileged LDRT instruction for 8 bit value.
		\param [in] ptr Pointer to data
		\return value of type uint8_t at (*ptr)
		*/
		__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
		{
		uint32_t result;

		__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
		return ((uint8_t)result); /* Add explicit type cast here */
		}


		/**
		\brief LDRT Unprivileged (16 bit)
		\details Executes a Unprivileged LDRT instruction for 16 bit values.
		\param [in] ptr Pointer to data
		\return value of type uint16_t at (*ptr)
		*/
		__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
		{
		uint32_t result;

		__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
		return ((uint16_t)result); /* Add explicit type cast here */
		}


		/**
		\brief LDRT Unprivileged (32 bit)
		\details Executes a Unprivileged LDRT instruction for 32 bit values.
		\param [in] ptr Pointer to data
		\return value of type uint32_t at (*ptr)
		*/
		__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
		{
		uint32_t result;

		__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
		return (result);
		}


		/**
		\brief STRT Unprivileged (8 bit)
		@@ -422,86 +64,6 @@ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
		__ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
		}

		/* ########################### Core Function Access ########################### */
		/** \ingroup CMSIS_Core_FunctionInterface
		\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
		@{
		*/

		/**
		\brief Enable IRQ Interrupts
		\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
		Can only be executed in Privileged modes.
		*/
		__STATIC_FORCEINLINE void __enable_irq(void)
		{
		__ASM volatile ("cpsie i" : : : "memory");
		}


		/**
		\brief Disable IRQ Interrupts
		\details Disables IRQ interrupts by setting the I-bit in the CPSR.
		Can only be executed in Privileged modes.
		*/
		__STATIC_FORCEINLINE void __disable_irq(void)
		{
		__ASM volatile ("cpsid i" : : : "memory");
		}

		/**
		\brief Enable FIQ
		\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
		Can only be executed in Privileged modes.
		*/
		__STATIC_FORCEINLINE void __enable_fault_irq(void)
		{
		__ASM volatile ("cpsie f" : : : "memory");
		}


		/**
		\brief Disable FIQ
		\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
		Can only be executed in Privileged modes.
		*/
		__STATIC_FORCEINLINE void __disable_fault_irq(void)
		{
		__ASM volatile ("cpsid f" : : : "memory");
		}


		/**
		\brief Get FPSCR
		\details Returns the current value of the Floating Point Status/Control register.
		\return Floating Point Status/Control register value
		*/
		__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
		{
		#if (defined(__ARM_FP) && (__ARM_FP >= 1))
		return __builtin_arm_get_fpscr();
		#else
		return(0U);
		#endif
		}


		/**
		\brief Set FPSCR
		\details Assigns the given value to the Floating Point Status/Control register.
		\param [in] fpscr Floating Point Status/Control value to set
		*/
		__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
		{
		#if (defined(__ARM_FP) && (__ARM_FP >= 1))
		__builtin_arm_set_fpscr(fpscr);
		#else
		(void)fpscr;
		#endif
		}


		/@} end of CMSIS_Core_RegAccFunctions /


		/* ################### Compiler specific Intrinsics ########################### */
		@@ -509,7 +71,6 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
		Access to dedicated SIMD instructions
		@{
		*/

		#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))

		#define __SADD8 __builtin_arm_sadd8
		@@ -627,11 +188,12 @@ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
		return (result);
		}

		#endif /* (__ARM_FEATURE_DSP == 1) */
		#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
		/** @} end of group CMSIS_SIMD_intrinsics */

		/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics
		Access to dedicated SIMD instructions
		/* ########################### Core Function Access ########################### */
		/** \ingroup CMSIS_Core_FunctionInterface
		\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
		@{
		*/

		@@ -743,6 +305,9 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
		#endif
		}

		/** @} end of CMSIS_Core_RegAccFunctions */


		/*
		* Include common core functions to access Coprocessor 15 registers
		*/
		@@ -824,6 +389,4 @@ __STATIC_INLINE void __FPU_Enable(void)
		);
		}

		/@} end of group CMSIS_Core_intrinsics /

		#endif /* __CMSIS_ARMCLANG_A_H */