Commit 54eaf195 authored by Carles Cufi's avatar Carles Cufi Committed by Carles Cufí
Browse files

cmsis: Add CMSIS-Core(R) 

This commit adds a preliminary implementation of CMSIS-Core(R) for use
with the ARM Cortex-R port.

At this time, CMSIS-Core(R) is not merged back into the upstream CMSIS
repository and therefore is not available from official sources.

Until upstream merge happens, the preliminary version can be obtained
from the following URL:

https://github.com/stephanosio/CMSIS_5/tree/core_r



Signed-off-by: default avatarStephanos Ioannidis <root@stephanos.io>
Signed-off-by: default avatarCarles Cufi <carles.cufi@nordicsemi.no>
parent 0d43487d

CMSIS/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0



add_subdirectory_ifdef(CONFIG_HAS_CMSIS_CORE_M Core)

add_subdirectory_ifdef(CONFIG_HAS_CMSIS_CORE_R Core_R)

CMSIS/Core_R/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0



zephyr_include_directories(Include)



# As of CMSIS v5.6.0, __PROGRAM_START is to indicate whether the

# ARM vendor or the OS supplies data/bss init routine, otherwise

# the default data/bss init routine for the selected toolchain is

# added. We set the macro in build-time to guarantee compatibility

# with all existing ARM platforms.



zephyr_compile_definitions(__PROGRAM_START)

CMSIS/Core_R/Include/cmsis_compiler.h

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/**************************************************************************//**

 * @file     cmsis_compiler.h

 * @brief    CMSIS compiler specific macros, functions, instructions

 * @version  V1.0.2

 * @date     10. January 2018

 ******************************************************************************/

/*

 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *

 * Licensed under the Apache License, Version 2.0 (the License); you may

 * not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 * www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an AS IS BASIS, WITHOUT

 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 */



#ifndef __CMSIS_COMPILER_H

#define __CMSIS_COMPILER_H



#include <stdint.h>



/*

 * Arm Compiler 4/5

 */

#if   defined ( __CC_ARM )

  #include "cmsis_armcc.h"





/*

 * Arm Compiler 6 (armclang)

 */

#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

  #include "cmsis_armclang.h"





/*

 * GNU Compiler

 */

#elif defined ( __GNUC__ )

  #include "cmsis_gcc.h"





/*

 * IAR Compiler

 */

#elif defined ( __ICCARM__ )

  #include "cmsis_iccarm.h"





/*

 * TI Arm Compiler

 */

#elif defined ( __TI_ARM__ )

  #include <cmsis_ccs.h>



  #ifndef   __ASM

    #define __ASM                     __asm

  #endif

  #ifndef   __INLINE

    #define __INLINE                  inline

  #endif

  #ifndef   __STATIC_INLINE

    #define __STATIC_INLINE           static inline

  #endif

  #ifndef   __STATIC_INLINE

    #define __STATIC_INLINE           static inline

  #endif

  #ifndef   __STATIC_FORCEINLINE

    #define __STATIC_FORCEINLINE      __STATIC_INLINE

  #endif

  #ifndef   __NO_RETURN

    #define __NO_RETURN               __attribute__((noreturn))

  #endif

  #ifndef   CMSIS_DEPRECATED

    #define CMSIS_DEPRECATED          __attribute__((deprecated))

  #endif

  #ifndef   __USED

    #define __USED                    __attribute__((used))

  #endif

  #ifndef   __WEAK

    #define __WEAK                    __attribute__((weak))

  #endif

  #ifndef   __UNALIGNED_UINT32

    struct __attribute__((packed)) T_UINT32 { uint32_t v; };

    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)

  #endif

  #ifndef   __ALIGNED

    #define __ALIGNED(x)              __attribute__((aligned(x)))

  #endif

  #ifndef   __PACKED

    #define __PACKED                  __attribute__((packed))

  #endif

  #ifndef   __COMPILER_BARRIER

    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.

    #define __COMPILER_BARRIER()      (void)0

  #endif





/*

 * TASKING Compiler

 */

#elif defined ( __TASKING__ )

  /*

   * The CMSIS functions have been implemented as intrinsics in the compiler.

   * Please use "carm -?i" to get an up to date list of all intrinsics,

   * Including the CMSIS ones.

   */



  #ifndef   __ASM

    #define __ASM                     __asm

  #endif

  #ifndef   __INLINE

    #define __INLINE                  inline

  #endif

  #ifndef   __STATIC_INLINE

    #define __STATIC_INLINE           static inline

  #endif

  #ifndef   __STATIC_FORCEINLINE

    #define __STATIC_FORCEINLINE      __STATIC_INLINE

  #endif

  #ifndef   __NO_RETURN

    #define __NO_RETURN               __attribute__((noreturn))

  #endif

  #ifndef   CMSIS_DEPRECATED

    #define CMSIS_DEPRECATED          __attribute__((deprecated))

  #endif

  #ifndef   __USED

    #define __USED                    __attribute__((used))

  #endif

  #ifndef   __WEAK

    #define __WEAK                    __attribute__((weak))

  #endif

  #ifndef   __UNALIGNED_UINT32

    struct __packed__ T_UINT32 { uint32_t v; };

    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)

  #endif

  #ifndef   __ALIGNED

    #define __ALIGNED(x)              __align(x)

  #endif

  #ifndef   __PACKED

    #define __PACKED                  __packed__

  #endif

  #ifndef   __COMPILER_BARRIER

    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.

    #define __COMPILER_BARRIER()      (void)0

  #endif





/*

 * COSMIC Compiler

 */

#elif defined ( __CSMC__ )

   #include <cmsis_csm.h>



 #ifndef   __ASM

    #define __ASM                     _asm

  #endif

  #ifndef   __INLINE

    #define __INLINE                  inline

  #endif

  #ifndef   __STATIC_INLINE

    #define __STATIC_INLINE           static inline

  #endif

  #ifndef   __STATIC_FORCEINLINE

    #define __STATIC_FORCEINLINE      __STATIC_INLINE

  #endif

  #ifndef   __NO_RETURN

    // NO RETURN is automatically detected hence no warning here

    #define __NO_RETURN

  #endif

  #ifndef   __USED

    #warning No compiler specific solution for __USED. __USED is ignored.

    #define __USED

  #endif

  #ifndef   CMSIS_DEPRECATED

    #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.

    #define CMSIS_DEPRECATED

  #endif

  #ifndef   __WEAK

    #define __WEAK                    __weak

  #endif

  #ifndef   __UNALIGNED_UINT32

    @packed struct T_UINT32 { uint32_t v; };

    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)

  #endif

  #ifndef   __ALIGNED

    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.

    #define __ALIGNED(x)

  #endif

  #ifndef   __PACKED

    #define __PACKED                  @packed

  #endif

  #ifndef   __COMPILER_BARRIER

    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.

    #define __COMPILER_BARRIER()      (void)0

  #endif





#else

  #error Unknown compiler.

#endif





#endif /* __CMSIS_COMPILER_H */

CMSIS/Core_R/Include/cmsis_cp15.h

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/**************************************************************************//**

 * @file     cmsis_cp15.h for CMSIS-Core(R)

 * @brief    CMSIS compiler specific macros, functions, instructions

 * @version  V1.0.0

 * @date     17. Oct 2019

 ******************************************************************************/

/*

 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.

 * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>

 *

 * SPDX-License-Identifier: Apache-2.0

 *

 * Licensed under the Apache License, Version 2.0 (the License); you may

 * not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 * www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an AS IS BASIS, WITHOUT

 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 */



#if   defined ( __ICCARM__ )

  #pragma system_include         /* treat file as system include file for MISRA check */

#elif defined (__clang__)

  #pragma clang system_header   /* treat file as system include file */

#endif



#ifndef __CMSIS_CP15_H

#define __CMSIS_CP15_H



/** \brief  Get ACTLR

    \return               Auxiliary Control register value

 */

__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 1, 0, 1);

  return(result);

}



/** \brief  Set ACTLR

    \param [in]    actlr  Auxiliary Control value to set

 */

__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)

{

  __set_CP(15, 0, actlr, 1, 0, 1);

}



/** \brief  Get CPACR

    \return               Coprocessor Access Control register value

 */

__STATIC_FORCEINLINE uint32_t __get_CPACR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 1, 0, 2);

  return result;

}



/** \brief  Set CPACR

    \param [in]    cpacr  Coprocessor Access Control value to set

 */

__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)

{

  __set_CP(15, 0, cpacr, 1, 0, 2);

}



/** \brief  Get DFSR

    \return               Data Fault Status Register value

 */

__STATIC_FORCEINLINE uint32_t __get_DFSR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 5, 0, 0);

  return result;

}



/** \brief  Set DFSR

    \param [in]    dfsr  Data Fault Status value to set

 */

__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)

{

  __set_CP(15, 0, dfsr, 5, 0, 0);

}



/** \brief  Get IFSR

    \return               Instruction Fault Status Register value

 */

__STATIC_FORCEINLINE uint32_t __get_IFSR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 5, 0, 1);

  return result;

}



/** \brief  Set IFSR

    \param [in]    ifsr  Instruction Fault Status value to set

 */

__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)

{

  __set_CP(15, 0, ifsr, 5, 0, 1);

}



#if (defined(__CORTEX_R) && (__CORTEX_R == 52U)) || \

    defined(DOXYGEN)



/** \brief  Get ISR

    \return               Interrupt Status Register value

 */

__STATIC_FORCEINLINE uint32_t __get_ISR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 12, 1, 0);

  return result;

}



#endif



/** \brief  Get CBAR

    \return               Configuration Base Address register value

 */

__STATIC_FORCEINLINE uint32_t __get_CBAR(void)

{

  uint32_t result;

  __get_CP(15, 4, result, 15, 0, 0);

  return result;

}



/** \brief  Set SCTLR



    This function assigns the given value to the System Control Register.



    \param [in]    sctlr  System Control Register value to set

 */

__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)

{

  __set_CP(15, 0, sctlr, 1, 0, 0);

}



/** \brief  Get SCTLR

    \return               System Control Register value

 */

__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 1, 0, 0);

  return result;

}



/** \brief  Set ACTRL

    \param [in]    actrl  Auxiliary Control Register value to set

 */

__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)

{

  __set_CP(15, 0, actrl, 1, 0, 1);

}



/** \brief  Get ACTRL

    \return               Auxiliary Control Register value

 */

__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 1, 0, 1);

  return result;

}



/** \brief  Get MPIDR



    This function returns the value of the Multiprocessor Affinity Register.



    \return               Multiprocessor Affinity Register value

 */

__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 0, 0, 5);

  return result;

}



/** \brief  Get VBAR



    This function returns the value of the Vector Base Address Register.



    \return               Vector Base Address Register

 */

__STATIC_FORCEINLINE uint32_t __get_VBAR(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 12, 0, 0);

  return result;

}



/** \brief  Set VBAR



    This function assigns the given value to the Vector Base Address Register.



    \param [in]    vbar  Vector Base Address Register value to set

 */

__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)

{

  __set_CP(15, 0, vbar, 12, 0, 0);

}



#if (defined(__CORTEX_R) && (__CORTEX_R == 52U) && \

    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \

    defined(DOXYGEN)



/** \brief  Set CNTFRQ



  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).



  \param [in]    value  CNTFRQ Register value to set

*/

__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)

{

  __set_CP(15, 0, value, 14, 0, 0);

}



/** \brief  Get CNTFRQ



    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).



    \return               CNTFRQ Register value

 */

__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 14, 0 , 0);

  return result;

}



/** \brief  Set CNTP_TVAL



  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).



  \param [in]    value  CNTP_TVAL Register value to set

*/

__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)

{

  __set_CP(15, 0, value, 14, 2, 0);

}



/** \brief  Get CNTP_TVAL



    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).



    \return               CNTP_TVAL Register value

 */

__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 14, 2, 0);

  return result;

}



/** \brief  Get CNTPCT



    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).



    \return               CNTPCT Register value

 */

__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)

{

  uint64_t result;

  __get_CP64(15, 0, result, 14);

  return result;

}



/** \brief  Set CNTP_CVAL



  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).



  \param [in]    value  CNTP_CVAL Register value to set

*/

__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)

{

  __set_CP64(15, 2, value, 14);

}



/** \brief  Get CNTP_CVAL



    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).



    \return               CNTP_CVAL Register value

 */

__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)

{

  uint64_t result;

  __get_CP64(15, 2, result, 14);

  return result;

}



/** \brief  Set CNTP_CTL



  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).



  \param [in]    value  CNTP_CTL Register value to set

*/

__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)

{

  __set_CP(15, 0, value, 14, 2, 1);

}



/** \brief  Get CNTP_CTL register

    \return               CNTP_CTL Register value

 */

__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)

{

  uint32_t result;

  __get_CP(15, 0, result, 14, 2, 1);

  return result;

}



#endif



/** \brief  Set BPIALL.



  Branch Predictor Invalidate All

 */

__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)

{

  __set_CP(15, 0, value, 7, 5, 6);

}



/** \brief  Set ICIALLU



  Instruction Cache Invalidate All

 */

__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)

{

  __set_CP(15, 0, value, 7, 5, 0);

}



/** \brief  Set DCCMVAC



  Data cache clean

 */

__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)

{

  __set_CP(15, 0, value, 7, 10, 1);

}



/** \brief  Set DCIMVAC



  Data cache invalidate

 */

__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)

{

  __set_CP(15, 0, value, 7, 6, 1);

}



/** \brief  Set DCCIMVAC



  Data cache clean and invalidate

 */

__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)

{

  __set_CP(15, 0, value, 7, 14, 1);

}



/** \brief  Set CSSELR

 */

__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)

{

//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");

  __set_CP(15, 2, value, 0, 0, 0);

}



/** \brief  Get CSSELR

    \return CSSELR Register value

 */

__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)

{

  uint32_t result;

//  __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");

  __get_CP(15, 2, result, 0, 0, 0);

  return result;

}



/** \brief  Set CCSIDR

    \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.

 */

CMSIS_DEPRECATED

__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)

{

  __set_CSSELR(value);

}



/** \brief  Get CCSIDR

    \return CCSIDR Register value

 */

__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)

{

  uint32_t result;

//  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");

  __get_CP(15, 1, result, 0, 0, 0);

  return result;

}



/** \brief  Get CLIDR

    \return CLIDR Register value

 */

__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)

{

  uint32_t result;

//  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");

  __get_CP(15, 1, result, 0, 0, 1);

  return result;

}



/** \brief  Set DCISW

 */

__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)

{

//  __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")

  __set_CP(15, 0, value, 7, 6, 2);

}



/** \brief  Set DCCSW

 */

__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)

{

//  __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")

  __set_CP(15, 0, value, 7, 10, 2);

}



/** \brief  Set DCCISW

 */

__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)

{

//  __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")

  __set_CP(15, 0, value, 7, 14, 2);

}



#endif

CMSIS/Core_R/Include/cmsis_gcc.h

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