Core-M: Import CMSIS-Core(M) 5.4.0 (CMSIS 5.7.0) (0e3e44cb) · Commits · Wenxi XU / cmsis

CMSIS/Core/Include/cachel1_armv7.h

0 → 100644

+411 −0

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		/******************************************************************************
		* @file cachel1_armv7.h
		* @brief CMSIS Level 1 Cache API for Armv7-M and later
		* @version V1.0.0
		* @date 03. March 2020
		******************************************************************************/
		/*
		* Copyright (c) 2020 Arm Limited. All rights reserved.
		*
		* SPDX-License-Identifier: Apache-2.0
		*
		* Licensed under the Apache License, Version 2.0 (the License); you may
		* not use this file except in compliance with the License.
		* You may obtain a copy of the License at
		*
		* www.apache.org/licenses/LICENSE-2.0
		*
		* Unless required by applicable law or agreed to in writing, software
		* distributed under the License is distributed on an AS IS BASIS, WITHOUT
		* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
		* See the License for the specific language governing permissions and
		* limitations under the License.
		*/

		#if defined ( __ICCARM__ )
		#pragma system_include /* treat file as system include file for MISRA check */
		#elif defined (__clang__)
		#pragma clang system_header /* treat file as system include file */
		#endif

		#ifndef ARM_CACHEL1_ARMV7_H
		#define ARM_CACHEL1_ARMV7_H

		/**
		\ingroup CMSIS_Core_FunctionInterface
		\defgroup CMSIS_Core_CacheFunctions Cache Functions
		\brief Functions that configure Instruction and Data cache.
		@{
		*/

		/* Cache Size ID Register Macros */
		#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
		#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )

		#ifndef __SCB_DCACHE_LINE_SIZE
		#define __SCB_DCACHE_LINE_SIZE 32U /!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR /
		#endif

		#ifndef __SCB_ICACHE_LINE_SIZE
		#define __SCB_ICACHE_LINE_SIZE 32U /!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR /
		#endif

		/**
		\brief Enable I-Cache
		\details Turns on I-Cache
		*/
		__STATIC_FORCEINLINE void SCB_EnableICache (void)
		{
		#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
		if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */

		__DSB();
		__ISB();
		SCB->ICIALLU = 0UL; /* invalidate I-Cache */
		__DSB();
		__ISB();
		SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief Disable I-Cache
		\details Turns off I-Cache
		*/
		__STATIC_FORCEINLINE void SCB_DisableICache (void)
		{
		#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
		__DSB();
		__ISB();
		SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
		SCB->ICIALLU = 0UL; /* invalidate I-Cache */
		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief Invalidate I-Cache
		\details Invalidates I-Cache
		*/
		__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
		{
		#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
		__DSB();
		__ISB();
		SCB->ICIALLU = 0UL;
		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief I-Cache Invalidate by address
		\details Invalidates I-Cache for the given address.
		I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
		I-Cache memory blocks which are part of given address + given size are invalidated.
		\param[in] addr address
		\param[in] isize size of memory block (in number of bytes)
		*/
		__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
		{
		#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
		if ( isize > 0 ) {
		int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
		uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;

		__DSB();

		do {
		SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
		op_addr += __SCB_ICACHE_LINE_SIZE;
		op_size -= __SCB_ICACHE_LINE_SIZE;
		} while ( op_size > 0 );

		__DSB();
		__ISB();
		}
		#endif
		}


		/**
		\brief Enable D-Cache
		\details Turns on D-Cache
		*/
		__STATIC_FORCEINLINE void SCB_EnableDCache (void)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		uint32_t ccsidr;
		uint32_t sets;
		uint32_t ways;

		if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */

		SCB->CSSELR = 0U; /* select Level 1 data cache */
		__DSB();

		ccsidr = SCB->CCSIDR;

		/* invalidate D-Cache */
		sets = (uint32_t)(CCSIDR_SETS(ccsidr));
		do {
		ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
		do {
		SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
		((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
		#if defined ( __CC_ARM )
		__schedule_barrier();
		#endif
		} while (ways-- != 0U);
		} while(sets-- != 0U);
		__DSB();

		SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */

		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief Disable D-Cache
		\details Turns off D-Cache
		*/
		__STATIC_FORCEINLINE void SCB_DisableDCache (void)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		uint32_t ccsidr;
		uint32_t sets;
		uint32_t ways;

		SCB->CSSELR = 0U; /* select Level 1 data cache */
		__DSB();

		SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
		__DSB();

		ccsidr = SCB->CCSIDR;

		/* clean & invalidate D-Cache */
		sets = (uint32_t)(CCSIDR_SETS(ccsidr));
		do {
		ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
		do {
		SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
		((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
		#if defined ( __CC_ARM )
		__schedule_barrier();
		#endif
		} while (ways-- != 0U);
		} while(sets-- != 0U);

		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief Invalidate D-Cache
		\details Invalidates D-Cache
		*/
		__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		uint32_t ccsidr;
		uint32_t sets;
		uint32_t ways;

		SCB->CSSELR = 0U; /* select Level 1 data cache */
		__DSB();

		ccsidr = SCB->CCSIDR;

		/* invalidate D-Cache */
		sets = (uint32_t)(CCSIDR_SETS(ccsidr));
		do {
		ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
		do {
		SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
		((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
		#if defined ( __CC_ARM )
		__schedule_barrier();
		#endif
		} while (ways-- != 0U);
		} while(sets-- != 0U);

		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief Clean D-Cache
		\details Cleans D-Cache
		*/
		__STATIC_FORCEINLINE void SCB_CleanDCache (void)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		uint32_t ccsidr;
		uint32_t sets;
		uint32_t ways;

		SCB->CSSELR = 0U; /* select Level 1 data cache */
		__DSB();

		ccsidr = SCB->CCSIDR;

		/* clean D-Cache */
		sets = (uint32_t)(CCSIDR_SETS(ccsidr));
		do {
		ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
		do {
		SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
		((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
		#if defined ( __CC_ARM )
		__schedule_barrier();
		#endif
		} while (ways-- != 0U);
		} while(sets-- != 0U);

		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief Clean & Invalidate D-Cache
		\details Cleans and Invalidates D-Cache
		*/
		__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		uint32_t ccsidr;
		uint32_t sets;
		uint32_t ways;

		SCB->CSSELR = 0U; /* select Level 1 data cache */
		__DSB();

		ccsidr = SCB->CCSIDR;

		/* clean & invalidate D-Cache */
		sets = (uint32_t)(CCSIDR_SETS(ccsidr));
		do {
		ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
		do {
		SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
		((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
		#if defined ( __CC_ARM )
		__schedule_barrier();
		#endif
		} while (ways-- != 0U);
		} while(sets-- != 0U);

		__DSB();
		__ISB();
		#endif
		}


		/**
		\brief D-Cache Invalidate by address
		\details Invalidates D-Cache for the given address.
		D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
		D-Cache memory blocks which are part of given address + given size are invalidated.
		\param[in] addr address
		\param[in] dsize size of memory block (in number of bytes)
		*/
		__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		if ( dsize > 0 ) {
		int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
		uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

		__DSB();

		do {
		SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
		op_addr += __SCB_DCACHE_LINE_SIZE;
		op_size -= __SCB_DCACHE_LINE_SIZE;
		} while ( op_size > 0 );

		__DSB();
		__ISB();
		}
		#endif
		}


		/**
		\brief D-Cache Clean by address
		\details Cleans D-Cache for the given address
		D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
		D-Cache memory blocks which are part of given address + given size are cleaned.
		\param[in] addr address
		\param[in] dsize size of memory block (in number of bytes)
		*/
		__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		if ( dsize > 0 ) {
		int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
		uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

		__DSB();

		do {
		SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
		op_addr += __SCB_DCACHE_LINE_SIZE;
		op_size -= __SCB_DCACHE_LINE_SIZE;
		} while ( op_size > 0 );

		__DSB();
		__ISB();
		}
		#endif
		}


		/**
		\brief D-Cache Clean and Invalidate by address
		\details Cleans and invalidates D_Cache for the given address
		D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
		D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
		\param[in] addr address (aligned to 32-byte boundary)
		\param[in] dsize size of memory block (in number of bytes)
		*/
		__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
		{
		#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
		if ( dsize > 0 ) {
		int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
		uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

		__DSB();

		do {
		SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
		op_addr += __SCB_DCACHE_LINE_SIZE;
		op_size -= __SCB_DCACHE_LINE_SIZE;
		} while ( op_size > 0 );

		__DSB();
		__ISB();
		}
		#endif
		}

		/@} end of CMSIS_Core_CacheFunctions /

		#endif /* ARM_CACHEL1_ARMV7_H */

CMSIS/Core/Include/cmsis_armcc.h

+10 −19

Original line number	Diff line number	Diff line
		/************************************************************************//
		* @file cmsis_armcc.h
		* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
		* @version V5.1.0
		* @date 08. May 2019
		* @version V5.2.1
		* @date 26. March 2020
		******************************************************************************/
		/*
		* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
		* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
		*
		* SPDX-License-Identifier: Apache-2.0
		*
		@@ -46,6 +46,7 @@

		/* __ARM_ARCH_8M_BASE__ not applicable */
		/* __ARM_ARCH_8M_MAIN__ not applicable */
		/* __ARM_ARCH_8_1M_MAIN__ not applicable */

		/* CMSIS compiler control DSP macros */
		#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
		@@ -127,7 +128,7 @@
		#endif

		#ifndef __VECTOR_TABLE_ATTRIBUTE
		#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
		#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
		#endif

		/* ########################### Core Function Access ########################### */
		@@ -444,33 +445,21 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
		so that all instructions following the ISB are fetched from cache or memory,
		after the instruction has been completed.
		*/
		#define __ISB() do {\
		__schedule_barrier();\
		__isb(0xF);\
		__schedule_barrier();\
		} while (0U)
		#define __ISB() __isb(0xF)

		/**
		\brief Data Synchronization Barrier
		\details Acts as a special kind of Data Memory Barrier.
		It completes when all explicit memory accesses before this instruction complete.
		*/
		#define __DSB() do {\
		__schedule_barrier();\
		__dsb(0xF);\
		__schedule_barrier();\
		} while (0U)
		#define __DSB() __dsb(0xF)

		/**
		\brief Data Memory Barrier
		\details Ensures the apparent order of the explicit memory operations before
		and after the instruction, without ensuring their completion.
		*/
		#define __DMB() do {\
		__schedule_barrier();\
		__dmb(0xF);\
		__schedule_barrier();\
		} while (0U)
		#define __DMB() __dmb(0xF)


		/**
		@@ -887,6 +876,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
		#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
		((int64_t)(ARG3) << 32U) ) >> 32U))

		#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))

		#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
		/@} end of group CMSIS_SIMD_intrinsics /

CMSIS/Core/Include/cmsis_armclang.h

+72 −49

File changed.

Preview size limit exceeded, changes collapsed.

CMSIS/Core/Include/cmsis_armclang_ltm.h

+12 −10

Original line number	Diff line number	Diff line
		/************************************************************************//
		* @file cmsis_armclang_ltm.h
		* @brief CMSIS compiler armclang (Arm Compiler 6) header file
		* @version V1.2.0
		* @date 08. May 2019
		* @version V1.3.0
		* @date 26. March 2020
		******************************************************************************/
		/*
		* Copyright (c) 2018-2019 Arm Limited. All rights reserved.
		* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
		*
		* SPDX-License-Identifier: Apache-2.0
		*
		@@ -133,7 +133,7 @@
		#endif

		#ifndef __VECTOR_TABLE_ATTRIBUTE
		#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
		#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
		#endif


		@@ -1218,7 +1218,7 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
		{
		uint32_t result;

		__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
		__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
		return ((uint8_t) result);
		}

		@@ -1233,7 +1233,7 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
		{
		uint32_t result;

		__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
		__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
		return ((uint16_t) result);
		}

		@@ -1248,7 +1248,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
		{
		uint32_t result;

		__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
		__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
		return(result);
		}

		@@ -1261,7 +1261,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
		*/
		__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
		{
		__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
		__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
		}


		@@ -1273,7 +1273,7 @@ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
		*/
		__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
		{
		__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
		__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
		}


		@@ -1285,7 +1285,7 @@ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
		*/
		__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
		{
		__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
		__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
		}


		@@ -1876,6 +1876,8 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
		#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
		((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )

		#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))

		__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
		{
		int32_t result;

CMSIS/Core/Include/cmsis_compiler.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -280,3 +280,4 @@


		#endif /* __CMSIS_COMPILER_H */

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