Commit 1d9e38ad authored by Christophe Favergeon's avatar Christophe Favergeon
Browse files

Reworked FFT initializations to make the work of the linker easier. 

New FFT initialization functions to make it easier for the linker
to optimize the code size when the library is used as a static
library and can't be rebuilt.

Compilation directives for code size optimizations have been removed.
parent af5294db

.gitignore

+2 −0
Original line number Diff line number Diff line
@@ -29,3 +29,5 @@ __pycache__/ 
.DS_Store

.swiftpm/

build/

Examples/cmsis_build/RTE/_Release*

Testing/cmsis_build/RTE/_Release*
 
 No newline at end of file

Doxygen/dsp.dxy.in

+21 −1
Original line number Diff line number Diff line
@@ -1003,7 +1003,27 @@ EXCLUDE_SYMBOLS = S \ 
   arm_cfft_sR_q31_* \

   arm_cfft_sR_q15_* \

   any32x4_t \

   any32x2_t

   any32x2_t \

   CFFTINIT_F32 \

   CFFT_UNDEF_INIT_F32 \

   CFFTINIT_F16 \

   CFFT_UNDEF_INIT_F16 \

   CFFTINIT_F64 \

   CFFT_UNDEF_INIT_F64 \

   CFFTINIT_Q15 \

   CFFT_UNDEF_INIT_Q15 \

   CFFTINIT_Q31 \

   CFFT_UNDEF_INIT_Q31 \

   RFFTINIT_Q31 \

   RFFT_UNDEF_INIT_Q31 \

   RFFTINIT_Q15 \

   RFFT_UNDEF_INIT_Q15 \

   MFCC_INIT_F32 \

   MFCC_INIT_F16 \

   MFCC_INIT_Q15 \

   MFCC_INIT_Q31 \

   FFTINIT





# The EXAMPLE_PATH tag can be used to specify one or more files or directories

# that contain example code fragments that are included (see the \include

Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c

+1 −1
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@@ -132,7 +132,7 @@ int32_t main(void) 


  status = ARM_MATH_SUCCESS;



  status=arm_cfft_init_f32(&varInstCfftF32,fftSize);

  status=arm_cfft_init_1024_f32(&varInstCfftF32);



  /* Process the data through the CFFT/CIFFT module */

  arm_cfft_f32(&varInstCfftF32, testInput_f32_10khz, ifftFlag, doBitReverse);

Examples/cmsis_build/.gitignore

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@@ -3,4 +3,4 @@ 
*@*

.*@*

*.cbuild.yml 

*.bat

Examples/cmsis_build/RTE/Device/ARMCM0P/gcc_arm.ld

0 → 100644
+296 −0
Original line number Diff line number Diff line 
/******************************************************************************

 * @file     gcc_arm.ld

 * @brief    GNU Linker Script for Cortex-M based device

 * @version  V2.1.0

 * @date     04. August 2020

 ******************************************************************************/

/*

 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *

 * Licensed under the Apache License, Version 2.0 (the License); you may

 * not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 * www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an AS IS BASIS, WITHOUT

 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 */



/*

 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------

 */



/*---------------------- Flash Configuration ----------------------------------

  <h> Flash Configuration

    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>

    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

  -----------------------------------------------------------------------------*/

__ROM_BASE = 0x00000000;

__ROM_SIZE = 0x00040000;



/*--------------------- Embedded RAM Configuration ----------------------------

  <h> RAM Configuration

    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>

    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

 -----------------------------------------------------------------------------*/

__RAM_BASE = 0x20000000;

__RAM_SIZE = 0x00020000;



/*--------------------- Stack / Heap Configuration ----------------------------

  <h> Stack / Heap Configuration

    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>

    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

  -----------------------------------------------------------------------------*/

__STACK_SIZE = 0x00000400;

__HEAP_SIZE  = 0x00000C00;



/*

 *-------------------- <<< end of configuration section >>> -------------------

 */



MEMORY

{

  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE

  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE

}



/* Linker script to place sections and symbol values. Should be used together

 * with other linker script that defines memory regions FLASH and RAM.

 * It references following symbols, which must be defined in code:

 *   Reset_Handler : Entry of reset handler

 *

 * It defines following symbols, which code can use without definition:

 *   __exidx_start

 *   __exidx_end

 *   __copy_table_start__

 *   __copy_table_end__

 *   __zero_table_start__

 *   __zero_table_end__

 *   __etext

 *   __data_start__

 *   __preinit_array_start

 *   __preinit_array_end

 *   __init_array_start

 *   __init_array_end

 *   __fini_array_start

 *   __fini_array_end

 *   __data_end__

 *   __bss_start__

 *   __bss_end__

 *   __end__

 *   end

 *   __HeapLimit

 *   __StackLimit

 *   __StackTop

 *   __stack

 */

ENTRY(Reset_Handler)



SECTIONS

{

  .text :

  {

    KEEP(*(.vectors))

    *(.text*)



    KEEP(*(.init))

    KEEP(*(.fini))



    /* .ctors */

    *crtbegin.o(.ctors)

    *crtbegin?.o(.ctors)

    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

    *(SORT(.ctors.*))

    *(.ctors)



    /* .dtors */

    *crtbegin.o(.dtors)

    *crtbegin?.o(.dtors)

    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

    *(SORT(.dtors.*))

    *(.dtors)



    *(.rodata*)



    KEEP(*(.eh_frame*))

  } > FLASH



  /*

   * SG veneers:

   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address

   * must be set, either with the command line option --section-start or in a linker script,

   * to indicate where to place these veneers in memory.

   */

/*

  .gnu.sgstubs :

  {

    . = ALIGN(32);

  } > FLASH

*/

  .ARM.extab :

  {

    *(.ARM.extab* .gnu.linkonce.armextab.*)

  } > FLASH



  __exidx_start = .;

  .ARM.exidx :

  {

    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

  } > FLASH

  __exidx_end = .;



  .copy.table :

  {

    . = ALIGN(4);

    __copy_table_start__ = .;



    LONG (__etext)

    LONG (__data_start__)

    LONG ((__data_end__ - __data_start__) / 4)



    /* Add each additional data section here */

/*

    LONG (__etext2)

    LONG (__data2_start__)

    LONG ((__data2_end__ - __data2_start__) / 4)

*/

    __copy_table_end__ = .;

  } > FLASH



  .zero.table :

  {

    . = ALIGN(4);

    __zero_table_start__ = .;

    /* Add each additional bss section here */

/*

    LONG (__bss2_start__)

    LONG ((__bss2_end__ - __bss2_start__) / 4)

*/

    __zero_table_end__ = .;

  } > FLASH



  /**

   * Location counter can end up 2byte aligned with narrow Thumb code but

   * __etext is assumed by startup code to be the LMA of a section in RAM

   * which must be 4byte aligned 

   */

  __etext = ALIGN (4);



  .data : AT (__etext)

  {

    __data_start__ = .;

    *(vtable)

    *(.data)

    *(.data.*)



    . = ALIGN(4);

    /* preinit data */

    PROVIDE_HIDDEN (__preinit_array_start = .);

    KEEP(*(.preinit_array))

    PROVIDE_HIDDEN (__preinit_array_end = .);



    . = ALIGN(4);

    /* init data */

    PROVIDE_HIDDEN (__init_array_start = .);

    KEEP(*(SORT(.init_array.*)))

    KEEP(*(.init_array))

    PROVIDE_HIDDEN (__init_array_end = .);



    . = ALIGN(4);

    /* finit data */

    PROVIDE_HIDDEN (__fini_array_start = .);

    KEEP(*(SORT(.fini_array.*)))

    KEEP(*(.fini_array))

    PROVIDE_HIDDEN (__fini_array_end = .);



    KEEP(*(.jcr*))

    . = ALIGN(4);

    /* All data end */

    __data_end__ = .;



  } > RAM



  /*

   * Secondary data section, optional

   *

   * Remember to add each additional data section

   * to the .copy.table above to asure proper

   * initialization during startup.

   */

/*

  __etext2 = ALIGN (4);



  .data2 : AT (__etext2)

  {

    . = ALIGN(4);

    __data2_start__ = .;

    *(.data2)

    *(.data2.*)

    . = ALIGN(4);

    __data2_end__ = .;



  } > RAM2

*/



  .bss :

  {

    . = ALIGN(4);

    __bss_start__ = .;

    *(.bss)

    *(.bss.*)

    *(COMMON)

    . = ALIGN(4);

    __bss_end__ = .;

  } > RAM AT > RAM



  /*

   * Secondary bss section, optional

   *

   * Remember to add each additional bss section

   * to the .zero.table above to asure proper

   * initialization during startup.

   */

/*

  .bss2 :

  {

    . = ALIGN(4);

    __bss2_start__ = .;

    *(.bss2)

    *(.bss2.*)

    . = ALIGN(4);

    __bss2_end__ = .;

  } > RAM2 AT > RAM2

*/



  .heap (COPY) :

  {

    . = ALIGN(8);

    __end__ = .;

    PROVIDE(end = .);

    . = . + __HEAP_SIZE;

    . = ALIGN(8);

    __HeapLimit = .;

  } > RAM



  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :

  {

    . = ALIGN(8);

    __StackLimit = .;

    . = . + __STACK_SIZE;

    . = ALIGN(8);

    __StackTop = .;

  } > RAM

  PROVIDE(__stack = __StackTop);



  /* Check if data + heap + stack exceeds RAM limit */

  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

}

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