Commit 03222992 authored by Christophe Favergeon's avatar Christophe Favergeon
Browse files

Migrated examples and tests to CMSIS build tools 2.0

parent 540161c1

Examples/.gitignore

+3 −1
Original line number Diff line number Diff line
@@ -4,3 +4,5 @@ EventRecorderStub.scvd 
_ARMCM0/

cmsis_build/tmp

cmsis_build/out

cmsis_build/examples_ac6.cbuild-idx.yml

*.cbuild.yml

Examples/cmsis_build/RTE/Device/ARMCM0P/gcc_arm.ld

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+0 −296
Original line number Diff line number Diff line 
/******************************************************************************

 * @file     gcc_arm.ld

 * @brief    GNU Linker Script for Cortex-M based device

 * @version  V2.1.0

 * @date     04. August 2020

 ******************************************************************************/

/*

 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *

 * Licensed under the Apache License, Version 2.0 (the License); you may

 * not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 * www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an AS IS BASIS, WITHOUT

 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 */



/*

 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------

 */



/*---------------------- Flash Configuration ----------------------------------

  <h> Flash Configuration

    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>

    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

  -----------------------------------------------------------------------------*/

__ROM_BASE = 0x00000000;

__ROM_SIZE = 0x00040000;



/*--------------------- Embedded RAM Configuration ----------------------------

  <h> RAM Configuration

    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>

    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

 -----------------------------------------------------------------------------*/

__RAM_BASE = 0x20000000;

__RAM_SIZE = 0x00020000;



/*--------------------- Stack / Heap Configuration ----------------------------

  <h> Stack / Heap Configuration

    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>

    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

  -----------------------------------------------------------------------------*/

__STACK_SIZE = 0x00000400;

__HEAP_SIZE  = 0x00000C00;



/*

 *-------------------- <<< end of configuration section >>> -------------------

 */



MEMORY

{

  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE

  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE

}



/* Linker script to place sections and symbol values. Should be used together

 * with other linker script that defines memory regions FLASH and RAM.

 * It references following symbols, which must be defined in code:

 *   Reset_Handler : Entry of reset handler

 *

 * It defines following symbols, which code can use without definition:

 *   __exidx_start

 *   __exidx_end

 *   __copy_table_start__

 *   __copy_table_end__

 *   __zero_table_start__

 *   __zero_table_end__

 *   __etext

 *   __data_start__

 *   __preinit_array_start

 *   __preinit_array_end

 *   __init_array_start

 *   __init_array_end

 *   __fini_array_start

 *   __fini_array_end

 *   __data_end__

 *   __bss_start__

 *   __bss_end__

 *   __end__

 *   end

 *   __HeapLimit

 *   __StackLimit

 *   __StackTop

 *   __stack

 */

ENTRY(Reset_Handler)



SECTIONS

{

  .text :

  {

    KEEP(*(.vectors))

    *(.text*)



    KEEP(*(.init))

    KEEP(*(.fini))



    /* .ctors */

    *crtbegin.o(.ctors)

    *crtbegin?.o(.ctors)

    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

    *(SORT(.ctors.*))

    *(.ctors)



    /* .dtors */

    *crtbegin.o(.dtors)

    *crtbegin?.o(.dtors)

    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

    *(SORT(.dtors.*))

    *(.dtors)



    *(.rodata*)



    KEEP(*(.eh_frame*))

  } > FLASH



  /*

   * SG veneers:

   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address

   * must be set, either with the command line option --section-start or in a linker script,

   * to indicate where to place these veneers in memory.

   */

/*

  .gnu.sgstubs :

  {

    . = ALIGN(32);

  } > FLASH

*/

  .ARM.extab :

  {

    *(.ARM.extab* .gnu.linkonce.armextab.*)

  } > FLASH



  __exidx_start = .;

  .ARM.exidx :

  {

    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

  } > FLASH

  __exidx_end = .;



  .copy.table :

  {

    . = ALIGN(4);

    __copy_table_start__ = .;



    LONG (__etext)

    LONG (__data_start__)

    LONG ((__data_end__ - __data_start__) / 4)



    /* Add each additional data section here */

/*

    LONG (__etext2)

    LONG (__data2_start__)

    LONG ((__data2_end__ - __data2_start__) / 4)

*/

    __copy_table_end__ = .;

  } > FLASH



  .zero.table :

  {

    . = ALIGN(4);

    __zero_table_start__ = .;

    /* Add each additional bss section here */

/*

    LONG (__bss2_start__)

    LONG ((__bss2_end__ - __bss2_start__) / 4)

*/

    __zero_table_end__ = .;

  } > FLASH



  /**

   * Location counter can end up 2byte aligned with narrow Thumb code but

   * __etext is assumed by startup code to be the LMA of a section in RAM

   * which must be 4byte aligned 

   */

  __etext = ALIGN (4);



  .data : AT (__etext)

  {

    __data_start__ = .;

    *(vtable)

    *(.data)

    *(.data.*)



    . = ALIGN(4);

    /* preinit data */

    PROVIDE_HIDDEN (__preinit_array_start = .);

    KEEP(*(.preinit_array))

    PROVIDE_HIDDEN (__preinit_array_end = .);



    . = ALIGN(4);

    /* init data */

    PROVIDE_HIDDEN (__init_array_start = .);

    KEEP(*(SORT(.init_array.*)))

    KEEP(*(.init_array))

    PROVIDE_HIDDEN (__init_array_end = .);



    . = ALIGN(4);

    /* finit data */

    PROVIDE_HIDDEN (__fini_array_start = .);

    KEEP(*(SORT(.fini_array.*)))

    KEEP(*(.fini_array))

    PROVIDE_HIDDEN (__fini_array_end = .);



    KEEP(*(.jcr*))

    . = ALIGN(4);

    /* All data end */

    __data_end__ = .;



  } > RAM



  /*

   * Secondary data section, optional

   *

   * Remember to add each additional data section

   * to the .copy.table above to asure proper

   * initialization during startup.

   */

/*

  __etext2 = ALIGN (4);



  .data2 : AT (__etext2)

  {

    . = ALIGN(4);

    __data2_start__ = .;

    *(.data2)

    *(.data2.*)

    . = ALIGN(4);

    __data2_end__ = .;



  } > RAM2

*/



  .bss :

  {

    . = ALIGN(4);

    __bss_start__ = .;

    *(.bss)

    *(.bss.*)

    *(COMMON)

    . = ALIGN(4);

    __bss_end__ = .;

  } > RAM AT > RAM



  /*

   * Secondary bss section, optional

   *

   * Remember to add each additional bss section

   * to the .zero.table above to asure proper

   * initialization during startup.

   */

/*

  .bss2 :

  {

    . = ALIGN(4);

    __bss2_start__ = .;

    *(.bss2)

    *(.bss2.*)

    . = ALIGN(4);

    __bss2_end__ = .;

  } > RAM2 AT > RAM2

*/



  .heap (COPY) :

  {

    . = ALIGN(8);

    __end__ = .;

    PROVIDE(end = .);

    . = . + __HEAP_SIZE;

    . = ALIGN(8);

    __HeapLimit = .;

  } > RAM



  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :

  {

    . = ALIGN(8);

    __StackLimit = .;

    . = . + __STACK_SIZE;

    . = ALIGN(8);

    __StackTop = .;

  } > RAM

  PROVIDE(__stack = __StackTop);



  /* Check if data + heap + stack exceeds RAM limit */

  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

}

Examples/cmsis_build/RTE/Device/ARMCM7_DP/gcc_arm.ld

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+0 −296
Original line number Diff line number Diff line 
/******************************************************************************

 * @file     gcc_arm.ld

 * @brief    GNU Linker Script for Cortex-M based device

 * @version  V2.1.0

 * @date     04. August 2020

 ******************************************************************************/

/*

 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *

 * Licensed under the Apache License, Version 2.0 (the License); you may

 * not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 * www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an AS IS BASIS, WITHOUT

 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 */



/*

 *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------

 */



/*---------------------- Flash Configuration ----------------------------------

  <h> Flash Configuration

    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>

    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

  -----------------------------------------------------------------------------*/

__ROM_BASE = 0x00000000;

__ROM_SIZE = 0x00040000;



/*--------------------- Embedded RAM Configuration ----------------------------

  <h> RAM Configuration

    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>

    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

 -----------------------------------------------------------------------------*/

__RAM_BASE = 0x20000000;

__RAM_SIZE = 0x00020000;



/*--------------------- Stack / Heap Configuration ----------------------------

  <h> Stack / Heap Configuration

    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>

    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>

  </h>

  -----------------------------------------------------------------------------*/

__STACK_SIZE = 0x00000400;

__HEAP_SIZE  = 0x00000C00;



/*

 *-------------------- <<< end of configuration section >>> -------------------

 */



MEMORY

{

  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE

  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE

}



/* Linker script to place sections and symbol values. Should be used together

 * with other linker script that defines memory regions FLASH and RAM.

 * It references following symbols, which must be defined in code:

 *   Reset_Handler : Entry of reset handler

 *

 * It defines following symbols, which code can use without definition:

 *   __exidx_start

 *   __exidx_end

 *   __copy_table_start__

 *   __copy_table_end__

 *   __zero_table_start__

 *   __zero_table_end__

 *   __etext

 *   __data_start__

 *   __preinit_array_start

 *   __preinit_array_end

 *   __init_array_start

 *   __init_array_end

 *   __fini_array_start

 *   __fini_array_end

 *   __data_end__

 *   __bss_start__

 *   __bss_end__

 *   __end__

 *   end

 *   __HeapLimit

 *   __StackLimit

 *   __StackTop

 *   __stack

 */

ENTRY(Reset_Handler)



SECTIONS

{

  .text :

  {

    KEEP(*(.vectors))

    *(.text*)



    KEEP(*(.init))

    KEEP(*(.fini))



    /* .ctors */

    *crtbegin.o(.ctors)

    *crtbegin?.o(.ctors)

    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

    *(SORT(.ctors.*))

    *(.ctors)



    /* .dtors */

    *crtbegin.o(.dtors)

    *crtbegin?.o(.dtors)

    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

    *(SORT(.dtors.*))

    *(.dtors)



    *(.rodata*)



    KEEP(*(.eh_frame*))

  } > FLASH



  /*

   * SG veneers:

   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address

   * must be set, either with the command line option --section-start or in a linker script,

   * to indicate where to place these veneers in memory.

   */

/*

  .gnu.sgstubs :

  {

    . = ALIGN(32);

  } > FLASH

*/

  .ARM.extab :

  {

    *(.ARM.extab* .gnu.linkonce.armextab.*)

  } > FLASH



  __exidx_start = .;

  .ARM.exidx :

  {

    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

  } > FLASH

  __exidx_end = .;



  .copy.table :

  {

    . = ALIGN(4);

    __copy_table_start__ = .;



    LONG (__etext)

    LONG (__data_start__)

    LONG ((__data_end__ - __data_start__) / 4)



    /* Add each additional data section here */

/*

    LONG (__etext2)

    LONG (__data2_start__)

    LONG ((__data2_end__ - __data2_start__) / 4)

*/

    __copy_table_end__ = .;

  } > FLASH



  .zero.table :

  {

    . = ALIGN(4);

    __zero_table_start__ = .;

    /* Add each additional bss section here */

/*

    LONG (__bss2_start__)

    LONG ((__bss2_end__ - __bss2_start__) / 4)

*/

    __zero_table_end__ = .;

  } > FLASH



  /**

   * Location counter can end up 2byte aligned with narrow Thumb code but

   * __etext is assumed by startup code to be the LMA of a section in RAM

   * which must be 4byte aligned 

   */

  __etext = ALIGN (4);



  .data : AT (__etext)

  {

    __data_start__ = .;

    *(vtable)

    *(.data)

    *(.data.*)



    . = ALIGN(4);

    /* preinit data */

    PROVIDE_HIDDEN (__preinit_array_start = .);

    KEEP(*(.preinit_array))

    PROVIDE_HIDDEN (__preinit_array_end = .);



    . = ALIGN(4);

    /* init data */

    PROVIDE_HIDDEN (__init_array_start = .);

    KEEP(*(SORT(.init_array.*)))

    KEEP(*(.init_array))

    PROVIDE_HIDDEN (__init_array_end = .);



    . = ALIGN(4);

    /* finit data */

    PROVIDE_HIDDEN (__fini_array_start = .);

    KEEP(*(SORT(.fini_array.*)))

    KEEP(*(.fini_array))

    PROVIDE_HIDDEN (__fini_array_end = .);



    KEEP(*(.jcr*))

    . = ALIGN(4);

    /* All data end */

    __data_end__ = .;



  } > RAM



  /*

   * Secondary data section, optional

   *

   * Remember to add each additional data section

   * to the .copy.table above to asure proper

   * initialization during startup.

   */

/*

  __etext2 = ALIGN (4);



  .data2 : AT (__etext2)

  {

    . = ALIGN(4);

    __data2_start__ = .;

    *(.data2)

    *(.data2.*)

    . = ALIGN(4);

    __data2_end__ = .;



  } > RAM2

*/



  .bss :

  {

    . = ALIGN(4);

    __bss_start__ = .;

    *(.bss)

    *(.bss.*)

    *(COMMON)

    . = ALIGN(4);

    __bss_end__ = .;

  } > RAM AT > RAM



  /*

   * Secondary bss section, optional

   *

   * Remember to add each additional bss section

   * to the .zero.table above to asure proper

   * initialization during startup.

   */

/*

  .bss2 :

  {

    . = ALIGN(4);

    __bss2_start__ = .;

    *(.bss2)

    *(.bss2.*)

    . = ALIGN(4);

    __bss2_end__ = .;

  } > RAM2 AT > RAM2

*/



  .heap (COPY) :

  {

    . = ALIGN(8);

    __end__ = .;

    PROVIDE(end = .);

    . = . + __HEAP_SIZE;

    . = ALIGN(8);

    __HeapLimit = .;

  } > RAM



  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :

  {

    . = ALIGN(8);

    __StackLimit = .;

    . = . + __STACK_SIZE;

    . = ALIGN(8);

    __StackTop = .;

  } > RAM

  PROVIDE(__stack = __StackTop);



  /* Check if data + heap + stack exceeds RAM limit */

  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

}

Examples/cmsis_build/RTE/Device/SSE-300-MPS3/region_limits.h

+2 −2
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
#define TOTAL_S_DDR4_SIZE         (0x10000000) /* 256 MB */



/* Heap and Stack sizes for secure and nonsecure applications */

#define HEAP_SIZE                 (0x00001000) /* 1 KiB */

#define STACK_SIZE                (0x00002000) /* 1 KiB */

#define HEAP_SIZE                 (0x00000400) /* 1 KiB */

#define STACK_SIZE                (0x00000400) /* 1 KiB */



#endif /* __REGION_LIMITS_H__ */

Examples/cmsis_build/RTE/Device/SSE-310-MPS3/corstone310_mps3_s.ld

deleted100644 → 0
+0 −193
Original line number Diff line number Diff line 
;/*

; * Copyright (c) 2021-2022 Arm Limited. All rights reserved.

; *

; * Licensed under the Apache License, Version 2.0 (the "License");

; * you may not use this file except in compliance with the License.

; * You may obtain a copy of the License at

; *

; *     http://www.apache.org/licenses/LICENSE-2.0

; *

; * Unless required by applicable law or agreed to in writing, software

; * distributed under the License is distributed on an "AS IS" BASIS,

; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

; * See the License for the specific language governing permissions and

; * limitations under the License.

; *

; *

; * This file is derivative of CMSIS V5.00 gcc_arm.ld

; */



/* Linker script to configure memory regions. */

/* This file will be run trough the pre-processor. */



#include "region_defs.h"



MEMORY

{

  FLASH (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE

  RAM   (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE

}



__heap_size__  = HEAP_SIZE;

__stack_size__ = STACK_SIZE;



/* Library configurations */

GROUP(libgcc.a libc.a libm.a libnosys.a)



ENTRY(Reset_Handler)



SECTIONS

{

    .text :

    {

        KEEP(*(.vectors))

        __Vectors_End = .;

        __Vectors_Size = __Vectors_End - __Vectors;

        __end__ = .;



        *(.text*)



        KEEP(*(.init))

        KEEP(*(.fini))





        /* .ctors */

        *crtbegin.o(.ctors)

        *crtbegin?.o(.ctors)

        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

        *(SORT(.ctors.*))

        *(.ctors)



        /* .dtors */

         *crtbegin.o(.dtors)

         *crtbegin?.o(.dtors)

         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

         *(SORT(.dtors.*))

         *(.dtors)



        *(.rodata*)



        KEEP(*(.eh_frame*))

    } > FLASH



    .ARM.extab :

    {

        *(.ARM.extab* .gnu.linkonce.armextab.*)

    } > FLASH



    __exidx_start = .;

    .ARM.exidx :

    {

        *(.ARM.exidx* .gnu.linkonce.armexidx.*)

    } > FLASH

    __exidx_end = .;



    /* To copy multiple ROM to RAM sections,

     * define etext2/data2_start/data2_end and

     * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps3_an524_ns.S */

    .copy.table :

    {

        . = ALIGN(4);

        __copy_table_start__ = .;

        LONG (__etext)

        LONG (__data_start__)

        LONG ((__data_end__ - __data_start__) / 4)

        LONG (DEFINED(__etext2) ? __etext2 : 0)

        LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)

        LONG (DEFINED(__data2_start__) ? ((__data2_end__ - __data2_start__) / 4) : 0)

        __copy_table_end__ = .;

    } > FLASH



    /* To clear multiple BSS sections,

     * uncomment .zero.table section and,

     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_mps3_an524_ns.S */

    .zero.table :

    {

        . = ALIGN(4);

        __zero_table_start__ = .;

        LONG (__bss_start__)

        LONG ((__bss_end__ - __bss_start__) / 4)

        LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)

        LONG (DEFINED(__bss2_start__) ? ((__bss2_end__ - __bss2_start__) / 4) : 0)

        __zero_table_end__ = .;

    } > FLASH



    __etext = .;



#if defined(BL2_LINKER)

    .tfm_bl2_shared_data : ALIGN(32)

    {

        . += BOOT_TFM_SHARED_DATA_SIZE;

    } > RAM

    Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);

    Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);

#endif



    .data : AT (__etext)

    {

        __data_start__ = .;

        *(vtable)

        *(.data*)



        . = ALIGN(4);

        /* preinit data */

        PROVIDE_HIDDEN (__preinit_array_start = .);

        KEEP(*(.preinit_array))

        PROVIDE_HIDDEN (__preinit_array_end = .);



        . = ALIGN(4);

        /* init data */

        PROVIDE_HIDDEN (__init_array_start = .);

        KEEP(*(SORT(.init_array.*)))

        KEEP(*(.init_array))

        PROVIDE_HIDDEN (__init_array_end = .);





        . = ALIGN(4);

        /* finit data */

        PROVIDE_HIDDEN (__fini_array_start = .);

        KEEP(*(SORT(.fini_array.*)))

        KEEP(*(.fini_array))

        PROVIDE_HIDDEN (__fini_array_end = .);



        KEEP(*(.jcr*))

        . = ALIGN(4);

        /* All data end */

        __data_end__ = .;



    } > RAM

    Image$$ER_DATA$$Base = ADDR(.data);



    .bss :

    {

        . = ALIGN(4);

        __bss_start__ = .;

        *(.bss*)

        *(COMMON)

        . = ALIGN(4);

        __bss_end__ = .;

    } > RAM



    bss_size = __bss_end__ - __bss_start__;



    .msp_stack : ALIGN(32)

    {

        . += __stack_size__;

    } > RAM

    __StackLimit = ADDR(.msp_stack);

    __StackTop = ADDR(.msp_stack) + SIZEOF(.msp_stack);



    .heap : ALIGN(8)

    {

        . = ALIGN(8);

        __end__ = .;

        PROVIDE(end = .);

        __HeapBase = .;

        . += __heap_size__;

        __HeapLimit = .;

        __heap_limit = .; /* Add for _sbrk */

    } > RAM

    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);



    PROVIDE(__stack = __StackTop);

}

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