@@ -6,20 +6,22 @@ Project Team members including YUAN Tong and FAN Qinyuan from class 2018.
## Introduction
Here is a brief introduction of the project, for more details please refer to the **[Project Report](Report/IEEE_report/4x4_multiplier_design.pdf)**, we will first introduce the design of basic gates, adders and the structure of the 4x4 multiplier. Then, we will create a layout for our design. All the procedure are following the Top-to-Down design and Down-to-Top develop.
The project contain two version, standard version and involution version. For standard version is a normal design of multiplier, for involution version, we reduce the area and delay of the multiplier by any method possible, this version can help one achive higher score but cannot be used in real world because the design in just bu-shit.
Here is a brief introduction of the project, for more details please refer to the **[Project Report(standard)](standard/Report/IEEE_report/4x4_multiplier_design.pdf)** and **[Project Report(involution)](involution/Report/IEEE_report/4x4_multiplier_design.pdf)**, we will first introduce the design of basic gates, adders and the structure of the 4x4 multiplier. Then, we will create a layout for our design. All the procedure are following the Top-to-Down design and Down-to-Top develop.
## Project Structure
### Design
We put [design files](Design/multiplier), the [figure of the schematic and layout](Design/Design_figures) and [simulation results](Design/simulation) in [this forder](Design).
In both version, we put [design files](standard/Design/multiplier), the [figure of the schematic and layout](standard/Design/Design_figures) and [simulation results](Design/simulation) in [this forder](standard/Design), the version shown here is standard version because it is more elegant.
@@ -27,6 +29,8 @@ Some important reference files are put here, for example, I have simplify the de
### Report
Here is the Latex source code of the design
### Addition
## Design of each level
@@ -41,14 +45,16 @@ Some important reference files are put here, for example, I have simplify the de
### Area of the Layout
As we tested, the area of the layout is **((-11.2, -95)(53.2, 2)), 6246.8 um2**
As we tested, the area of the layout is \textbf{**((0.39, -52)(62, 0)), 3276um2**}
## Propagation delay
Here we will compare the post-layout delay measurements with the schematic level delay measurement 50f F cap is attached to the output. We apply two set of input to the multiplier so we can get the transfer data of all output. The first set is 0000 x 1111 = 11100001 and the second set is 0010 x 1111 = 00011110. As we measure, the maxmun down-to-up delay is **1ns**and uo-to-down delay is **0.75ns**, the plots are shown in Appendix.
Here we will compare the post-layout delay measurements with the schematic level delay measurement 50f F cap is attached to the output. We apply two set of input to the multiplier so we can get the transfer data of all output. The first set is $0000 \times 1111 = 11100001$ and the second set is $0010 \times 1111 = 00011110$. As we measure, the maxmun down-to-up delay is **1.915ns**for av-extracted view and **1.560ns** for schematic view, uo-to-down delay is **0.96ns** for av-extracted view and **0.773ns** for schematic view, from the data we could found that the delay of schematic view is a little lower than av-extracted view due to omiting of some cap. The plots are shown in Appendix.
## Layout Technic
Here we will introduce some layout skills that TAs will not tell you during the course, but they greatly helped me to improve the performance of the multiplier
## Conclusion
In this project, we experience the procedure of Top to Down design and Down to Top Develop, we first design the multiplier in hignest level, then we gradually split each of the component so we can get the basic logic gate we need. The development procedure start form the bisic logic gate, we design half adder and full adder based on these logic gates, finally the multiplier will be constructed by adders. In each level a serises of test were done to make sure the design functions well. During the layout procedure, we change the way transistors were put, so the size and delay is reduced.
\@writefile{toc}{\contentsline{subsection}{\numberline{\mbox{VIII-A}}Delay of basic Gates}{5}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{15}{\ignorespaces Delay of Inverter with output capacitance 15f F\relax}}{5}{}\protected@file@percent }
@@ -86,6 +86,8 @@
\@writefile{lof}{\contentsline{figure}{\numberline{26}{\ignorespaces Delay of XOR Gate with output capacitance 960f F\relax}}{7}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{27}{\ignorespaces Low to high delay of 11100001\relax}}{7}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{28}{\ignorespaces Low to high delay of 11100001\relax}}{7}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{29}{\ignorespacesHigh to low delay of 11100001\relax}}{7}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{29}{\ignorespacesLow to high delay of 11100001 in schematic view\relax}}{7}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{30}{\ignorespaces High to low delay of 11100001\relax}}{7}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{31}{\ignorespaces High to low delay of 11100001\relax}}{7}{}\protected@file@percent }
\@writefile{lof}{\contentsline{figure}{\numberline{32}{\ignorespaces High to low delay of 11100001 in schematic view\relax}}{7}{}\protected@file@percent }
