Loading Design/simulation/test_files/1_input.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=0.3p save ca:current save :pwr Design/simulation/test_files/1_input_C1.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=15f save ca:current save :pwr Design/simulation/test_files/1_input_C2.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=120f save ca:current save :pwr Design/simulation/test_files/1_input_C3.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=960f save ca:current save :pwr Design/simulation/test_files/2_AND_C1.input 0 → 100644 +8 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 4.2n 0 4.4n 1.8 6.4n 1.8] v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 4.2n 1.8 4.4n 1.8 6.4n 1.8] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=15f save ca:current save :pwr Loading
Design/simulation/test_files/1_input.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=0.3p save ca:current save :pwr
Design/simulation/test_files/1_input_C1.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=15f save ca:current save :pwr
Design/simulation/test_files/1_input_C2.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=120f save ca:current save :pwr
Design/simulation/test_files/1_input_C3.input 0 → 100644 +7 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=960f save ca:current save :pwr
Design/simulation/test_files/2_AND_C1.input 0 → 100644 +8 −0 Original line number Diff line number Diff line simulator lang=spectre v0 (vdd! 0) vsource type=dc dc=1.8 v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 4.2n 0 4.4n 1.8 6.4n 1.8] v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 4.2n 1.8 4.4n 1.8 6.4n 1.8] v2 (gnd! 0) vsource type=dc dc=0 ca (Out 0) capacitor c=15f save ca:current save :pwr
