@@ -23,6 +23,8 @@ We put [design files](Design/multiplier), the [figure of the schematic and layou
### Reference
Some important reference files are put here, for example, I have simplify the design rules we need in this project in file [Design_Rules.pdf](reference/Design_Rules.pdf)
### Report
### Addition
@@ -37,6 +39,14 @@ We put [design files](Design/multiplier), the [figure of the schematic and layou
## Performance
### Area of the Layout
As we tested, the area of the layout is **((-11.2, -95)(53.2, 2)), 6246.8$\mu m^2$**
## Propagation delay
Here we will compare the post-layout delay measurements with the schematic level delay measurement 50f F cap is attached to the output. We apply two set of input to the multiplier so we can get the transfer data of all output. The first set is $ 0000 \times 1111 = 11100001$ and the second set is $ 0010 \times 1111 = 00011110$. As we measure, the maxmun down-to-up delay is **1ns** and uo-to-down delay is **0.75ns**, the plots are shown in Appendix.
## Layout Technic
Here we will introduce some layout skills that TAs will not tell you during the course, but they greatly helped me to improve the performance of the multiplier
