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a/Design/simulation/test_files/1_input.input b/involution/Design/multiplier/1_input.input similarity index 100% rename from Design/simulation/test_files/1_input.input rename to involution/Design/multiplier/1_input.input diff --git a/involution/Design/multiplier/1_input.input~ b/involution/Design/multiplier/1_input.input~ new file mode 100644 index 0000000000000000000000000000000000000000..d6e0482a903abc01022dc9bec47ac5802dfda072 --- /dev/null +++ b/involution/Design/multiplier/1_input.input~ @@ -0,0 +1,7 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[On 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/Design/simulation/test_files/2_input.input b/involution/Design/multiplier/2_input.input similarity index 100% rename from Design/simulation/test_files/2_input.input rename to involution/Design/multiplier/2_input.input diff --git a/Design/simulation/test_files/3_input.input~ b/involution/Design/multiplier/3_input.input similarity index 100% rename from Design/simulation/test_files/3_input.input~ rename to involution/Design/multiplier/3_input.input diff --git a/involution/Design/multiplier/3_input.input~ b/involution/Design/multiplier/3_input.input~ new file mode 100644 index 0000000000000000000000000000000000000000..d898debac25182fd6d936371b5434a6175e7b1be --- /dev/null +++ b/involution/Design/multiplier/3_input.input~ @@ -0,0 +1,9 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 16n 0 16.2n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 1.8 16n 1.8 16.2n 0 24n 0 24.2n 1.8] +v4 (Cin 0) vsource type=pwl wave=[0n 0 4n 0 4.2n 1.8 8n 1.8 8.2n 0 12n 0 12.2n 1.8 16n 1.8 16.2n 0 20n 0 20.2n 1.8 24n 1.8 24.2n 0 28n 0 28.2n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git 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Design/multiplier/4X4_multiplier/schematic/master.tag rename to involution/Design/multiplier/4X4_multiplier/schematic/master.tag diff --git a/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa b/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..fccf2cb68b360b1f2eb72241f65c7f62e4a64d0f Binary files /dev/null and b/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa differ diff --git a/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa.cdslck b/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..88e078fa8ba42aa49d400e41416941a2673ee832 --- /dev/null +++ b/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/4X4_multiplier/schematic/sch.oa.cdslck.dirlck +TimeEditLocked Thu May 27 01:50:57 2021 CST diff --git a/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..88e078fa8ba42aa49d400e41416941a2673ee832 --- /dev/null +++ b/involution/Design/multiplier/4X4_multiplier/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. 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multiplier_low" \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -format "DFII" \ + -run_name "and2" +log_file \ + -file_name "/home/SME_VLSI/VLSI_57/306cadence/LVS/qrc.and2.log" +output_db -type extracted_view \ + -enable_cellview_check false \ + -include_cap_model "false" \ + -include_parasitic_cap_model "true" \ + -include_parasitic_res_model "comment" \ + -include_res_model "false" \ + -res_component "presistor" \ + -res_property_name "r" \ + -view_name "av_extracted" +output_setup \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -temporary_directory_name "and2" +process_technology \ + -technology_library_file "/home/SME_VLSI/306cadence/assuraTech/oa_2014/assura_tech.lib" \ + -technology_name "assura_gpdk_tech" \ + -temperature \ + 25.0 + + diff --git a/involution/Design/multiplier/and2/av_extracted/data.dm b/involution/Design/multiplier/and2/av_extracted/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..2fd9bb4c61aedfd4a14c8993e0024c681d1bd544 Binary files /dev/null and b/involution/Design/multiplier/and2/av_extracted/data.dm differ diff --git a/involution/Design/multiplier/and2/av_extracted/layout.oa b/involution/Design/multiplier/and2/av_extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..c321834f2bc0759ce6f5275d9cf9d369c2886084 Binary files /dev/null and b/involution/Design/multiplier/and2/av_extracted/layout.oa differ diff --git a/Design/multiplier/and2_ass/layout/master.tag b/involution/Design/multiplier/and2/av_extracted/master.tag similarity index 100% rename from Design/multiplier/and2_ass/layout/master.tag rename to involution/Design/multiplier/and2/av_extracted/master.tag diff --git a/Design/multiplier/and2/data.dm b/involution/Design/multiplier/and2/data.dm similarity index 100% rename from Design/multiplier/and2/data.dm rename to involution/Design/multiplier/and2/data.dm diff --git a/involution/Design/multiplier/and2/extracted/layout.oa b/involution/Design/multiplier/and2/extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..9860b06156069020579476f3c5b21b395b136674 Binary files /dev/null and b/involution/Design/multiplier/and2/extracted/layout.oa differ diff --git a/Design/multiplier/full_adder_2/av_extracted/master.tag b/involution/Design/multiplier/and2/extracted/master.tag similarity index 100% rename from Design/multiplier/full_adder_2/av_extracted/master.tag rename to involution/Design/multiplier/and2/extracted/master.tag diff --git a/involution/Design/multiplier/and2/extracted/thumbnail_128x128.png b/involution/Design/multiplier/and2/extracted/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..7a292b6e46ff999e51e00789dc8daf72c764a834 Binary files /dev/null and b/involution/Design/multiplier/and2/extracted/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/and2/layout/layout.oa b/involution/Design/multiplier/and2/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..8b296222bb7ea389074dcd6a5a372982a29b817d Binary files /dev/null and b/involution/Design/multiplier/and2/layout/layout.oa differ diff --git a/Design/multiplier/full_adder_2/extracted/master.tag b/involution/Design/multiplier/and2/layout/master.tag similarity index 100% rename from Design/multiplier/full_adder_2/extracted/master.tag rename to involution/Design/multiplier/and2/layout/master.tag diff --git a/involution/Design/multiplier/and2/layout/thumbnail_128x128.png b/involution/Design/multiplier/and2/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..73408f3117525e1af6c00140b025010903c784f3 Binary files /dev/null and b/involution/Design/multiplier/and2/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/and2/schematic/data.dm b/involution/Design/multiplier/and2/schematic/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..caa71de1c1f485e4471d3fdbfdfcaf6049ffa753 Binary files /dev/null and b/involution/Design/multiplier/and2/schematic/data.dm differ diff --git a/Design/multiplier/full_adder_2/schematic/master.tag b/involution/Design/multiplier/and2/schematic/master.tag similarity index 100% rename from Design/multiplier/full_adder_2/schematic/master.tag rename to involution/Design/multiplier/and2/schematic/master.tag diff --git a/involution/Design/multiplier/and2/schematic/sch.oa b/involution/Design/multiplier/and2/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..ac8dad44c4c418e5489e894d6e46621d58823a61 Binary files /dev/null and b/involution/Design/multiplier/and2/schematic/sch.oa differ diff --git a/involution/Design/multiplier/and2/schematic/sch.oa.cdslck b/involution/Design/multiplier/and2/schematic/sch.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..9f15346c7392b8fe9d1e3ae1aba6c5091f263b90 --- /dev/null +++ b/involution/Design/multiplier/and2/schematic/sch.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/and2/schematic/sch.oa.cdslck +TimeEditLocked Wed May 26 16:55:37 2021 CST diff --git a/involution/Design/multiplier/and2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 b/involution/Design/multiplier/and2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 new file mode 100644 index 0000000000000000000000000000000000000000..9f15346c7392b8fe9d1e3ae1aba6c5091f263b90 --- /dev/null +++ b/involution/Design/multiplier/and2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/and2/schematic/sch.oa.cdslck +TimeEditLocked Wed May 26 16:55:37 2021 CST diff --git a/Design/multiplier/and2/schematic/thumbnail_128x128.png b/involution/Design/multiplier/and2/schematic/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/and2/schematic/thumbnail_128x128.png rename to involution/Design/multiplier/and2/schematic/thumbnail_128x128.png diff --git a/Design/multiplier/full_adder_2/symbol/master.tag b/involution/Design/multiplier/and2/symbol/master.tag similarity index 100% rename from Design/multiplier/full_adder_2/symbol/master.tag rename to involution/Design/multiplier/and2/symbol/master.tag diff --git a/Design/multiplier/and2/symbol/symbol.oa b/involution/Design/multiplier/and2/symbol/symbol.oa similarity index 100% rename from Design/multiplier/and2/symbol/symbol.oa rename to involution/Design/multiplier/and2/symbol/symbol.oa diff --git a/Design/multiplier/and2/symbol/thumbnail_128x128.png b/involution/Design/multiplier/and2/symbol/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/and2/symbol/thumbnail_128x128.png rename to involution/Design/multiplier/and2/symbol/thumbnail_128x128.png diff --git a/involution/Design/multiplier/and2_ass/layout/layout.oa b/involution/Design/multiplier/and2_ass/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..1c7de9f334372e768216950da27ee2d120c7a6c7 Binary files /dev/null and b/involution/Design/multiplier/and2_ass/layout/layout.oa differ diff --git a/involution/Design/multiplier/and2_ass/layout/layout.oa- b/involution/Design/multiplier/and2_ass/layout/layout.oa- new file mode 100644 index 0000000000000000000000000000000000000000..7fe9ee79b67732be1e61cae36b6238023573601e Binary files /dev/null and b/involution/Design/multiplier/and2_ass/layout/layout.oa- differ diff --git a/involution/Design/multiplier/and2_ass/layout/layout.oa.cdslck b/involution/Design/multiplier/and2_ass/layout/layout.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..3c9b6b3d118dcddc78b9d08c9e8b3a695a70fafb --- /dev/null +++ b/involution/Design/multiplier/and2_ass/layout/layout.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 114175 +ProcessCreationTime_UTC 1622046572 +ProcessCreationTime_Readable Thu May 27 00:29:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/and2_ass/layout/layout.oa.cdslck.dirlck +TimeEditLocked Thu May 27 00:42:55 2021 CST diff --git a/involution/Design/multiplier/and2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.114175 b/involution/Design/multiplier/and2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.114175 new file mode 100644 index 0000000000000000000000000000000000000000..3c9b6b3d118dcddc78b9d08c9e8b3a695a70fafb --- /dev/null +++ b/involution/Design/multiplier/and2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.114175 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 114175 +ProcessCreationTime_UTC 1622046572 +ProcessCreationTime_Readable Thu May 27 00:29:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/and2_ass/layout/layout.oa.cdslck.dirlck +TimeEditLocked Thu May 27 00:42:55 2021 CST diff --git a/Design/multiplier/full_adder_2/layout/master.tag b/involution/Design/multiplier/and2_ass/layout/master.tag similarity index 100% rename from Design/multiplier/full_adder_2/layout/master.tag rename to involution/Design/multiplier/and2_ass/layout/master.tag diff --git a/involution/Design/multiplier/and2_ass/layout/thumbnail_128x128.png b/involution/Design/multiplier/and2_ass/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..93bef9d713d14d5d1c3206d695ba9a817d463c45 Binary files /dev/null and b/involution/Design/multiplier/and2_ass/layout/thumbnail_128x128.png differ diff --git a/Design/multiplier/cdsinfo.tag b/involution/Design/multiplier/cdsinfo.tag similarity index 100% rename from Design/multiplier/cdsinfo.tag rename to involution/Design/multiplier/cdsinfo.tag diff --git a/Design/multiplier/data.dm b/involution/Design/multiplier/data.dm similarity index 100% rename from Design/multiplier/data.dm rename to involution/Design/multiplier/data.dm diff --git a/Design/multiplier/full_adder_2/av_extracted/CCLFile b/involution/Design/multiplier/full_adder_2/av_extracted/CCLFile similarity index 100% rename from Design/multiplier/full_adder_2/av_extracted/CCLFile rename to involution/Design/multiplier/full_adder_2/av_extracted/CCLFile diff --git a/Design/multiplier/full_adder_2/av_extracted/data.dm b/involution/Design/multiplier/full_adder_2/av_extracted/data.dm similarity index 100% rename from Design/multiplier/full_adder_2/av_extracted/data.dm rename to involution/Design/multiplier/full_adder_2/av_extracted/data.dm diff --git a/involution/Design/multiplier/full_adder_2/av_extracted/layout.oa b/involution/Design/multiplier/full_adder_2/av_extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..81dec147f66249913b68ccd538703f63700c4224 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2/av_extracted/layout.oa differ diff --git a/Design/multiplier/full_adder_2_ass/layout/master.tag b/involution/Design/multiplier/full_adder_2/av_extracted/master.tag similarity index 100% rename from Design/multiplier/full_adder_2_ass/layout/master.tag rename to involution/Design/multiplier/full_adder_2/av_extracted/master.tag diff --git a/involution/Design/multiplier/full_adder_2/av_extracted/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2/av_extracted/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..7accf02b8a0afed933ec86a75390b111e3cfbd9f Binary files /dev/null and b/involution/Design/multiplier/full_adder_2/av_extracted/thumbnail_128x128.png differ diff --git a/Design/multiplier/full_adder_2/data.dm b/involution/Design/multiplier/full_adder_2/data.dm similarity index 100% rename from Design/multiplier/full_adder_2/data.dm rename to involution/Design/multiplier/full_adder_2/data.dm diff --git a/Design/multiplier/full_adder_2/extracted/layout.oa b/involution/Design/multiplier/full_adder_2/extracted/layout.oa similarity index 100% rename from Design/multiplier/full_adder_2/extracted/layout.oa rename to involution/Design/multiplier/full_adder_2/extracted/layout.oa diff --git a/Design/multiplier/half_adder_2/av_extracted/master.tag b/involution/Design/multiplier/full_adder_2/extracted/master.tag similarity index 100% rename from Design/multiplier/half_adder_2/av_extracted/master.tag rename to involution/Design/multiplier/full_adder_2/extracted/master.tag diff --git a/Design/multiplier/full_adder_2/extracted/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2/extracted/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/full_adder_2/extracted/thumbnail_128x128.png rename to involution/Design/multiplier/full_adder_2/extracted/thumbnail_128x128.png diff --git a/involution/Design/multiplier/full_adder_2/layout/layout.oa b/involution/Design/multiplier/full_adder_2/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..f30a38d312cf1b145791e40e3f3d6d80f509e7ae Binary files /dev/null and b/involution/Design/multiplier/full_adder_2/layout/layout.oa differ diff --git a/Design/multiplier/half_adder_2/layout/master.tag b/involution/Design/multiplier/full_adder_2/layout/master.tag similarity index 100% rename from Design/multiplier/half_adder_2/layout/master.tag rename to involution/Design/multiplier/full_adder_2/layout/master.tag diff --git a/involution/Design/multiplier/full_adder_2/layout/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..3e7654dfbb5c02f3fb8fa606331acf3da87389e9 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/full_adder_2/schematic/data.dm b/involution/Design/multiplier/full_adder_2/schematic/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..87841c16a37c0734a03a6917244036b43a06bcb4 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2/schematic/data.dm differ diff --git a/Design/multiplier/half_adder_2/schematic/master.tag b/involution/Design/multiplier/full_adder_2/schematic/master.tag similarity index 100% rename from Design/multiplier/half_adder_2/schematic/master.tag rename to involution/Design/multiplier/full_adder_2/schematic/master.tag diff --git a/involution/Design/multiplier/full_adder_2/schematic/sch.oa b/involution/Design/multiplier/full_adder_2/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..1b68b7abcae41a3713d933e7de0f9e23890d5246 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2/schematic/sch.oa differ diff --git a/involution/Design/multiplier/full_adder_2/schematic/sch.oa.cdslck b/involution/Design/multiplier/full_adder_2/schematic/sch.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..ccb0907e2eb907ab45f9cb76199217ea8695928d --- /dev/null +++ b/involution/Design/multiplier/full_adder_2/schematic/sch.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/full_adder_2/schematic/sch.oa.cdslck +TimeEditLocked Wed May 26 14:56:12 2021 CST diff --git a/involution/Design/multiplier/full_adder_2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 b/involution/Design/multiplier/full_adder_2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 new file mode 100644 index 0000000000000000000000000000000000000000..ccb0907e2eb907ab45f9cb76199217ea8695928d --- /dev/null +++ b/involution/Design/multiplier/full_adder_2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/full_adder_2/schematic/sch.oa.cdslck +TimeEditLocked Wed May 26 14:56:12 2021 CST diff --git a/Design/multiplier/full_adder_2/schematic/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2/schematic/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/full_adder_2/schematic/thumbnail_128x128.png rename to involution/Design/multiplier/full_adder_2/schematic/thumbnail_128x128.png diff --git a/Design/multiplier/half_adder_2/symbol/master.tag b/involution/Design/multiplier/full_adder_2/symbol/master.tag similarity index 100% rename from Design/multiplier/half_adder_2/symbol/master.tag rename to involution/Design/multiplier/full_adder_2/symbol/master.tag diff --git a/Design/multiplier/full_adder_2/symbol/symbol.oa b/involution/Design/multiplier/full_adder_2/symbol/symbol.oa similarity index 100% rename from Design/multiplier/full_adder_2/symbol/symbol.oa rename to involution/Design/multiplier/full_adder_2/symbol/symbol.oa diff --git a/Design/multiplier/full_adder_2/symbol/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2/symbol/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/full_adder_2/symbol/thumbnail_128x128.png rename to involution/Design/multiplier/full_adder_2/symbol/thumbnail_128x128.png diff --git a/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..85cc351cadb4f19302e34a659f839244579ee198 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa differ diff --git a/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa- b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa- new file mode 100644 index 0000000000000000000000000000000000000000..85cc351cadb4f19302e34a659f839244579ee198 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa- differ diff --git a/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..76ed93cbbc634f8e526fcc152eaaeaf2cb1687bb --- /dev/null +++ b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/full_adder_2_ass/layout/layout.oa.cdslck.dirlck +TimeEditLocked Thu May 27 01:42:14 2021 CST diff --git a/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..76ed93cbbc634f8e526fcc152eaaeaf2cb1687bb --- /dev/null +++ b/involution/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/full_adder_2_ass/layout/layout.oa.cdslck.dirlck +TimeEditLocked Thu May 27 01:42:14 2021 CST diff --git a/Design/multiplier/half_adder_2_ass/layout/master.tag b/involution/Design/multiplier/full_adder_2_ass/layout/master.tag similarity index 100% rename from Design/multiplier/half_adder_2_ass/layout/master.tag rename to involution/Design/multiplier/full_adder_2_ass/layout/master.tag diff --git a/involution/Design/multiplier/full_adder_2_ass/layout/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2_ass/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..deb0708b0301e54111baf59b3b0cb1124b153e59 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2_ass/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/full_adder_2_narrow/layout/layout.oa b/involution/Design/multiplier/full_adder_2_narrow/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..84e90d98ddc82afcb256a8e451cb1dfc762717d5 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2_narrow/layout/layout.oa differ diff --git a/Design/multiplier/inv/av_extracted/master.tag b/involution/Design/multiplier/full_adder_2_narrow/layout/master.tag similarity index 100% rename from Design/multiplier/inv/av_extracted/master.tag rename to involution/Design/multiplier/full_adder_2_narrow/layout/master.tag diff --git a/involution/Design/multiplier/full_adder_2_narrow/layout/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2_narrow/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..e7d7a23f4e872e758fd42e4ad095acf15451aad8 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2_narrow/layout/thumbnail_128x128.png differ diff --git a/Design/multiplier/inv/schematic/master.tag b/involution/Design/multiplier/full_adder_2_narrow/schematic/master.tag similarity index 100% rename from Design/multiplier/inv/schematic/master.tag rename to involution/Design/multiplier/full_adder_2_narrow/schematic/master.tag diff --git a/involution/Design/multiplier/full_adder_2_narrow/schematic/sch.oa b/involution/Design/multiplier/full_adder_2_narrow/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..970b44bc0e27ca97cb23236cf9a45a19541523e5 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2_narrow/schematic/sch.oa differ diff --git a/involution/Design/multiplier/full_adder_2_narrow/schematic/thumbnail_128x128.png b/involution/Design/multiplier/full_adder_2_narrow/schematic/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..bd66eaf2580bb5b8510c0f1f38b420b50de0c989 Binary files /dev/null and b/involution/Design/multiplier/full_adder_2_narrow/schematic/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/half_adder.input b/involution/Design/multiplier/half_adder.input new file mode 100644 index 0000000000000000000000000000000000000000..cd548cfff8a6368d38f759118181f7054a486e23 --- /dev/null +++ b/involution/Design/multiplier/half_adder.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 1.8 16n 1.8 16.2n 0 24n 0 24.2n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 0 16n 0 16.2n 1.8 24n 1.8 24.2n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/involution/Design/multiplier/half_adder.input~ b/involution/Design/multiplier/half_adder.input~ new file mode 100644 index 0000000000000000000000000000000000000000..cd548cfff8a6368d38f759118181f7054a486e23 --- /dev/null +++ b/involution/Design/multiplier/half_adder.input~ @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 1.8 16n 1.8 16.2n 0 24n 0 24.2n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 0 16n 0 16.2n 1.8 24n 1.8 24.2n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/Design/multiplier/half_adder_2/av_extracted/CCLFile b/involution/Design/multiplier/half_adder_2/av_extracted/CCLFile similarity index 100% rename from Design/multiplier/half_adder_2/av_extracted/CCLFile rename to involution/Design/multiplier/half_adder_2/av_extracted/CCLFile diff --git a/Design/multiplier/half_adder_2/av_extracted/data.dm b/involution/Design/multiplier/half_adder_2/av_extracted/data.dm similarity index 100% rename from Design/multiplier/half_adder_2/av_extracted/data.dm rename to involution/Design/multiplier/half_adder_2/av_extracted/data.dm diff --git a/Design/multiplier/half_adder_2/av_extracted/layout.oa b/involution/Design/multiplier/half_adder_2/av_extracted/layout.oa similarity index 100% rename from Design/multiplier/half_adder_2/av_extracted/layout.oa rename to involution/Design/multiplier/half_adder_2/av_extracted/layout.oa diff --git a/Design/multiplier/inv/extracted/master.tag b/involution/Design/multiplier/half_adder_2/av_extracted/master.tag similarity index 100% rename from Design/multiplier/inv/extracted/master.tag rename to involution/Design/multiplier/half_adder_2/av_extracted/master.tag diff --git a/Design/multiplier/half_adder_2/data.dm b/involution/Design/multiplier/half_adder_2/data.dm similarity index 100% rename from Design/multiplier/half_adder_2/data.dm rename to involution/Design/multiplier/half_adder_2/data.dm diff --git a/involution/Design/multiplier/half_adder_2/layout/layout.oa b/involution/Design/multiplier/half_adder_2/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..0fd56d541c36693196b750792fbd791e37daf922 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2/layout/layout.oa differ diff --git a/Design/multiplier/inv/layout/master.tag b/involution/Design/multiplier/half_adder_2/layout/master.tag similarity index 100% rename from Design/multiplier/inv/layout/master.tag rename to involution/Design/multiplier/half_adder_2/layout/master.tag diff --git a/involution/Design/multiplier/half_adder_2/layout/thumbnail_128x128.png b/involution/Design/multiplier/half_adder_2/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..3927c1cc7d80803cc7310e620e806da49357d8cf Binary files /dev/null and b/involution/Design/multiplier/half_adder_2/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/half_adder_2/schematic/data.dm b/involution/Design/multiplier/half_adder_2/schematic/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..488d06e0152d8e2f6bf33b920afa50caef943874 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2/schematic/data.dm differ diff --git a/Design/multiplier/nand2/schematic/master.tag b/involution/Design/multiplier/half_adder_2/schematic/master.tag similarity index 100% rename from Design/multiplier/nand2/schematic/master.tag rename to involution/Design/multiplier/half_adder_2/schematic/master.tag diff --git a/involution/Design/multiplier/half_adder_2/schematic/sch.oa b/involution/Design/multiplier/half_adder_2/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..c96c7698ada089508f0d3d8006f7be1a5ba19563 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2/schematic/sch.oa differ diff --git a/involution/Design/multiplier/half_adder_2/schematic/sch.oa.cdslck b/involution/Design/multiplier/half_adder_2/schematic/sch.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..11294d3d80b569c5d51b0be29670abaa13bd09c0 --- /dev/null +++ b/involution/Design/multiplier/half_adder_2/schematic/sch.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/half_adder_2/schematic/sch.oa.cdslck +TimeEditLocked Wed May 26 16:55:11 2021 CST diff --git a/involution/Design/multiplier/half_adder_2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 b/involution/Design/multiplier/half_adder_2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 new file mode 100644 index 0000000000000000000000000000000000000000..11294d3d80b569c5d51b0be29670abaa13bd09c0 --- /dev/null +++ b/involution/Design/multiplier/half_adder_2/schematic/sch.oa.cdslck.RHEL30.serveric3.23779 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/half_adder_2/schematic/sch.oa.cdslck +TimeEditLocked Wed May 26 16:55:11 2021 CST diff --git a/Design/multiplier/half_adder_2/schematic/thumbnail_128x128.png b/involution/Design/multiplier/half_adder_2/schematic/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/half_adder_2/schematic/thumbnail_128x128.png rename to involution/Design/multiplier/half_adder_2/schematic/thumbnail_128x128.png diff --git a/Design/multiplier/inv/symbol/master.tag b/involution/Design/multiplier/half_adder_2/symbol/master.tag similarity index 100% rename from Design/multiplier/inv/symbol/master.tag rename to involution/Design/multiplier/half_adder_2/symbol/master.tag diff --git a/Design/multiplier/half_adder_2/symbol/symbol.oa b/involution/Design/multiplier/half_adder_2/symbol/symbol.oa similarity index 100% rename from Design/multiplier/half_adder_2/symbol/symbol.oa rename to involution/Design/multiplier/half_adder_2/symbol/symbol.oa diff --git a/Design/multiplier/half_adder_2/symbol/thumbnail_128x128.png b/involution/Design/multiplier/half_adder_2/symbol/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/half_adder_2/symbol/thumbnail_128x128.png rename to involution/Design/multiplier/half_adder_2/symbol/thumbnail_128x128.png diff --git a/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..7e6103ff0109733dfd71293b46bafdbad606c9d6 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa differ diff --git a/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa- b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa- new file mode 100644 index 0000000000000000000000000000000000000000..676911d761cc74e1a4ebc37e4cabe25425d76a76 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa- differ diff --git a/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..a462d6230a5449af02299a1ed35816b144d77f79 --- /dev/null +++ b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/half_adder_2_ass/layout/layout.oa.cdslck.dirlck +TimeEditLocked Thu May 27 01:31:25 2021 CST diff --git a/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..a462d6230a5449af02299a1ed35816b144d77f79 --- /dev/null +++ b/involution/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/half_adder_2_ass/layout/layout.oa.cdslck.dirlck +TimeEditLocked Thu May 27 01:31:25 2021 CST diff --git a/Design/multiplier/nand2/av_extracted/master.tag b/involution/Design/multiplier/half_adder_2_ass/layout/master.tag similarity index 100% rename from Design/multiplier/nand2/av_extracted/master.tag rename to involution/Design/multiplier/half_adder_2_ass/layout/master.tag diff --git a/involution/Design/multiplier/half_adder_2_ass/layout/thumbnail_128x128.png b/involution/Design/multiplier/half_adder_2_ass/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..1a1a48f26e4534ab7018d973fa2e7094da00f13d Binary files /dev/null and b/involution/Design/multiplier/half_adder_2_ass/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/half_adder_2_narrow/layout/layout.oa b/involution/Design/multiplier/half_adder_2_narrow/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..fe291701548bcd4a128ca5a1fb8d3a7d4ad9cbd3 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2_narrow/layout/layout.oa differ diff --git a/Design/multiplier/nand2/extracted/master.tag b/involution/Design/multiplier/half_adder_2_narrow/layout/master.tag similarity index 100% rename from Design/multiplier/nand2/extracted/master.tag rename to involution/Design/multiplier/half_adder_2_narrow/layout/master.tag diff --git a/involution/Design/multiplier/half_adder_2_narrow/layout/thumbnail_128x128.png b/involution/Design/multiplier/half_adder_2_narrow/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..7a17781fe04def371cb72ca5c3dc67700d1d3fb4 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2_narrow/layout/thumbnail_128x128.png differ diff --git a/Design/multiplier/xor2/schematic/master.tag b/involution/Design/multiplier/half_adder_2_narrow/schematic/master.tag similarity index 100% rename from Design/multiplier/xor2/schematic/master.tag rename to involution/Design/multiplier/half_adder_2_narrow/schematic/master.tag diff --git a/involution/Design/multiplier/half_adder_2_narrow/schematic/sch.oa b/involution/Design/multiplier/half_adder_2_narrow/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..27fd778868738d3cbdaa0b5155a44222c1cf32bd Binary files /dev/null and b/involution/Design/multiplier/half_adder_2_narrow/schematic/sch.oa differ diff --git a/involution/Design/multiplier/half_adder_2_narrow/schematic/thumbnail_128x128.png b/involution/Design/multiplier/half_adder_2_narrow/schematic/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..56216524f61631589afe8abe2ebefb4cd4aadd32 Binary files /dev/null and b/involution/Design/multiplier/half_adder_2_narrow/schematic/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/inv/av_extracted/CCLFile b/involution/Design/multiplier/inv/av_extracted/CCLFile new file mode 100644 index 0000000000000000000000000000000000000000..d4a7aa3c7293d9f1b1fa522f39f1dfb3c69c1981 --- /dev/null +++ b/involution/Design/multiplier/inv/av_extracted/CCLFile @@ -0,0 +1,43 @@ +# +# OPTION COMMAND FILE created by Cadence Quantus QRC Extraction Version 14.1.5-s182 from CCL +# +device_reduction \ + -m_factor infinite +extract \ + -selection "all" \ + -type "r_only" +extraction_setup \ + -array_vias_spacing auto \ + -max_fracture_length infinite \ + -max_fracture_length_unit "MICRONS" \ + -max_via_array_size \ + "auto" \ + -net_name_space "LAYOUT" +filter_res \ + -min_res 0.001 +input_db -type assura \ + -design_cell_name "inv layout multiplier_low" \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -format "DFII" \ + -run_name "inv" +log_file \ + -file_name "/home/SME_VLSI/VLSI_57/306cadence/LVS/qrc.inv.log" +output_db -type extracted_view \ + -enable_cellview_check false \ + -include_cap_model "false" \ + -include_parasitic_cap_model "true" \ + -include_parasitic_res_model "comment" \ + -include_res_model "false" \ + -res_component "presistor" \ + -res_property_name "r" \ + -view_name "av_extracted" +output_setup \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -temporary_directory_name "inv" +process_technology \ + -technology_library_file "/home/SME_VLSI/306cadence/assuraTech/oa_2014/assura_tech.lib" \ + -technology_name "assura_gpdk_tech" \ + -temperature \ + 25.0 + + diff --git a/involution/Design/multiplier/inv/av_extracted/data.dm b/involution/Design/multiplier/inv/av_extracted/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..8ea70c9e369469d75cb64c10849709e1fa3f39f1 Binary files /dev/null and b/involution/Design/multiplier/inv/av_extracted/data.dm differ diff --git a/involution/Design/multiplier/inv/av_extracted/layout.oa b/involution/Design/multiplier/inv/av_extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..16f8497d28cc00beddc39a59e435a91c81b4a497 Binary files /dev/null and b/involution/Design/multiplier/inv/av_extracted/layout.oa differ diff --git a/Design/multiplier/nand2/layout/master.tag b/involution/Design/multiplier/inv/av_extracted/master.tag similarity index 100% rename from Design/multiplier/nand2/layout/master.tag rename to involution/Design/multiplier/inv/av_extracted/master.tag diff --git a/Design/multiplier/inv/data.dm b/involution/Design/multiplier/inv/data.dm similarity index 100% rename from Design/multiplier/inv/data.dm rename to involution/Design/multiplier/inv/data.dm diff --git a/involution/Design/multiplier/inv/extracted/layout.oa b/involution/Design/multiplier/inv/extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..ba1584b71f13cf00ff2a0e47e1f68460c7ecf73a Binary files /dev/null and b/involution/Design/multiplier/inv/extracted/layout.oa differ diff --git a/Design/multiplier/xor2/av_extracted/master.tag b/involution/Design/multiplier/inv/extracted/master.tag similarity index 100% rename from Design/multiplier/xor2/av_extracted/master.tag rename to involution/Design/multiplier/inv/extracted/master.tag diff --git a/involution/Design/multiplier/inv/extracted/thumbnail_128x128.png b/involution/Design/multiplier/inv/extracted/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..4d1ba427e14f4a26ce14364dbf4c4153867a019f Binary files /dev/null and b/involution/Design/multiplier/inv/extracted/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/inv/layout/layout.oa b/involution/Design/multiplier/inv/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..8310c892626c225838d62274e8883e494d205b93 Binary files /dev/null and b/involution/Design/multiplier/inv/layout/layout.oa differ diff --git a/Design/multiplier/xor2/extracted/master.tag b/involution/Design/multiplier/inv/layout/master.tag similarity index 100% rename from Design/multiplier/xor2/extracted/master.tag rename to involution/Design/multiplier/inv/layout/master.tag diff --git a/involution/Design/multiplier/inv/layout/thumbnail_128x128.png b/involution/Design/multiplier/inv/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..badc6d1431a4dfe78e9f1f49a46e72e5b74c2b6b Binary files /dev/null and b/involution/Design/multiplier/inv/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/inv/schematic/data.dm b/involution/Design/multiplier/inv/schematic/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..107b3ef631d2d8e2eecef2659b0ea355013b1080 Binary files /dev/null and b/involution/Design/multiplier/inv/schematic/data.dm differ diff --git a/involution/Design/multiplier/inv/schematic/master.tag b/involution/Design/multiplier/inv/schematic/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..26be1bef2ea7f883db0d50576c31cb244b3b0d9f --- /dev/null +++ b/involution/Design/multiplier/inv/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/involution/Design/multiplier/inv/schematic/sch.oa b/involution/Design/multiplier/inv/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..a3f64f77f28149f9e30f8395626e83069e00c7aa Binary files /dev/null and b/involution/Design/multiplier/inv/schematic/sch.oa differ diff --git a/involution/Design/multiplier/inv/schematic/sch.oa.cdslck b/involution/Design/multiplier/inv/schematic/sch.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..dceec93d631a799411180edb93f8ca4d26db17a7 --- /dev/null +++ b/involution/Design/multiplier/inv/schematic/sch.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/inv/schematic/sch.oa.cdslck +TimeEditLocked Thu May 27 02:34:11 2021 CST diff --git a/involution/Design/multiplier/inv/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/inv/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..dceec93d631a799411180edb93f8ca4d26db17a7 --- /dev/null +++ b/involution/Design/multiplier/inv/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/inv/schematic/sch.oa.cdslck +TimeEditLocked Thu May 27 02:34:11 2021 CST diff --git a/Design/multiplier/inv/schematic/thumbnail_128x128.png b/involution/Design/multiplier/inv/schematic/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/inv/schematic/thumbnail_128x128.png rename to involution/Design/multiplier/inv/schematic/thumbnail_128x128.png diff --git a/Design/multiplier/nand2/symbol/master.tag b/involution/Design/multiplier/inv/symbol/master.tag similarity index 100% rename from Design/multiplier/nand2/symbol/master.tag rename to involution/Design/multiplier/inv/symbol/master.tag diff --git a/Design/multiplier/inv/symbol/symbol.oa b/involution/Design/multiplier/inv/symbol/symbol.oa similarity index 100% rename from Design/multiplier/inv/symbol/symbol.oa rename to involution/Design/multiplier/inv/symbol/symbol.oa diff --git a/involution/Design/multiplier/inv/symbol/symbol.oa.cdslck b/involution/Design/multiplier/inv/symbol/symbol.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..e32141f019d8e02fac57518629398060bf85feb7 --- /dev/null +++ b/involution/Design/multiplier/inv/symbol/symbol.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/inv/symbol/symbol.oa.cdslck +TimeEditLocked Wed May 26 16:15:01 2021 CST diff --git a/involution/Design/multiplier/inv/symbol/symbol.oa.cdslck.RHEL30.serveric3.23779 b/involution/Design/multiplier/inv/symbol/symbol.oa.cdslck.RHEL30.serveric3.23779 new file mode 100644 index 0000000000000000000000000000000000000000..e32141f019d8e02fac57518629398060bf85feb7 --- /dev/null +++ b/involution/Design/multiplier/inv/symbol/symbol.oa.cdslck.RHEL30.serveric3.23779 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 23779 +ProcessCreationTime_UTC 1622009026 +ProcessCreationTime_Readable Wed May 26 14:03:46 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/inv/symbol/symbol.oa.cdslck +TimeEditLocked Wed May 26 16:15:01 2021 CST diff --git a/Design/multiplier/inv/symbol/thumbnail_128x128.png b/involution/Design/multiplier/inv/symbol/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/inv/symbol/thumbnail_128x128.png rename to involution/Design/multiplier/inv/symbol/thumbnail_128x128.png diff --git a/involution/Design/multiplier/nand2/av_extracted/CCLFile b/involution/Design/multiplier/nand2/av_extracted/CCLFile new file mode 100644 index 0000000000000000000000000000000000000000..98354adcc14beedc572073d492b1ae9798004cc4 --- /dev/null +++ b/involution/Design/multiplier/nand2/av_extracted/CCLFile @@ -0,0 +1,43 @@ +# +# OPTION COMMAND FILE created by Cadence Quantus QRC Extraction Version 14.1.5-s182 from CCL +# +device_reduction \ + -m_factor infinite +extract \ + -selection "all" \ + -type "r_only" +extraction_setup \ + -array_vias_spacing auto \ + -max_fracture_length infinite \ + -max_fracture_length_unit "MICRONS" \ + -max_via_array_size \ + "auto" \ + -net_name_space "LAYOUT" +filter_res \ + -min_res 0.001 +input_db -type assura \ + -design_cell_name "nand2 layout multiplier_low" \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -format "DFII" \ + -run_name "nand2" +log_file \ + -file_name "/home/SME_VLSI/VLSI_57/306cadence/LVS/qrc.nand2.log" +output_db -type extracted_view \ + -enable_cellview_check false \ + -include_cap_model "false" \ + -include_parasitic_cap_model "true" \ + -include_parasitic_res_model "comment" \ + -include_res_model "false" \ + -res_component "presistor" \ + -res_property_name "r" \ + -view_name "av_extracted" +output_setup \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -temporary_directory_name "nand2" +process_technology \ + -technology_library_file "/home/SME_VLSI/306cadence/assuraTech/oa_2014/assura_tech.lib" \ + -technology_name "assura_gpdk_tech" \ + -temperature \ + 25.0 + + diff --git a/involution/Design/multiplier/nand2/av_extracted/data.dm b/involution/Design/multiplier/nand2/av_extracted/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..5fd0c27756c7432ac5b61406282816c62a206c35 Binary files /dev/null and b/involution/Design/multiplier/nand2/av_extracted/data.dm differ diff --git a/involution/Design/multiplier/nand2/av_extracted/layout.oa b/involution/Design/multiplier/nand2/av_extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..23568c0e5247d598ec7da4df30d0fbcee45ab503 Binary files /dev/null and b/involution/Design/multiplier/nand2/av_extracted/layout.oa differ diff --git a/Design/multiplier/xor2/layout/master.tag b/involution/Design/multiplier/nand2/av_extracted/master.tag similarity index 100% rename from Design/multiplier/xor2/layout/master.tag rename to involution/Design/multiplier/nand2/av_extracted/master.tag diff --git a/Design/multiplier/nand2/data.dm b/involution/Design/multiplier/nand2/data.dm similarity index 100% rename from Design/multiplier/nand2/data.dm rename to involution/Design/multiplier/nand2/data.dm diff --git a/involution/Design/multiplier/nand2/extracted/layout.oa b/involution/Design/multiplier/nand2/extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..6a984c7cf9d15f6b36f590c7981dbb2193866a36 Binary files /dev/null and b/involution/Design/multiplier/nand2/extracted/layout.oa differ diff --git a/involution/Design/multiplier/nand2/extracted/master.tag b/involution/Design/multiplier/nand2/extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/nand2/extracted/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/involution/Design/multiplier/nand2/extracted/thumbnail_128x128.png b/involution/Design/multiplier/nand2/extracted/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..e34bece932b0ce91cf4310244f053a81407feaa7 Binary files /dev/null and b/involution/Design/multiplier/nand2/extracted/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/nand2/layout/layout.oa b/involution/Design/multiplier/nand2/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..9a38f5baa46473a484ba307ecfe8b4463ef76024 Binary files /dev/null and b/involution/Design/multiplier/nand2/layout/layout.oa differ diff --git a/involution/Design/multiplier/nand2/layout/layout.oa.cdslck b/involution/Design/multiplier/nand2/layout/layout.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..aebe0cd142e2ac25fcee8ee0d0ae1bf2e4dcd8ca --- /dev/null +++ b/involution/Design/multiplier/nand2/layout/layout.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/nand2/layout/layout.oa.cdslck +TimeEditLocked Thu May 27 02:28:31 2021 CST diff --git a/involution/Design/multiplier/nand2/layout/layout.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/nand2/layout/layout.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..aebe0cd142e2ac25fcee8ee0d0ae1bf2e4dcd8ca --- /dev/null +++ b/involution/Design/multiplier/nand2/layout/layout.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/nand2/layout/layout.oa.cdslck +TimeEditLocked Thu May 27 02:28:31 2021 CST diff --git a/involution/Design/multiplier/nand2/layout/master.tag b/involution/Design/multiplier/nand2/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/nand2/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/involution/Design/multiplier/nand2/layout/thumbnail_128x128.png b/involution/Design/multiplier/nand2/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..48bd7fd662a914b3528ff775a8a2333ce98ad816 Binary files /dev/null and b/involution/Design/multiplier/nand2/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/nand2/schematic/data.dm b/involution/Design/multiplier/nand2/schematic/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..cb82f394a7302051689cb1b54b351d7221fb0169 Binary files /dev/null and b/involution/Design/multiplier/nand2/schematic/data.dm differ diff --git a/involution/Design/multiplier/nand2/schematic/master.tag b/involution/Design/multiplier/nand2/schematic/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..26be1bef2ea7f883db0d50576c31cb244b3b0d9f --- /dev/null +++ b/involution/Design/multiplier/nand2/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/involution/Design/multiplier/nand2/schematic/sch.oa b/involution/Design/multiplier/nand2/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..242486457dcd19f0ff5a357079c36bbd8f9454c0 Binary files /dev/null and b/involution/Design/multiplier/nand2/schematic/sch.oa differ diff --git a/involution/Design/multiplier/nand2/schematic/sch.oa.cdslck b/involution/Design/multiplier/nand2/schematic/sch.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..fa04c0b62f9f1d6ba645d5d8367c58e10dcf58b6 --- /dev/null +++ b/involution/Design/multiplier/nand2/schematic/sch.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/nand2/schematic/sch.oa.cdslck.dirlck +TimeEditLocked Thu May 27 03:01:08 2021 CST diff --git a/involution/Design/multiplier/nand2/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/nand2/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..fa04c0b62f9f1d6ba645d5d8367c58e10dcf58b6 --- /dev/null +++ b/involution/Design/multiplier/nand2/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/nand2/schematic/sch.oa.cdslck.dirlck +TimeEditLocked Thu May 27 03:01:08 2021 CST diff --git a/Design/multiplier/nand2/schematic/thumbnail_128x128.png b/involution/Design/multiplier/nand2/schematic/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/nand2/schematic/thumbnail_128x128.png rename to involution/Design/multiplier/nand2/schematic/thumbnail_128x128.png diff --git a/Design/multiplier/xor2/symbol/master.tag b/involution/Design/multiplier/nand2/symbol/master.tag similarity index 100% rename from Design/multiplier/xor2/symbol/master.tag rename to involution/Design/multiplier/nand2/symbol/master.tag diff --git a/Design/multiplier/nand2/symbol/symbol.oa b/involution/Design/multiplier/nand2/symbol/symbol.oa similarity index 100% rename from Design/multiplier/nand2/symbol/symbol.oa rename to involution/Design/multiplier/nand2/symbol/symbol.oa diff --git a/Design/multiplier/nand2/symbol/thumbnail_128x128.png b/involution/Design/multiplier/nand2/symbol/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/nand2/symbol/thumbnail_128x128.png rename to involution/Design/multiplier/nand2/symbol/thumbnail_128x128.png diff --git a/involution/Design/multiplier/size_match/layout/layout.oa b/involution/Design/multiplier/size_match/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..43c3b79d5bbd7c9e338b6b886577db65c37ead53 Binary files /dev/null and b/involution/Design/multiplier/size_match/layout/layout.oa differ diff --git a/involution/Design/multiplier/size_match/layout/master.tag b/involution/Design/multiplier/size_match/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/size_match/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/involution/Design/multiplier/size_match/layout/thumbnail_128x128.png b/involution/Design/multiplier/size_match/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..9d4c486e686cf833232da08838e03b42b6a20d1e Binary files /dev/null and b/involution/Design/multiplier/size_match/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/size_match_2/layout/layout.oa b/involution/Design/multiplier/size_match_2/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..b9e0159fc6d46e2b94ed69cf484ca542286a442e Binary files /dev/null and b/involution/Design/multiplier/size_match_2/layout/layout.oa differ diff --git a/involution/Design/multiplier/size_match_2/layout/master.tag b/involution/Design/multiplier/size_match_2/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/size_match_2/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/involution/Design/multiplier/size_match_2/layout/thumbnail_128x128.png b/involution/Design/multiplier/size_match_2/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..36f114d599006862c7fc4b57f36001a5d6036e4f Binary files /dev/null and b/involution/Design/multiplier/size_match_2/layout/thumbnail_128x128.png differ diff --git a/Design/multiplier/tech.db b/involution/Design/multiplier/tech.db similarity index 100% rename from Design/multiplier/tech.db rename to involution/Design/multiplier/tech.db diff --git a/involution/Design/multiplier/test.input b/involution/Design/multiplier/test.input new file mode 100644 index 0000000000000000000000000000000000000000..a51ee1f4220b99b68634adfbfbb4161d2291cd0e --- /dev/null +++ b/involution/Design/multiplier/test.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] +v3 (B 0) vsource type=pwl wave=[0n 0 4n 0 4.2n 1.8 16.2n 1.8 16.4n 0] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/involution/Design/multiplier/xor2.input b/involution/Design/multiplier/xor2.input new file mode 100644 index 0000000000000000000000000000000000000000..a51ee1f4220b99b68634adfbfbb4161d2291cd0e --- /dev/null +++ b/involution/Design/multiplier/xor2.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] +v3 (B 0) vsource type=pwl wave=[0n 0 4n 0 4.2n 1.8 16.2n 1.8 16.4n 0] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/involution/Design/multiplier/xor2.input~ b/involution/Design/multiplier/xor2.input~ new file mode 100644 index 0000000000000000000000000000000000000000..a51ee1f4220b99b68634adfbfbb4161d2291cd0e --- /dev/null +++ b/involution/Design/multiplier/xor2.input~ @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] +v3 (B 0) vsource type=pwl wave=[0n 0 4n 0 4.2n 1.8 16.2n 1.8 16.4n 0] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/involution/Design/multiplier/xor2/av_extracted/CCLFile b/involution/Design/multiplier/xor2/av_extracted/CCLFile new file mode 100644 index 0000000000000000000000000000000000000000..9a0cdbe212f7c700dc6e1d4907a1ee523d9889d3 --- /dev/null +++ b/involution/Design/multiplier/xor2/av_extracted/CCLFile @@ -0,0 +1,43 @@ +# +# OPTION COMMAND FILE created by Cadence Quantus QRC Extraction Version 14.1.5-s182 from CCL +# +device_reduction \ + -m_factor infinite +extract \ + -selection "all" \ + -type "r_only" +extraction_setup \ + -array_vias_spacing auto \ + -max_fracture_length infinite \ + -max_fracture_length_unit "MICRONS" \ + -max_via_array_size \ + "auto" \ + -net_name_space "LAYOUT" +filter_res \ + -min_res 0.001 +input_db -type assura \ + -design_cell_name "xor2 layout multiplier_low" \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -format "DFII" \ + -run_name "xor2" +log_file \ + -file_name "/home/SME_VLSI/VLSI_57/306cadence/LVS/qrc.xor2.log" +output_db -type extracted_view \ + -enable_cellview_check false \ + -include_cap_model "false" \ + -include_parasitic_cap_model "true" \ + -include_parasitic_res_model "comment" \ + -include_res_model "false" \ + -res_component "presistor" \ + -res_property_name "r" \ + -view_name "av_extracted" +output_setup \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -temporary_directory_name "xor2" +process_technology \ + -technology_library_file "/home/SME_VLSI/306cadence/assuraTech/oa_2014/assura_tech.lib" \ + -technology_name "assura_gpdk_tech" \ + -temperature \ + 25.0 + + diff --git a/involution/Design/multiplier/xor2/av_extracted/data.dm b/involution/Design/multiplier/xor2/av_extracted/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..498d997533e482e4dfc5c981af84806eea93c087 Binary files /dev/null and b/involution/Design/multiplier/xor2/av_extracted/data.dm differ diff --git a/involution/Design/multiplier/xor2/av_extracted/layout.oa b/involution/Design/multiplier/xor2/av_extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..558474008b3d50141695e253007b6b3418e39df1 Binary files /dev/null and b/involution/Design/multiplier/xor2/av_extracted/layout.oa differ diff --git a/involution/Design/multiplier/xor2/av_extracted/master.tag b/involution/Design/multiplier/xor2/av_extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/xor2/av_extracted/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/xor2/data.dm b/involution/Design/multiplier/xor2/data.dm similarity index 100% rename from Design/multiplier/xor2/data.dm rename to involution/Design/multiplier/xor2/data.dm diff --git a/Design/multiplier/xor2/extracted/layout.oa b/involution/Design/multiplier/xor2/extracted/layout.oa similarity index 100% rename from Design/multiplier/xor2/extracted/layout.oa rename to involution/Design/multiplier/xor2/extracted/layout.oa diff --git a/involution/Design/multiplier/xor2/extracted/master.tag b/involution/Design/multiplier/xor2/extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/xor2/extracted/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/xor2/extracted/thumbnail_128x128.png b/involution/Design/multiplier/xor2/extracted/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/xor2/extracted/thumbnail_128x128.png rename to involution/Design/multiplier/xor2/extracted/thumbnail_128x128.png diff --git a/involution/Design/multiplier/xor2/layout/layout.oa b/involution/Design/multiplier/xor2/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..d9cdaf4c83f54efd6600ff02d47f2ebfc19e8f8b Binary files /dev/null and b/involution/Design/multiplier/xor2/layout/layout.oa differ diff --git a/involution/Design/multiplier/xor2/layout/layout.oa.cdslck b/involution/Design/multiplier/xor2/layout/layout.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..85648b1254359bca979d02216a17f9b2747806d5 --- /dev/null +++ b/involution/Design/multiplier/xor2/layout/layout.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/xor2/layout/layout.oa.cdslck +TimeEditLocked Thu May 27 02:28:36 2021 CST diff --git a/involution/Design/multiplier/xor2/layout/layout.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/xor2/layout/layout.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..85648b1254359bca979d02216a17f9b2747806d5 --- /dev/null +++ b/involution/Design/multiplier/xor2/layout/layout.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/xor2/layout/layout.oa.cdslck +TimeEditLocked Thu May 27 02:28:36 2021 CST diff --git a/involution/Design/multiplier/xor2/layout/master.tag b/involution/Design/multiplier/xor2/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/xor2/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/involution/Design/multiplier/xor2/layout/thumbnail_128x128.png b/involution/Design/multiplier/xor2/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..619d9fab4d37151fde2dbcfafdc13df266d563b7 Binary files /dev/null and b/involution/Design/multiplier/xor2/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/xor2/schematic/data.dm b/involution/Design/multiplier/xor2/schematic/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..cdf369dcd9a8f0179ef44bf5c4d8ad1209ff9868 Binary files /dev/null and b/involution/Design/multiplier/xor2/schematic/data.dm differ diff --git a/involution/Design/multiplier/xor2/schematic/master.tag b/involution/Design/multiplier/xor2/schematic/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..26be1bef2ea7f883db0d50576c31cb244b3b0d9f --- /dev/null +++ b/involution/Design/multiplier/xor2/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/involution/Design/multiplier/xor2/schematic/sch.oa b/involution/Design/multiplier/xor2/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..7af5c0361d9804640474f6c4d2ff19a2dfd86067 Binary files /dev/null and b/involution/Design/multiplier/xor2/schematic/sch.oa differ diff --git a/involution/Design/multiplier/xor2/schematic/sch.oa.cdslck b/involution/Design/multiplier/xor2/schematic/sch.oa.cdslck new file mode 100644 index 0000000000000000000000000000000000000000..1584cec08519238f3409146865a6060eecf360e2 --- /dev/null +++ b/involution/Design/multiplier/xor2/schematic/sch.oa.cdslck @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/xor2/schematic/sch.oa.cdslck.dirlck +TimeEditLocked Thu May 27 03:09:40 2021 CST diff --git a/involution/Design/multiplier/xor2/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 b/involution/Design/multiplier/xor2/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 new file mode 100644 index 0000000000000000000000000000000000000000..1584cec08519238f3409146865a6060eecf360e2 --- /dev/null +++ b/involution/Design/multiplier/xor2/schematic/sch.oa.cdslck.RHEL30.serveric3.6429 @@ -0,0 +1,16 @@ +# +# Edit Lock-Stake file. CAUTION: Please do not change. +# +# Information about current Edit Lock Owner. +# +LockStakeVersion 1.1 +LoginName VLSI_57 +HostName serveric3 +ProcessIdentifier 6429 +ProcessCreationTime_UTC 1622048912 +ProcessCreationTime_Readable Thu May 27 01:08:32 2021 CST +AppIdentifier OA File System Design Manager +OSType unix +ReasonForPlacingEditLock OpenAccess edit lock +FilePathUsedToEditLock /home/SME_VLSI/VLSI_57/306cadence/multiplier_low/xor2/schematic/sch.oa.cdslck.dirlck +TimeEditLocked Thu May 27 03:09:40 2021 CST diff --git a/Design/multiplier/xor2/schematic/thumbnail_128x128.png b/involution/Design/multiplier/xor2/schematic/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/xor2/schematic/thumbnail_128x128.png rename to involution/Design/multiplier/xor2/schematic/thumbnail_128x128.png diff --git a/involution/Design/multiplier/xor2/symbol/master.tag b/involution/Design/multiplier/xor2/symbol/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..e1024da05678ababdb17d8f8ef60d53e9761add0 --- /dev/null +++ b/involution/Design/multiplier/xor2/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/Design/multiplier/xor2/symbol/symbol.oa b/involution/Design/multiplier/xor2/symbol/symbol.oa similarity index 100% rename from Design/multiplier/xor2/symbol/symbol.oa rename to involution/Design/multiplier/xor2/symbol/symbol.oa diff --git a/Design/multiplier/xor2/symbol/thumbnail_128x128.png b/involution/Design/multiplier/xor2/symbol/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/xor2/symbol/thumbnail_128x128.png rename to involution/Design/multiplier/xor2/symbol/thumbnail_128x128.png diff --git a/Design/multiplier/nand2/av_extracted/CCLFile b/involution/Design/multiplier/xor2_backend/av_extracted/CCLFile similarity index 100% rename from Design/multiplier/nand2/av_extracted/CCLFile rename to involution/Design/multiplier/xor2_backend/av_extracted/CCLFile diff --git a/Design/multiplier/nand2/av_extracted/data.dm b/involution/Design/multiplier/xor2_backend/av_extracted/data.dm similarity index 100% rename from Design/multiplier/nand2/av_extracted/data.dm rename to involution/Design/multiplier/xor2_backend/av_extracted/data.dm diff --git a/involution/Design/multiplier/xor2_backend/av_extracted/layout.oa b/involution/Design/multiplier/xor2_backend/av_extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..7db3099de541da1db4273dcbea84db45ea7e9689 Binary files /dev/null and b/involution/Design/multiplier/xor2_backend/av_extracted/layout.oa differ diff --git a/involution/Design/multiplier/xor2_backend/av_extracted/master.tag b/involution/Design/multiplier/xor2_backend/av_extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/xor2_backend/av_extracted/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/involution/Design/multiplier/xor2_backend/data.dm b/involution/Design/multiplier/xor2_backend/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..a4b12e433c67d0c4be984c6f86228c86aca5fbe1 Binary files /dev/null and b/involution/Design/multiplier/xor2_backend/data.dm differ diff --git a/involution/Design/multiplier/xor2_backend/extracted/layout.oa b/involution/Design/multiplier/xor2_backend/extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..5550f556a2eaad44dfd97d8b3761bc02e651d08c Binary files /dev/null and b/involution/Design/multiplier/xor2_backend/extracted/layout.oa differ diff --git a/involution/Design/multiplier/xor2_backend/extracted/master.tag b/involution/Design/multiplier/xor2_backend/extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/xor2_backend/extracted/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/nand2/extracted/thumbnail_128x128.png b/involution/Design/multiplier/xor2_backend/extracted/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/nand2/extracted/thumbnail_128x128.png rename to involution/Design/multiplier/xor2_backend/extracted/thumbnail_128x128.png diff --git a/involution/Design/multiplier/xor2_backend/layout/layout.oa b/involution/Design/multiplier/xor2_backend/layout/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..56f5bb2b3b74a71cfe52b85324202fe913cfc4b9 Binary files /dev/null and b/involution/Design/multiplier/xor2_backend/layout/layout.oa differ diff --git a/involution/Design/multiplier/xor2_backend/layout/master.tag b/involution/Design/multiplier/xor2_backend/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/involution/Design/multiplier/xor2_backend/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/involution/Design/multiplier/xor2_backend/layout/thumbnail_128x128.png b/involution/Design/multiplier/xor2_backend/layout/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..78bb310fa2497b7e0fe266b09d1345007cc526cd Binary files /dev/null and b/involution/Design/multiplier/xor2_backend/layout/thumbnail_128x128.png differ diff --git a/involution/Design/multiplier/xor2_backend/schematic/data.dm b/involution/Design/multiplier/xor2_backend/schematic/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..90241198eda6dbec57707356852d14fd87b18b6a Binary files /dev/null and b/involution/Design/multiplier/xor2_backend/schematic/data.dm differ diff --git a/involution/Design/multiplier/xor2_backend/schematic/master.tag b/involution/Design/multiplier/xor2_backend/schematic/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..26be1bef2ea7f883db0d50576c31cb244b3b0d9f --- /dev/null +++ b/involution/Design/multiplier/xor2_backend/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/involution/Design/multiplier/xor2_backend/schematic/sch.oa b/involution/Design/multiplier/xor2_backend/schematic/sch.oa new file mode 100644 index 0000000000000000000000000000000000000000..83c058ae3e84ee4d87b3f012b90e5ae6c5bc4fbb Binary files /dev/null and b/involution/Design/multiplier/xor2_backend/schematic/sch.oa differ diff --git a/involution/Design/multiplier/xor2_backend/schematic/thumbnail_128x128.png b/involution/Design/multiplier/xor2_backend/schematic/thumbnail_128x128.png new file mode 100644 index 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rf896n rf897n rf898n rf899n rf900n rf901n rf902n rf903n rf904n rf905n rf906n rf907n rf908n rf909n rf910n rf911n rf912n rf913n rf914n rf915n rf916n rf917n rf918n rf919n rf920n rf921n rf922n rf923n rf924n rf925n rf926n rf927n rf928n rf929n rf930n rf931n rf932n rf933n rf934n rf935n rf936n rf937n rf938n rf939n rf940n rf941n rf942n rf943n rf944n rf945n rf946n rf947n rf948n rf949n rf950n rf951n rf952n rf953n rf954n rf955n rf956n rf957n rf958n rf959n rf960n rf961n rf962n rf963n rf964n rf965n rf966n rf967n rf968n rf969n rf970n rf971n rf972n rf973n rf974n rf975n rf976n rf977n rf978n rf979n rf980n rf981n rf982n rf983n rf984n rf985n rf986n rf987n rf988n rf989n rf990n rf991n rf992n rf993n rf994n rf995n rf996n rf997n rf998n rf999n rf1000n rf1001n rf1002n rf1003n rf1004n rf1005n rf1006n rf1007n rf1008n rf1009n rf1010n rf1011n rf1012n rf1013n rf1014n rf1015n rf1016n rf1017n rf1018n rf1019n rf1020n rf1021n rf1022n rf1023n rf1024n rf1025n rf1026n rf1027n rf1028n rf1029n rf1030n rf1031n rf1032n rf1033n rf1034n rf1035n rf1036n rf1037n rf1038n rf1039n rf1040n rf1041n rf1042n rf1043n rf1044n rf1045n rf1046n rf1047n rf1048n rf1049n rf1050n rf1051n rf1052n rf1053n rf1054n rf1055n rf1056n rf1057n rf1058n rf1059n rf1060n rf1061n rf1062n rf1063n rf1064n rf1065n rf1066n rf1067n rf1068n rf1069n rf1070n rf1071n rf1072n rf1073n rf1074n rf1075n rf1076n rf1077n rf1078n rf1079n rf1080n rf1081n rf1082n rf1083n rf1084n rf1085n rf1086n rf1087n rf1088n rf1089n rf1090n rf1091n rf1092n rf1093n rf1094n rf1095n rf1096n rf1097n rf1098n rf1099n rf1100n rf1101n rf1102n rf1103n rf1104n rf1105n rf1106n rf1107n rf1108n rf1109n rf1110n rf1111n rf1112n rf1113n rf1114n rf1115n rf1116n rf1117n rf1118n rf1119n rf1120n rf1121n rf1122n rf1123n rf1124n rf1125n rf1126n rf1127n rf1128n rf1129n rf1130n rf1131n rf1132n rf1133n rf1134n rf1135n rf1136n rf1137n rf1138n rf1139n rf1140n rf1141n rf1142n rf1143n rf1144n rf1145n rf1146n rf1147n rf1148n rf1149n rf1150n rf1151n rf1152n rf1153n rf1154n rf1155n rf1156n rf1157n rf1158n rf1159n rf1160n rf1161n rf1162n rf1163n rf1164n rf1165n rf1166n rf1167n rf1168n rf1169n rf1170n rf1171n rf1172n rf1173n rf1174n rf1175n rf1176n rf1177n rf1178n rf1179n rf1180n rf1181n rf1182n rf1183n rf1184n rf1185n rf1186n rf1187n rf1188n rf1189n rf1190n rf1191n rf1192n rf1193n rf1194n rf1195n rf1196n rf1197n rf1198n rf1199n rf1200n rf1201n rg1n rg2n rg3n rg4n rg5n rg6n rg7n rg8n rg9n rg10n rg11n rg12n rg13n rg14n rg15n rg16n rg17n rg18n rg20n rg21n rg22n rg23n rg24n rg25n rg26n rg27n rg28n rg29n rg30n rg31n rg32n rg33n rg34n rg35n rg36n rg37n rg38n rg39n rg40n rg41n rg42n rg43n rg44n rg45n rg46n rg47n rg48n rg49n rg50n rg51n rg52n rg53n rg54n rg55n rg56n rg57n rg58n rg59n rg60n rg61n rg62n rg63n rg64n rg65n rg66n rg67n rg68n rg69n rg70n rg71n rg72n rg73n rg74n rg75n rg76n rg77n rg78n rg79n rg80n rg81n rg82n rg83n rg84n rg85n rg86n rg87n rg88n rg89n rg90n rg91n rg92n rg93n rg94n rg95n rg96n rg97n rg98n rg99n rg100n rg101n rg102n rg103n rg104n rg105n rg106n rg107n rg108n rg109n rg110n rg111n rg112n rg113n rg114n rg115n rg116n rg117n rg118n rg119n rg120n rg121n rg122n rg123n rg124n rg125n rg126n rg127n rg128n rg129n rg130n rg131n rg132n rg133n rg134n rg135n rg136n rg137n rg138n rg139n rg140n rg141n rg142n rg143n rg144n rg145n rg146n rg147n rg148n rg149n rg150n rg151n rg152n rg153n rg154n rg155n rg156n rg157n rg158n rg159n rg160n rg161n rg162n rg163n rg165n rg166n rg167n rg168n rg169n rg170n rg171n rg172n rg173n rg174n rg175n rg176n rg177n rg178n rg179n rg180n rg181n rg182n rg183n rg184n rg185n rg186n rg187n rg188n rg189n rg190n rg191n rg192n rg193n rg194n rg195n rg196n rg197n rg198n rg199n rg200n rg201n rg202n rg203n rg204n rg205n rg206n rg207n rg208n rg209n rg210n rg211n rg212n rg213n rg214n rg215n rg216n rg217n rg218n rg219n rg220n rg221n rg222n rg223n rg224n rg225n rg226n rg227n rg228n rg229n rg230n rg231n rg232n rg233n rg234n rg235n rg236n rg237n rg238n rg239n rg240n rg241n rg242n rg243n rg244n rg245n rg246n rg247n rg248n rg249n rg250n rg251n rg252n rg253n rg254n rg255n rg256n rg257n rg258n rg259n rg260n rg261n rg262n rg263n rg264n rg265n rg266n rg267n rg268n rg269n rg270n rg271n rg272n rg273n rg274n rg275n rg276n rg277n rg278n rg279n rg280n rg281n rg282n rg283n rg284n rg285n rg286n rg287n rg288n rg289n rg290n rg291n rg292n rg293n rg294n rg295n rg296n rg297n rg298n rg299n rg300n rg301n rg302n rg303n rg304n rg305n rg306n rg307n rg308n rg309n rg310n rg311n rg312n rg313n rg314n rg315n rg316n rg317n rg318n rg319n rg320n rg321n rg322n rg323n rg324n rg325n rg326n rg327n rg328n rg329n rg330n rg331n rg332n rg333n rg334n rg335n rg336n rg337n rg338n rg339n rg340n rg341n rg342n rg343n rg344n rg345n rg346n rg347n rg348n rg349n rg350n rg351n rg352n rg353n rg354n rg355n rg356n rg357n rg358n rg359n rg360n rg361n rg362n rg363n rg364n rg365n rg366n rg367n rg368n rg369n rg370n rg371n rg372n rg373n rg374n rg375n rg376n rg377n rg378n rg379n rg380n rg381n rg382n rg383n rg384n rg385n rg386n rg387n rg388n rg389n rg390n rg391n rg392n rg393n rg394n rg395n rg396n rg397n rg398n rg399n rg400n rg401n rg402n rg403n rg404n rg405n rg406n rg407n rg408n rg409n rg410n rg411n rg412n rg413n rg414n rg415n rg416n rg417n rg418n rg419n rg420n rg421n rg422n rg423n rg424n rg425n rg426n rg427n rg428n rg429n rg430n rg431n rg432n rg433n rg434n rg435n rg436n rg437n rg438n rg439n rg440n rg441n rg442n rg443n rg444n rg445n rg446n rg447n rg448n rg449n rg450n rg451n rg452n rg453n rg454n rg455n rg456n rg457n rg458n rg459n rg460n rg461n rg462n rg463n rg464n rg465n rg466n rg467n rg468n rg469n rg470n rg471n rg472n rg473n rg474n rg475n rg476n rg477n rg478n rg479n rg480n rg481n rg482n rg483n rg484n rg485n rg486n rg487n rg488n rg489n rg490n rg491n rg492n rg493n rg494n rg495n rg496n rg497n rg498n rg499n rg500n rg501n rg502n rg503n rg504n rg505n rg506n rg507n rg508n rg509n rg510n rg511n rg512n rg514n rg515n rg516n rg517n rg518n rg519n rg520n rg521n rg522n rg523n rg524n rg525n rg526n rg527n rg528n rg529n rg530n rg531n rg532n rg533n rg534n rg535n rg536n rg537n rg538n rg539n rg540n rg541n rg542n rg543n rg544n rg545n rg546n rg547n rg548n rg549n rg550n rg551n rg552n rg553n rg554n rg555n rg556n rg557n rg558n rg559n rg560n rg561n rg562n rg563n rg564n rg565n rg566n rg567n rg568n rg569n rg570n rg571n rg572n rg573n rg574n rg575n rg576n rg577n rg578n rg579n rg580n rg581n rg582n rg583n rg584n rg585n rg586n rg587n rg588n rg589n rg590n rg591n rg592n rg593n rg594n rg595n rg596n rg597n rg598n rg599n rg600n rg601n rg602n rg603n rg604n rg605n rg606n rg607n rg608n rg609n rg610n rg611n rg612n rg613n rg614n rg615n rg616n rg617n rg618n rg619n rg620n rg621n rg622n rg623n rg624n rg625n rg626n rg627n rg628n rg629n rg630n rg631n rg632n rg633n rg634n rg635n rg636n rg637n rg638n rg640n rg641n rg642n rg643n rg644n rg645n rg647n rg648n rg649n rg650n rg651n rg652n rg653n rg654n rg655n rg656n" "analogLib_presistor_spectre" +"I25|MP0n I22|MP0n I14|MP2n I17|MP2n I25|MP1n I22|MP1n I8|I1|MP4n I7|I1|MP4n I14|MP1n I17|MP0n I25|MP2n I22|MP2n I8|I1|MP1n I7|I1|MP1n I14|MP0n I17|MP1n I8|I1|MP0n I7|I1|MP0n I8|I3|MP1n I8|I1|MP2n I7|I3|MP1n I7|I1|MP2n I6|I3|MP2n I6|I1|MP5n I8|I3|MP0n I8|I1|MP3n I7|I3|MP0n I7|I1|MP3n I6|I3|MP1n I6|I1|MP2n I24|MP0n I6|I1|MP0n I23|MP0n I6|I1|MP1n I16|MP2n I6|I3|MP0n I6|I1|MP3n I8|I1|MP5n I8|I3|MP2n I7|I1|MP5n I7|I3|MP2n I6|I1|MP4n I16|MP1n I2|I4|MP0n I24|MP1n I16|MP0n I23|MP1n I13|MP2n I11|I4|MP1n I24|MP2n I23|MP2n I2|I4|MP1n I11|I4|MP0n I1|I0|MP0n I1|I4|MP4n I1|I0|MP1n I1|I4|MP0n I1|I4|MP5n I1|I4|MP1n I13|MP1n I13|MP0n I1|I4|MP3n I1|I4|MP2n I2|I1|MP1n I2|I1|MP0n I2|I0|MP1n I2|I0|MP0n I2|I4|MP4n I1|I3|MP5n I1|I3|MP2n I1|I3|MP3n I1|I2|MP0n I1|I2|MP1n I1|I3|MP1n I1|I3|MP0n I1|I1|MP1n I1|I1|MP0n I1|I3|MP4n I3|I3|MP5n I2|I3|MP5n I2|I2|MP0n I2|I2|MP1n I3|I3|MP2n I2|I3|MP2n I2|I3|MP3n I2|I3|MP1n I2|I3|MP0n I2|I3|MP4n I2|I4|MP5n I2|I4|MP2n I2|I4|MP3n I11|I3|MP0n I11|I1|MP1n I11|I1|MP0n I11|I3|MP4n I11|I0|MP1n I11|I4|MP5n I11|I0|MP0n I11|I4|MP2n I11|I4|MP4n I11|I4|MP3n I10|I3|MP2n I10|I3|MP5n I11|I3|MP5n I11|I3|MP2n I11|I3|MP3n I11|I2|MP0n I11|I2|MP1n I11|I3|MP1n I0|I3|MP4n I0|I1|MP1n I0|I1|MP0n I0|I3|MP0n I0|I3|MP1n I0|I2|MP1n I0|I2|MP0n I0|I3|MP3n I0|I3|MP2n I0|I3|MP5n I3|I0|MP0n I3|I0|MP1n I3|I1|MP1n I3|I1|MP0n I3|I2|MP1n I3|I2|MP0n I0|I4|MP3n I21|MP2n I0|I4|MP4n I0|I4|MP2n I0|I0|MP0n I3|I4|MP4n I0|I4|MP5n I0|I0|MP1n I18|MP1n I0|I4|MP0n I21|MP0n I0|I4|MP1n I21|MP1n I18|MP2n I10|I3|MP0n I3|I3|MP0n I10|I3|MP1n I10|I2|MP1n I3|I3|MP1n I10|I2|MP0n I10|I3|MP3n I3|I3|MP3n I10|I4|MP5n I3|I4|MP5n I10|I0|MP1n I10|I3|MP4n I3|I3|MP4n I10|I1|MP1n I10|I1|MP0n I10|I4|MP3n I3|I4|MP3n I10|I4|MP4n I10|I4|MP2n I3|I4|MP2n I10|I0|MP0n I26|MP0n I26|MP1n I10|I4|MP0n I3|I4|MP0n I10|I4|MP1n I3|I4|MP1n I26|MP2n I4|I2|MP1n I4|I2|MP0n I5|I1|MP4n I12|MP2n I4|I3|MP5n I18|MP0n I5|I3|MP0n I5|I1|MP3n I4|I1|MP1n I5|I1|MP1n I4|I1|MP0n I12|MP1n I5|I1|MP0n I12|MP0n I4|I4|MP4n I5|I1|MP5n I5|I3|MP2n I4|I0|MP0n I5|I3|MP1n I5|I1|MP2n I4|I0|MP1n I20|MP1n I15|MP0n I19|MP1n I20|MP0n I15|MP1n I19|MP0n I20|MP2n I15|MP2n I19|MP2n I4|I3|MP4n I4|I3|MP0n I4|I3|MP1n I4|I3|MP3n I4|I3|MP2n I9|I0|MP1n I9|I3|MP4n I9|I1|MP1n I9|I1|MP0n I9|I3|MP0n I9|I3|MP1n I9|I2|MP1n I9|I2|MP0n I9|I3|MP3n I9|I3|MP2n I9|I3|MP5n I4|I4|MP3n I9|I4|MP3n I9|I4|MP4n I4|I4|MP2n I9|I4|MP2n I9|I0|MP0n I4|I4|MP5n I9|I4|MP5n I27|MP1n I27|MP0n I4|I4|MP0n I9|I4|MP0n I4|I4|MP1n I9|I4|MP1n I27|MP2n" "gpdk_pmos_spectre" +"I25|MN0n I22|MN0n I14|MN2n I17|MN2n I25|MN1n I22|MN1n I8|I1|MN4n I7|I1|MN4n I14|MN1n I17|MN0n I25|MN2n I22|MN2n I8|I1|MN2n I7|I1|MN2n I14|MN0n I17|MN1n I8|I1|MN3n I7|I1|MN3n I8|I3|MN1n I8|I1|MN1n I7|I3|MN1n I7|I1|MN1n I6|I3|MN2n I6|I1|MN5n I8|I3|MN0n I8|I1|MN0n I7|I3|MN0n I7|I1|MN0n I6|I3|MN1n I6|I1|MN1n I24|MN0n I6|I1|MN3n I23|MN0n I6|I1|MN2n I16|MN2n I6|I3|MN0n I6|I1|MN0n I8|I1|MN5n I8|I3|MN2n I7|I1|MN5n I7|I3|MN2n I6|I1|MN4n I16|MN1n I2|I4|MN3n I24|MN1n I16|MN0n I23|MN1n I13|MN2n I11|I4|MN2n I24|MN2n I23|MN2n I2|I4|MN2n I11|I4|MN3n I1|I4|MN1n I2|I0|MN1n I2|I0|MN0n I13|MN1n I13|MN0n I1|I4|MN3n I2|I4|MN4n I1|I4|MN2n I11|I4|MN5n I11|I0|MN0n I2|I4|MN5n I11|I4|MN1n I11|I4|MN4n I2|I4|MN1n I11|I4|MN0n I2|I4|MN0n I1|I0|MN0n I1|I4|MN4n I2|I1|MN1n I1|I0|MN1n I2|I1|MN0n I1|I4|MN0n I1|I4|MN5n I2|I3|MN2n I11|I3|MN3n I11|I1|MN1n I2|I3|MN3n I11|I1|MN0n I11|I3|MN4n I2|I3|MN4n I11|I0|MN1n I1|I2|MN1n I1|I3|MN2n I2|I3|MN5n I1|I3|MN3n I1|I1|MN1n I2|I2|MN0n I1|I1|MN0n I1|I3|MN4n I2|I2|MN1n I11|I3|MN5n I11|I3|MN1n I2|I3|MN1n I11|I3|MN0n I2|I3|MN0n I11|I2|MN0n I11|I2|MN1n I11|I3|MN2n I10|I3|MN1n I10|I3|MN5n I3|I3|MN1n I3|I3|MN5n I1|I3|MN5n I1|I3|MN1n I1|I3|MN0n I1|I2|MN0n I0|I2|MN1n I3|I1|MN1n I0|I2|MN0n I0|I3|MN0n I3|I2|MN1n I0|I3|MN1n I0|I3|MN5n I3|I2|MN0n I3|I0|MN0n I0|I3|MN4n I0|I1|MN0n I3|I0|MN1n I0|I1|MN1n I0|I3|MN3n I3|I1|MN0n I0|I3|MN2n I0|I4|MN0n I21|MN2n I0|I4|MN4n I0|I4|MN1n I0|I0|MN0n I3|I4|MN4n I0|I4|MN5n I0|I0|MN1n I18|MN1n I0|I4|MN3n I21|MN0n I0|I4|MN2n I21|MN1n I18|MN2n I10|I3|MN3n I3|I3|MN3n I10|I3|MN2n I10|I2|MN1n I3|I3|MN2n I10|I2|MN0n I10|I3|MN0n I3|I3|MN0n I10|I4|MN5n I3|I4|MN5n I10|I0|MN1n I10|I3|MN4n I3|I3|MN4n I10|I1|MN0n I10|I1|MN1n I10|I4|MN0n I3|I4|MN0n I10|I4|MN4n I10|I4|MN1n I3|I4|MN1n I10|I0|MN0n I26|MN0n I26|MN1n I10|I4|MN3n I3|I4|MN3n I10|I4|MN2n I3|I4|MN2n I26|MN2n I4|I2|MN1n I4|I2|MN0n I5|I1|MN4n I12|MN2n I4|I3|MN5n I18|MN0n I5|I3|MN0n I5|I1|MN0n I4|I1|MN0n I5|I1|MN2n I4|I1|MN1n I12|MN1n I5|I1|MN3n I12|MN0n I4|I4|MN4n I5|I1|MN5n I5|I3|MN2n I4|I0|MN0n I5|I3|MN1n I5|I1|MN1n I4|I0|MN1n I20|MN1n I15|MN0n I19|MN1n I20|MN0n I15|MN1n I19|MN0n I20|MN2n I15|MN2n I19|MN2n I4|I3|MN2n I9|I3|MN2n I9|I2|MN1n I9|I2|MN0n I4|I3|MN0n I9|I3|MN0n I4|I3|MN1n I9|I3|MN1n I9|I3|MN5n I9|I0|MN1n I4|I3|MN4n I9|I3|MN4n I9|I1|MN0n I9|I1|MN1n I4|I3|MN3n I9|I3|MN3n I4|I4|MN0n I9|I4|MN0n I9|I4|MN4n I4|I4|MN1n I9|I4|MN1n I9|I0|MN0n I4|I4|MN5n I9|I4|MN5n I27|MN1n I27|MN0n I4|I4|MN3n I9|I4|MN3n I4|I4|MN2n I9|I4|MN2n I27|MN2n" "gpdk_nmos_spectre" diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/multiplier_low_4X4_multiplier_av_extracted.net b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/multiplier_low_4X4_multiplier_av_extracted.net new file mode 100644 index 0000000000000000000000000000000000000000..96276a4321c582b2cfae47f18e3aaae5b566753e --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/multiplier_low_4X4_multiplier_av_extracted.net @@ -0,0 +1,4 @@ +HEADER +"PSFversion" "1.00" +"vdd!v" "vdd!v" +"gnd!v" "0v" diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/amap/multiplier_4X4_multiplier_extracted.net b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/multiplier_low_4X4_multiplier_av_extracted.port similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/amap/multiplier_4X4_multiplier_extracted.net rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/multiplier_low_4X4_multiplier_av_extracted.port diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.inst new file mode 100644 index 0000000000000000000000000000000000000000..d4c756ad79df78de02f5a62b2abb985ed00c140a --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.inst @@ -0,0 +1,3 @@ +HEADER +"PSFversion" "1.00" +"__NEXT_FILE__" "multiplier_low_4X4_multiplier_av_extracted" diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.net new file mode 100644 index 0000000000000000000000000000000000000000..d4c756ad79df78de02f5a62b2abb985ed00c140a --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.net @@ -0,0 +1,3 @@ +HEADER +"PSFversion" "1.00" +"__NEXT_FILE__" "multiplier_low_4X4_multiplier_av_extracted" diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.port new file mode 100644 index 0000000000000000000000000000000000000000..d4c756ad79df78de02f5a62b2abb985ed00c140a --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/amap/top_level_map.port @@ -0,0 +1,3 @@ +HEADER +"PSFversion" "1.00" +"__NEXT_FILE__" "multiplier_low_4X4_multiplier_av_extracted" diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..2dac1034cb27485368f62b29d58a110eb892c019 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low 4X4_multiplier av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..318b5c78e4bf222cd40491eae12999624ad49092 Binary files /dev/null and b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/map b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/map new file mode 100644 index 0000000000000000000000000000000000000000..7d9ddec01629f18eaf8854ecac84e03cf5e227a5 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/map @@ -0,0 +1,19 @@ +( ( nil + version "2.1" + mapType "incremental" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + hierDelim "." + ) +( net + ) +( inst + ) +( model +( "4X4_multiplier" "multiplier_low_4X4_multiplier_av_extracted" ) + ) +( term + ) +( param + ) + ) diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/ihnl/cds0/map.ext b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/ihnl/cds0/map.ext rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..dfb739e4b193429a708acaf79d58228a6c06775f --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,2919 @@ + +// Library name: multiplier_low +// Cell name: 4X4_multiplier +// View name: av_extracted +rd1 (\8\:net19 \5\:net19) resistor r=8.0091 c=0 +rd2 (\12\:net16 \3\:net16) resistor r=5.8364 c=0 +rd3 (\24\:X3 \25\:X3) resistor r=3.1579 c=0 +rd4 (\25\:X3 \26\:X3) resistor r=0.5024 c=0 +rd5 (\26\:X3 \17\:X3) resistor r=5.0228 c=0 +rd6 (\17\:X3 \16\:X3) resistor r=4.8777 c=0 +rd7 (\25\:X3 \18\:X3) resistor r=0.04452 c=0 +rd8 (\26\:X3 X3) resistor r=1.8728 c=0 +rd9 (\20\:net17 net17) resistor r=7.2124 c=0 +rd10 (\20\:net54 \8\:net54) resistor r=8.6175 c=0 +rd11 (\12\:net15 net15) resistor r=7.3099 c=0 +rd12 (\14\:net21 net21) resistor r=5.4346 c=0 +rd13 (\8\:net0100 \11\:net0100) resistor r=4.2422 c=0 +rd14 (\8\:net29 \11\:net29) resistor r=4.6625 c=0 +rd15 (X2 \25\:X2) resistor r=2.0091 c=0 +rd16 (\25\:X2 \6\:X2) resistor r=4.3508 c=0 +rd17 (\25\:X2 \26\:X2) resistor r=4.9199 c=0 +rd18 (\26\:X2 \14\:X2) resistor r=9.0609 c=0 +rd19 (\25\:X2 \21\:X2) resistor r=4.2095 c=0 +rd20 (\26\:X2 \15\:X2) resistor r=3.9144 c=0 +rd21 (\11\:net45 \10\:net45) resistor r=3.8783 c=0 +rd22 (\11\:net5 \3\:net5) resistor r=4.1 c=0 +rd23 (\11\:net44 \8\:net44) resistor r=2.3746 c=0 +rd24 (\11\:net32 \8\:net32) resistor r=2.3184 c=0 +rd25 (\24\:X1 \3\:X1) resistor r=3.2855 c=0 +rd26 (\3\:X1 \25\:X1) resistor r=0.05722 c=0 +rd27 (\25\:X1 X1) resistor r=2.0116 c=0 +rd28 (\25\:X1 \26\:X1) resistor r=4.9159 c=0 +rd29 (\26\:X1 \9\:X1) resistor r=5.0544 c=0 +rd30 (\26\:X1 \18\:X1) resistor r=0.03024 c=0 +rd31 (X0 \25\:X0) resistor r=4.3738 c=0 +rd32 (\25\:X0 \11\:X0) resistor r=1.0865 c=0 +rd33 (\25\:X0 \24\:X0) resistor r=0.8508 c=0 +rd34 (\24\:X0 \22\:X0) resistor r=1.5696 c=0 +rd35 (\22\:X0 \23\:X0) resistor r=4.8116 c=0 +re1 (\16\:X3 \1\:X3) resistor r=4.4678 c=0 +re2 (\17\:X3 \3\:X3) resistor r=4.4712 c=0 +re3 (\5\:X3 \18\:X3) resistor r=4 c=0 +re4 (\4\:net19 \5\:net19) resistor r=0.005495 c=0 +re5 (net19 \4\:net19) resistor r=2 c=0 +re6 (\18\:net090 \2\:net090) resistor r=3.1152 c=0 +re7 (\18\:net13 \2\:net13) resistor r=3.1152 c=0 +re8 (\19\:net090 \4\:net090) resistor r=4.9649 c=0 +re9 (\4\:net13 \19\:net13) resistor r=4.9666 c=0 +re10 (\5\:net093 \2\:net093) resistor r=3.1619 c=0 +re11 (\6\:net19 \8\:net19) resistor r=2 c=0 +re12 (\3\:net16 net16) resistor r=2 c=0 +re13 (Z7 \1\:Z7) resistor r=6.021 c=0 +re14 (\8\:net54 \9\:net54) resistor r=0.004082 c=0 +re15 (\3\:net54 \9\:net54) resistor r=2 c=0 +re16 (\12\:net16 \13\:net16) resistor r=4.0411 c=0 +re17 (\6\:net55 \4\:net55) resistor r=5.3786 c=0 +re18 (\19\:X3 \24\:X3) resistor r=4 c=0 +re19 (\13\:I4\|net3 \14\:I4\|net3) resistor r=2.6847 c=0 +re20 (\14\:I4\|net3 \6\:I4\|net3) resistor r=0.9844 c=0 +re21 (\8\:I4\|net3 \14\:I4\|net3) resistor r=2 c=0 +re22 (\13\:I9\|net3 \14\:I9\|net3) resistor r=2.6847 c=0 +re23 (\14\:I9\|net3 \6\:I9\|net3) resistor r=0.9844 c=0 +re24 (\8\:I9\|net3 \14\:I9\|net3) resistor r=2 c=0 +re25 (net21 \2\:net21) resistor r=4 c=0 +re26 (net15 \2\:net15) resistor r=0.001087 c=0 +re27 (net17 \2\:net17) resistor r=0.004082 c=0 +re28 (Z6 \1\:Z6) resistor r=3.0317 c=0 +re29 (\15\:net55 \20\:net55) resistor r=4.7641 c=0 +re30 (\5\:X2 \6\:X2) resistor r=2 c=0 +re31 (\11\:X2 \14\:X2) resistor r=2 c=0 +re32 (\15\:X2 \12\:X2) resistor r=2 c=0 +re33 (\10\:net38 \2\:net38) resistor r=3.1152 c=0 +re34 (\4\:net38 \11\:net38) resistor r=5.0824 c=0 +re35 (\9\:net8 \5\:net8) resistor r=5.1152 c=0 +re36 (\11\:net8 \2\:net8) resistor r=5.0534 c=0 +re37 (\13\:net39 \2\:net39) resistor r=5.7166 c=0 +re38 (\10\:net087 \5\:net087) resistor r=3.1152 c=0 +re39 (\11\:net087 \2\:net087) resistor r=5.0993 c=0 +re40 (\21\:net55 net55) resistor r=8.1859 c=0 +re41 (\20\:net17 \19\:net17) resistor r=3.0466 c=0 +re42 (\20\:net54 \19\:net54) resistor r=3.0379 c=0 +re43 (\11\:net15 \12\:net15) resistor r=4 c=0 +re44 (\14\:net21 \12\:net21) resistor r=4.0011 c=0 +re45 (\14\:I0\|net3 \15\:I0\|net3) resistor r=0.6847 c=0 +re46 (\15\:I0\|net3 \6\:I0\|net3) resistor r=0.9844 c=0 +re47 (\8\:I0\|net3 \15\:I0\|net3) resistor r=2 c=0 +re48 (\13\:I10\|net3 \14\:I10\|net3) resistor r=2.6847 c=0 +re49 (\14\:I10\|net3 \6\:I10\|net3) resistor r=0.9844 c=0 +re50 (\8\:I10\|net3 \14\:I10\|net3) resistor r=2 c=0 +re51 (\14\:I3\|net3 \15\:I3\|net3) resistor r=0.6847 c=0 +re52 (\15\:I3\|net3 \6\:I3\|net3) resistor r=0.9844 c=0 +re53 (\8\:I3\|net3 \15\:I3\|net3) resistor r=2 c=0 +re54 (Z5 \2\:Z5) resistor r=3.1416 c=0 +re55 (\8\:net0100 \2\:net0100) resistor r=5.4502 c=0 +re56 (\8\:net29 \2\:net29) resistor r=5.86 c=0 +re57 (Z4 \1\:Z4) resistor r=3.0829 c=0 +re58 (\11\:net31 \2\:net31) resistor r=5.438 c=0 +re59 (\3\:net5 \2\:net5) resistor r=2.422 c=0 +re60 (\10\:net45 \2\:net45) resistor r=2.4508 c=0 +re61 (\11\:net1 \2\:net1) resistor r=6.1255 c=0 +re62 (\11\:net26 \2\:net26) resistor r=6.1929 c=0 +re63 (\10\:net0100 \11\:net0100) resistor r=2 c=0 +re64 (\13\:I1\|net3 \14\:I1\|net3) resistor r=2.9844 c=0 +re65 (\14\:I1\|net3 \7\:I1\|net3) resistor r=0.6847 c=0 +re66 (\12\:I1\|net3 \14\:I1\|net3) resistor r=2 c=0 +re67 (\10\:net29 \11\:net29) resistor r=2 c=0 +re68 (\19\:X2 \21\:X2) resistor r=4.0089 c=0 +re69 (\3\:net34 \13\:net34) resistor r=3.1152 c=0 +re70 (\13\:I11\|net3 \14\:I11\|net3) resistor r=2.9844 c=0 +re71 (\14\:I11\|net3 \7\:I11\|net3) resistor r=0.6847 c=0 +re72 (\12\:I11\|net3 \14\:I11\|net3) resistor r=2 c=0 +re73 (\13\:I2\|net3 \14\:I2\|net3) resistor r=2.9844 c=0 +re74 (\14\:I2\|net3 \7\:I2\|net3) resistor r=0.6847 c=0 +re75 (\9\:I2\|net3 \14\:I2\|net3) resistor r=2 c=0 +re76 (\3\:net078 \13\:net078) resistor r=3.1152 c=0 +re77 (\3\:net28 \13\:net28) resistor r=3.1152 c=0 +re78 (\18\:net34 \2\:net34) resistor r=6.3777 c=0 +re79 (\15\:net078 \2\:net078) resistor r=5.3259 c=0 +re80 (\14\:net28 \2\:net28) resistor r=5.1758 c=0 +re81 (\1\:X1 \3\:X1) resistor r=4.0933 c=0 +re82 (\8\:net44 \3\:net44) resistor r=8.0252 c=0 +re83 (\8\:X1 \9\:X1) resistor r=2.3735 c=0 +re84 (\14\:X1 \18\:X1) resistor r=2.5129 c=0 +re85 (\6\:net0115 \5\:net0115) resistor r=4.7641 c=0 +re86 (\8\:net32 \3\:net32) resistor r=9.1881 c=0 +re87 (\2\:net095 \12\:net095) resistor r=7.462 c=0 +re88 (\9\:net0115 \10\:net0115) resistor r=5.3786 c=0 +re89 (\12\:net5 \11\:net5) resistor r=4.4477 c=0 +re90 (\12\:net45 \11\:net45) resistor r=4.4706 c=0 +re91 (\11\:net44 \10\:net44) resistor r=2.7182 c=0 +re92 (\10\:net32 \11\:net32) resistor r=2.553 c=0 +re93 (\2\:net35 \11\:net35) resistor r=11.1009 c=0 +re94 (\6\:net075 \4\:net075) resistor r=5.3786 c=0 +re95 (\6\:net47 \4\:net47) resistor r=5.3786 c=0 +re96 (net075 \11\:net075) resistor r=2.6252 c=0 +re97 (\11\:net47 net47) resistor r=2.6218 c=0 +re98 (\23\:X1 \24\:X1) resistor r=4 c=0 +re99 (\11\:X0 \6\:X0) resistor r=2.0078 c=0 +re100 (\12\:net0127 net0127) resistor r=5.6983 c=0 +re101 (\22\:net0115 \20\:net0115) resistor r=7.1937 c=0 +re102 (\18\:net075 \23\:net075) resistor r=4.7641 c=0 +re103 (\18\:net47 \23\:net47) resistor r=4.7641 c=0 +re104 (\22\:X0 \21\:X0) resistor r=4.2267 c=0 +re105 (\23\:X0 \20\:X0) resistor r=4.2289 c=0 +re106 (\24\:X0 \5\:X0) resistor r=21.5123 c=0 +re107 (Z3 \3\:Z3) resistor r=3.8779 c=0 +re108 (Z2 \3\:Z2) resistor r=4.033 c=0 +re109 (Z1 \3\:Z1) resistor r=5.9155 c=0 +re110 (Y2 \21\:Y2) resistor r=1.1311 c=0 +re111 (\21\:Y2 \22\:Y2) resistor r=2.7111 c=0 +re112 (\22\:Y2 \23\:Y2) resistor r=10.4714 c=0 +re113 (\23\:Y2 \5\:Y2) resistor r=5.6954 c=0 +re114 (\21\:Y2 \17\:Y2) resistor r=1.078 c=0 +re115 (\22\:Y2 \15\:Y2) resistor r=3.023 c=0 +re116 (\23\:Y2 \6\:Y2) resistor r=3.1738 c=0 +re117 (Y3 \21\:Y3) resistor r=1.1311 c=0 +re118 (\21\:Y3 \22\:Y3) resistor r=2.8324 c=0 +re119 (\22\:Y3 \23\:Y3) resistor r=10.4206 c=0 +re120 (\23\:Y3 \5\:Y3) resistor r=5.6155 c=0 +re121 (\21\:Y3 \17\:Y3) resistor r=1.0707 c=0 +re122 (\22\:Y3 \15\:Y3) resistor r=3.0112 c=0 +re123 (\23\:Y3 \6\:Y3) resistor r=3.1534 c=0 +re124 (Z0 \2\:Z0) resistor r=20.9575 c=0 +rf1 (\1\:X3 \2\:X3) resistor r=0.01 c=0 +rf2 (\3\:X3 \4\:X3) resistor r=0.01 c=0 +rf4 (\5\:X3 \6\:X3) resistor r=0.01 c=0 +rf5 (\5\:Y3 \1\:Y3) resistor r=2.01 c=0 +rf6 (\5\:Y2 \1\:Y2) resistor r=2.01 c=0 +rf7 (\5\:X0 \1\:X0) resistor r=2.01 c=0 +rf9 (I27\|net013 \2\:I27\|net013) resistor r=0.2434 c=0 +rf10 (\2\:I27\|net013 \3\:I27\|net013) resistor r=0.3205 c=0 +rf11 (\2\:I27\|net013 \4\:I27\|net013) resistor r=0.5422 c=0 +rf12 (I20\|net013 \2\:I20\|net013) resistor r=0.2434 c=0 +rf13 (\2\:I20\|net013 \3\:I20\|net013) resistor r=0.3205 c=0 +rf14 (\2\:I20\|net013 \4\:I20\|net013) resistor r=0.5422 c=0 +rf15 (I15\|net013 \2\:I15\|net013) resistor r=0.2434 c=0 +rf16 (\2\:I15\|net013 \3\:I15\|net013) resistor r=0.3205 c=0 +rf17 (\2\:I15\|net013 \4\:I15\|net013) resistor r=0.5422 c=0 +rf18 (I19\|net013 \2\:I19\|net013) resistor r=0.2434 c=0 +rf19 (\2\:I19\|net013 \3\:I19\|net013) resistor r=0.3205 c=0 +rf20 (\2\:I19\|net013 \4\:I19\|net013) resistor r=0.5422 c=0 +rf21 (net090 \2\:net090) resistor r=2.0022 c=0 +rf22 (net13 \2\:net13) resistor r=2.0022 c=0 +rf23 (\3\:net13 \4\:net13) resistor r=0.2066 c=0 +rf24 (\4\:net13 \5\:net13) resistor r=0.6132 c=0 +rf25 (\3\:net090 \4\:net090) resistor r=0.2066 c=0 +rf26 (\4\:net090 \5\:net090) resistor r=0.6132 c=0 +rf27 (\1\:Z0 \2\:Z0) resistor r=0.6132 c=0 +rf28 (\2\:Z0 \3\:Z0) resistor r=0.2066 c=0 +rf29 (net093 \2\:net093) resistor r=0.2066 c=0 +rf30 (\2\:net093 \3\:net093) resistor r=0.6132 c=0 +rf31 (net19 \2\:net19) resistor r=0.285 c=0 +rf32 (net19 \3\:net19) resistor r=0.8307 c=0 +rf33 (I4\|net3 \2\:I4\|net3) resistor r=0.7396 c=0 +rf34 (\2\:I4\|net3 \3\:I4\|net3) resistor r=0.4087 c=0 +rf35 (\3\:I4\|net3 \4\:I4\|net3) resistor r=0.7213 c=0 +rf36 (\2\:I4\|net3 \5\:I4\|net3) resistor r=0.2896 c=0 +rf37 (\2\:I4\|net3 \6\:I4\|net3) resistor r=2.2056 c=0 +rf38 (\3\:I4\|net3 \7\:I4\|net3) resistor r=0.2841 c=0 +rf39 (I9\|net3 \2\:I9\|net3) resistor r=0.7396 c=0 +rf40 (\2\:I9\|net3 \3\:I9\|net3) resistor r=0.4087 c=0 +rf41 (\3\:I9\|net3 \4\:I9\|net3) resistor r=0.7213 c=0 +rf42 (\2\:I9\|net3 \5\:I9\|net3) resistor r=0.2896 c=0 +rf43 (\2\:I9\|net3 \6\:I9\|net3) resistor r=2.2056 c=0 +rf44 (\3\:I9\|net3 \7\:I9\|net3) resistor r=0.2841 c=0 +rf45 (I4\|I4\|Ai \2\:I4\|I4\|Ai) resistor r=0.84 c=0 +rf46 (I4\|I4\|Ai \3\:I4\|I4\|Ai) resistor r=0.2475 c=0 +rf47 (I9\|I4\|Ai \2\:I9\|I4\|Ai) resistor r=0.84 c=0 +rf48 (I9\|I4\|Ai \3\:I9\|I4\|Ai) resistor r=0.2475 c=0 +rf49 (\12\:net090 \18\:net090) resistor r=2.0267 c=0 +rf50 (\19\:net090 \15\:net090) resistor r=0.02222 c=0 +rf51 (\12\:net13 \18\:net13) resistor r=2.0267 c=0 +rf52 (\19\:net13 \15\:net13) resistor r=0.02222 c=0 +rf53 (\4\:net093 \5\:net093) resistor r=2.0111 c=0 +rf54 (I5\|I1\|Bi \2\:I5\|I1\|Bi) resistor r=0.3619 c=0 +rf55 (\2\:I5\|I1\|Bi \3\:I5\|I1\|Bi) resistor r=0.6109 c=0 +rf56 (\2\:I5\|I1\|Bi \4\:I5\|I1\|Bi) resistor r=0.2422 c=0 +rf57 (\5\:I4\|I4\|Bi \6\:I4\|I4\|Bi) resistor r=0.3789 c=0 +rf58 (\6\:I4\|I4\|Bi I4\|I4\|Bi) resistor r=0.2425 c=0 +rf59 (\6\:I4\|I4\|Bi \7\:I4\|I4\|Bi) resistor r=0.3634 c=0 +rf60 (\5\:I9\|I4\|Bi \6\:I9\|I4\|Bi) resistor r=0.3789 c=0 +rf61 (\6\:I9\|I4\|Bi I9\|I4\|Bi) resistor r=0.2425 c=0 +rf62 (\6\:I9\|I4\|Bi \7\:I9\|I4\|Bi) resistor r=0.3634 c=0 +rf63 (\6\:net19 \7\:net19) resistor r=2.0233 c=0 +rf64 (net16 \2\:net16) resistor r=2.0233 c=0 +rf65 (net55 \2\:net55) resistor r=2.01 c=0 +rf66 (\5\:I5\|I3\|net013 \6\:I5\|I3\|net013) resistor r=0.4307 c=0 +rf67 (\6\:I5\|I3\|net013 I5\|I3\|net013) resistor r=0.5507 c=0 +rf68 (\6\:I5\|I3\|net013 \7\:I5\|I3\|net013) resistor r=0.8338 c=0 +rf69 (\8\:I4\|net3 \9\:I4\|net3) resistor r=0.01 c=0 +rf70 (\8\:I9\|net3 \9\:I9\|net3) resistor r=0.01 c=0 +rf71 (\3\:net55 \4\:net55) resistor r=0.002222 c=0 +rf72 (I4\|net1 \2\:I4\|net1) resistor r=0.7023 c=0 +rf73 (\2\:I4\|net1 \3\:I4\|net1) resistor r=0.5764 c=0 +rf74 (\2\:I4\|net1 \4\:I4\|net1) resistor r=0.5108 c=0 +rf75 (I9\|net1 \2\:I9\|net1) resistor r=0.7023 c=0 +rf76 (\2\:I9\|net1 \3\:I9\|net1) resistor r=0.5764 c=0 +rf77 (\2\:I9\|net1 \4\:I9\|net1) resistor r=0.5108 c=0 +rf78 (\5\:net55 \6\:net55) resistor r=0.002222 c=0 +rf79 (net54 \2\:net54) resistor r=0.629 c=0 +rf80 (\2\:net54 \3\:net54) resistor r=0.1083 c=0 +rf81 (\3\:net54 \4\:net54) resistor r=0.1123 c=0 +rf82 (\4\:net54 \5\:net54) resistor r=0.4382 c=0 +rf83 (\2\:net54 \6\:net54) resistor r=0.4386 c=0 +rf84 (\4\:net54 \7\:net54) resistor r=0.6387 c=0 +rf85 (I4\|I3\|Ai \2\:I4\|I3\|Ai) resistor r=0.04192 c=0 +rf86 (\2\:I4\|I3\|Ai \3\:I4\|I3\|Ai) resistor r=0.6961 c=0 +rf87 (\2\:I4\|I3\|Ai \4\:I4\|I3\|Ai) resistor r=0.4006 c=0 +rf88 (I9\|I3\|Ai \2\:I9\|I3\|Ai) resistor r=0.04192 c=0 +rf89 (\2\:I9\|I3\|Ai \3\:I9\|I3\|Ai) resistor r=0.6961 c=0 +rf90 (\2\:I9\|I3\|Ai \4\:I9\|I3\|Ai) resistor r=0.4006 c=0 +rf91 (\14\:net16 \13\:net16) resistor r=0.1956 c=0 +rf92 (\13\:net16 \15\:net16) resistor r=1.0615 c=0 +rf93 (\2\:Z7 \1\:Z7) resistor r=0.1956 c=0 +rf94 (\1\:Z7 \3\:Z7) resistor r=1.0615 c=0 +rf95 (\19\:X3 \20\:X3) resistor r=0.01 c=0 +rf96 (\14\:net55 \15\:net55) resistor r=0.01 c=0 +rf97 (\15\:I4\|net3 \13\:I4\|net3) resistor r=0.08472 c=0 +rf98 (\15\:I9\|net3 \13\:I9\|net3) resistor r=0.08472 c=0 +rf99 (\3\:net21 \2\:net21) resistor r=0.1 c=0 +rf100 (\3\:net15 \2\:net15) resistor r=2.1 c=0 +rf102 (I12\|net013 \2\:I12\|net013) resistor r=0.2434 c=0 +rf103 (\2\:I12\|net013 \3\:I12\|net013) resistor r=0.3205 c=0 +rf104 (\2\:I12\|net013 \4\:I12\|net013) resistor r=0.5422 c=0 +rf105 (\4\:I5\|I1\|Ai \5\:I5\|I1\|Ai) resistor r=0.2765 c=0 +rf106 (\5\:I5\|I1\|Ai \2\:I5\|I1\|Ai) resistor r=0.04519 c=0 +rf107 (\5\:I5\|I1\|Ai \6\:I5\|I1\|Ai) resistor r=0.7634 c=0 +rf108 (\3\:net17 \4\:net17) resistor r=0.2905 c=0 +rf109 (\4\:net17 \5\:net17) resistor r=0.08276 c=0 +rf110 (\5\:net17 \6\:net17) resistor r=0.2973 c=0 +rf111 (\5\:net17 \7\:net17) resistor r=0.4127 c=0 +rf112 (\7\:net17 \8\:net17) resistor r=0.3748 c=0 +rf113 (\7\:net17 \9\:net17) resistor r=0.5859 c=0 +rf114 (\2\:net17 \4\:net17) resistor r=2 c=0 +rf115 (\2\:Z6 \1\:Z6) resistor r=0.2905 c=0 +rf116 (\1\:Z6 \3\:Z6) resistor r=0.08276 c=0 +rf117 (\3\:Z6 \4\:Z6) resistor r=0.2973 c=0 +rf118 (\3\:Z6 \5\:Z6) resistor r=0.4127 c=0 +rf119 (\5\:Z6 \6\:Z6) resistor r=0.3748 c=0 +rf120 (\5\:Z6 \7\:Z6) resistor r=0.5859 c=0 +rf121 (\16\:net55 \20\:net55) resistor r=0.01 c=0 +rf122 (\5\:I4\|net6 \6\:I4\|net6) resistor r=0.7681 c=0 +rf123 (\6\:I4\|net6 I4\|net6) resistor r=0.8057 c=0 +rf124 (\6\:I4\|net6 \7\:I4\|net6) resistor r=0.4319 c=0 +rf125 (\5\:I9\|net6 \6\:I9\|net6) resistor r=0.7681 c=0 +rf126 (\6\:I9\|net6 I9\|net6) resistor r=0.8057 c=0 +rf127 (\6\:I9\|net6 \7\:I9\|net6) resistor r=0.4319 c=0 +rf128 (net39 \2\:net39) resistor r=0.2066 c=0 +rf129 (\2\:net39 \3\:net39) resistor r=0.6132 c=0 +rf131 (I4\|I3\|Bi \4\:I4\|I3\|Bi) resistor r=0.07769 c=0 +rf132 (\4\:I4\|I3\|Bi \5\:I4\|I3\|Bi) resistor r=0.2684 c=0 +rf133 (\4\:I4\|I3\|Bi \6\:I4\|I3\|Bi) resistor r=0.5661 c=0 +rf134 (I9\|I3\|Bi \4\:I9\|I3\|Bi) resistor r=0.07769 c=0 +rf135 (\4\:I9\|I3\|Bi \5\:I9\|I3\|Bi) resistor r=0.2684 c=0 +rf136 (\4\:I9\|I3\|Bi \6\:I9\|I3\|Bi) resistor r=0.5661 c=0 +rf137 (\6\:Y3 \7\:Y3) resistor r=0.01 c=0 +rf138 (\5\:X2 \1\:X2) resistor r=2.01 c=0 +rf139 (\6\:Y2 \7\:Y2) resistor r=0.01 c=0 +rf140 (I18\|net013 \2\:I18\|net013) resistor r=0.2434 c=0 +rf141 (\2\:I18\|net013 \3\:I18\|net013) resistor r=0.3205 c=0 +rf142 (\2\:I18\|net013 \4\:I18\|net013) resistor r=0.5422 c=0 +rf143 (\11\:X2 \7\:X2) resistor r=2.01 c=0 +rf144 (\12\:X2 \13\:X2) resistor r=2.01 c=0 +rf145 (I26\|net013 \2\:I26\|net013) resistor r=0.2434 c=0 +rf146 (\2\:I26\|net013 \3\:I26\|net013) resistor r=0.3205 c=0 +rf147 (\2\:I26\|net013 \4\:I26\|net013) resistor r=0.5422 c=0 +rf148 (I21\|net013 \2\:I21\|net013) resistor r=0.2434 c=0 +rf149 (\2\:I21\|net013 \3\:I21\|net013) resistor r=0.3205 c=0 +rf150 (\2\:I21\|net013 \4\:I21\|net013) resistor r=0.5422 c=0 +rf151 (net38 \2\:net38) resistor r=2.0022 c=0 +rf152 (\3\:net38 \4\:net38) resistor r=0.2066 c=0 +rf153 (\4\:net38 \5\:net38) resistor r=0.6132 c=0 +rf154 (I0\|net3 \2\:I0\|net3) resistor r=0.7396 c=0 +rf155 (\2\:I0\|net3 \3\:I0\|net3) resistor r=0.4087 c=0 +rf156 (\3\:I0\|net3 \4\:I0\|net3) resistor r=0.7213 c=0 +rf157 (\2\:I0\|net3 \5\:I0\|net3) resistor r=0.2896 c=0 +rf158 (\2\:I0\|net3 \6\:I0\|net3) resistor r=2.2056 c=0 +rf159 (\3\:I0\|net3 \7\:I0\|net3) resistor r=0.2841 c=0 +rf160 (net8 \2\:net8) resistor r=0.2066 c=0 +rf161 (\2\:net8 \3\:net8) resistor r=0.6132 c=0 +rf162 (\4\:net8 \5\:net8) resistor r=2.0022 c=0 +rf163 (net087 \2\:net087) resistor r=0.2066 c=0 +rf164 (\2\:net087 \3\:net087) resistor r=0.6132 c=0 +rf165 (\4\:net087 \5\:net087) resistor r=2.0022 c=0 +rf166 (I0\|I4\|Ai \2\:I0\|I4\|Ai) resistor r=0.84 c=0 +rf167 (I0\|I4\|Ai \3\:I0\|I4\|Ai) resistor r=0.2475 c=0 +rf168 (\9\:net38 \10\:net38) resistor r=2.0267 c=0 +rf169 (\11\:net38 \12\:net38) resistor r=0.02222 c=0 +rf170 (I10\|net3 \2\:I10\|net3) resistor r=0.7396 c=0 +rf171 (\2\:I10\|net3 \3\:I10\|net3) resistor r=0.4087 c=0 +rf172 (\3\:I10\|net3 \4\:I10\|net3) resistor r=0.7213 c=0 +rf173 (\2\:I10\|net3 \5\:I10\|net3) resistor r=0.2896 c=0 +rf174 (\2\:I10\|net3 \6\:I10\|net3) resistor r=2.2056 c=0 +rf175 (\3\:I10\|net3 \7\:I10\|net3) resistor r=0.2841 c=0 +rf176 (\5\:I0\|I4\|Bi \6\:I0\|I4\|Bi) resistor r=0.3789 c=0 +rf177 (\6\:I0\|I4\|Bi I0\|I4\|Bi) resistor r=0.2425 c=0 +rf178 (\6\:I0\|I4\|Bi \7\:I0\|I4\|Bi) resistor r=0.3634 c=0 +rf179 (I3\|net3 \2\:I3\|net3) resistor r=0.7396 c=0 +rf180 (\2\:I3\|net3 \3\:I3\|net3) resistor r=0.4087 c=0 +rf181 (\3\:I3\|net3 \4\:I3\|net3) resistor r=0.7213 c=0 +rf182 (\2\:I3\|net3 \5\:I3\|net3) resistor r=0.2896 c=0 +rf183 (\2\:I3\|net3 \6\:I3\|net3) resistor r=2.2056 c=0 +rf184 (\3\:I3\|net3 \7\:I3\|net3) resistor r=0.2841 c=0 +rf185 (\4\:I10\|I4\|Ai \5\:I10\|I4\|Ai) resistor r=0.84 c=0 +rf186 (\4\:I10\|I4\|Ai \3\:I10\|I4\|Ai) resistor r=0.2475 c=0 +rf187 (I3\|I4\|Ai \2\:I3\|I4\|Ai) resistor r=0.84 c=0 +rf188 (I3\|I4\|Ai \3\:I3\|I4\|Ai) resistor r=0.2475 c=0 +rf189 (\10\:net8 \9\:net8) resistor r=0.02667 c=0 +rf190 (\11\:net8 \12\:net8) resistor r=0.02222 c=0 +rf191 (\13\:net39 \4\:net39) resistor r=2.0233 c=0 +rf192 (\5\:I10\|I4\|Bi \6\:I10\|I4\|Bi) resistor r=0.3789 c=0 +rf193 (\6\:I10\|I4\|Bi I10\|I4\|Bi) resistor r=0.2425 c=0 +rf194 (\6\:I10\|I4\|Bi \7\:I10\|I4\|Bi) resistor r=0.3634 c=0 +rf195 (\9\:net087 \10\:net087) resistor r=2.0267 c=0 +rf196 (\11\:net087 \12\:net087) resistor r=0.02222 c=0 +rf197 (\8\:I0\|net3 \9\:I0\|net3) resistor r=0.01 c=0 +rf198 (\5\:I3\|I4\|Bi \6\:I3\|I4\|Bi) resistor r=0.3789 c=0 +rf199 (\6\:I3\|I4\|Bi I3\|I4\|Bi) resistor r=0.2425 c=0 +rf200 (\6\:I3\|I4\|Bi \7\:I3\|I4\|Bi) resistor r=0.3634 c=0 +rf201 (I0\|net1 \2\:I0\|net1) resistor r=0.7023 c=0 +rf202 (\2\:I0\|net1 \3\:I0\|net1) resistor r=0.5764 c=0 +rf203 (\2\:I0\|net1 \4\:I0\|net1) resistor r=0.5108 c=0 +rf204 (\19\:net17 \10\:net17) resistor r=2.0233 c=0 +rf205 (I0\|I3\|Ai \2\:I0\|I3\|Ai) resistor r=0.04192 c=0 +rf206 (\2\:I0\|I3\|Ai \3\:I0\|I3\|Ai) resistor r=0.6961 c=0 +rf207 (\2\:I0\|I3\|Ai \4\:I0\|I3\|Ai) resistor r=0.4006 c=0 +rf208 (\22\:net55 \21\:net55) resistor r=0.1956 c=0 +rf209 (\21\:net55 \23\:net55) resistor r=1.0615 c=0 +rf210 (\19\:net54 \10\:net54) resistor r=2.0233 c=0 +rf211 (\8\:I10\|net3 \9\:I10\|net3) resistor r=0.01 c=0 +rf212 (\8\:I3\|net3 \9\:I3\|net3) resistor r=0.01 c=0 +rf213 (I10\|net1 \2\:I10\|net1) resistor r=0.7023 c=0 +rf214 (\2\:I10\|net1 \3\:I10\|net1) resistor r=0.5764 c=0 +rf215 (\2\:I10\|net1 \4\:I10\|net1) resistor r=0.5108 c=0 +rf216 (I3\|net1 \2\:I3\|net1) resistor r=0.7023 c=0 +rf217 (\2\:I3\|net1 \3\:I3\|net1) resistor r=0.5764 c=0 +rf218 (\2\:I3\|net1 \4\:I3\|net1) resistor r=0.5108 c=0 +rf219 (I10\|I3\|Ai \2\:I10\|I3\|Ai) resistor r=0.04192 c=0 +rf220 (\2\:I10\|I3\|Ai \3\:I10\|I3\|Ai) resistor r=0.6961 c=0 +rf221 (\2\:I10\|I3\|Ai \4\:I10\|I3\|Ai) resistor r=0.4006 c=0 +rf222 (\13\:I0\|net3 \14\:I0\|net3) resistor r=2.0847 c=0 +rf223 (\13\:net15 \11\:net15) resistor r=0.1956 c=0 +rf224 (\11\:net15 \14\:net15) resistor r=1.0615 c=0 +rf225 (net31 \2\:net31) resistor r=2.1 c=0 +rf226 (I3\|I3\|Ai \2\:I3\|I3\|Ai) resistor r=0.04192 c=0 +rf227 (\2\:I3\|I3\|Ai \3\:I3\|I3\|Ai) resistor r=0.6961 c=0 +rf228 (\2\:I3\|I3\|Ai \4\:I3\|I3\|Ai) resistor r=0.4006 c=0 +rf229 (\11\:net21 \12\:net21) resistor r=0.1956 c=0 +rf230 (\12\:net21 \13\:net21) resistor r=1.0615 c=0 +rf231 (\15\:I10\|net3 \13\:I10\|net3) resistor r=0.08472 c=0 +rf232 (net29 \2\:net29) resistor r=0.2905 c=0 +rf233 (\2\:net29 \3\:net29) resistor r=0.08276 c=0 +rf234 (\3\:net29 \4\:net29) resistor r=0.2973 c=0 +rf235 (\3\:net29 \5\:net29) resistor r=0.4127 c=0 +rf236 (\5\:net29 \6\:net29) resistor r=0.3748 c=0 +rf237 (\5\:net29 \7\:net29) resistor r=0.5859 c=0 +rf238 (net1 \2\:net1) resistor r=2.1 c=0 +rf239 (\5\:I0\|net6 \6\:I0\|net6) resistor r=0.7681 c=0 +rf240 (\6\:I0\|net6 I0\|net6) resistor r=0.8057 c=0 +rf241 (\6\:I0\|net6 \7\:I0\|net6) resistor r=0.4319 c=0 +rf242 (\13\:I3\|net3 \14\:I3\|net3) resistor r=2.0847 c=0 +rf243 (net26 \2\:net26) resistor r=2.1 c=0 +rf244 (\1\:Z5 \2\:Z5) resistor r=0.2905 c=0 +rf245 (\2\:Z5 \3\:Z5) resistor r=0.08276 c=0 +rf246 (\3\:Z5 \4\:Z5) resistor r=0.2973 c=0 +rf247 (\3\:Z5 \5\:Z5) resistor r=0.4127 c=0 +rf248 (\5\:Z5 \6\:Z5) resistor r=0.3748 c=0 +rf249 (\5\:Z5 \7\:Z5) resistor r=0.5859 c=0 +rf250 (\5\:I10\|net6 \6\:I10\|net6) resistor r=0.7681 c=0 +rf251 (\6\:I10\|net6 I10\|net6) resistor r=0.8057 c=0 +rf252 (\6\:I10\|net6 \7\:I10\|net6) resistor r=0.4319 c=0 +rf253 (net0100 \2\:net0100) resistor r=0.2905 c=0 +rf254 (\2\:net0100 \3\:net0100) resistor r=0.08276 c=0 +rf255 (\3\:net0100 \4\:net0100) resistor r=0.2973 c=0 +rf256 (\3\:net0100 \5\:net0100) resistor r=0.4127 c=0 +rf257 (\5\:net0100 \6\:net0100) resistor r=0.3748 c=0 +rf258 (\5\:net0100 \7\:net0100) resistor r=0.5859 c=0 +rf259 (\5\:I3\|net6 \6\:I3\|net6) resistor r=0.7681 c=0 +rf260 (\6\:I3\|net6 I3\|net6) resistor r=0.8057 c=0 +rf261 (\6\:I3\|net6 \7\:I3\|net6) resistor r=0.4319 c=0 +rf262 (I0\|I3\|Bi \2\:I0\|I3\|Bi) resistor r=0.07769 c=0 +rf263 (\2\:I0\|I3\|Bi \3\:I0\|I3\|Bi) resistor r=0.2684 c=0 +rf264 (\2\:I0\|I3\|Bi \4\:I0\|I3\|Bi) resistor r=0.5661 c=0 +rf265 (I1\|I3\|Bi \2\:I1\|I3\|Bi) resistor r=0.2684 c=0 +rf266 (\2\:I1\|I3\|Bi \3\:I1\|I3\|Bi) resistor r=0.07769 c=0 +rf267 (\2\:I1\|I3\|Bi \4\:I1\|I3\|Bi) resistor r=0.5661 c=0 +rf268 (I10\|I3\|Bi \4\:I10\|I3\|Bi) resistor r=0.07769 c=0 +rf269 (\4\:I10\|I3\|Bi \5\:I10\|I3\|Bi) resistor r=0.2684 c=0 +rf270 (\4\:I10\|I3\|Bi \6\:I10\|I3\|Bi) resistor r=0.5661 c=0 +rf271 (I3\|I3\|Bi \4\:I3\|I3\|Bi) resistor r=0.07769 c=0 +rf272 (\4\:I3\|I3\|Bi \5\:I3\|I3\|Bi) resistor r=0.2684 c=0 +rf273 (\4\:I3\|I3\|Bi \6\:I3\|I3\|Bi) resistor r=0.5661 c=0 +rf274 (I11\|I3\|Bi \2\:I11\|I3\|Bi) resistor r=0.2684 c=0 +rf275 (\2\:I11\|I3\|Bi \3\:I11\|I3\|Bi) resistor r=0.07769 c=0 +rf276 (\2\:I11\|I3\|Bi \4\:I11\|I3\|Bi) resistor r=0.5661 c=0 +rf277 (net32 \2\:net32) resistor r=0.2973 c=0 +rf278 (\2\:net32 \3\:net32) resistor r=0.08276 c=0 +rf279 (\3\:net32 \4\:net32) resistor r=0.2905 c=0 +rf280 (\2\:net32 \5\:net32) resistor r=0.4127 c=0 +rf281 (\5\:net32 \6\:net32) resistor r=0.5859 c=0 +rf282 (\5\:net32 \7\:net32) resistor r=0.3748 c=0 +rf283 (I2\|I3\|Bi \2\:I2\|I3\|Bi) resistor r=0.2684 c=0 +rf284 (\2\:I2\|I3\|Bi \3\:I2\|I3\|Bi) resistor r=0.07769 c=0 +rf285 (\2\:I2\|I3\|Bi \4\:I2\|I3\|Bi) resistor r=0.5661 c=0 +rf286 (net35 \2\:net35) resistor r=2.1 c=0 +rf287 (\4\:I1\|net3 \7\:I1\|net3) resistor r=2.0847 c=0 +rf288 (I1\|net6 \2\:I1\|net6) resistor r=0.7681 c=0 +rf289 (\2\:I1\|net6 \3\:I1\|net6) resistor r=0.4319 c=0 +rf290 (\2\:I1\|net6 \4\:I1\|net6) resistor r=0.8057 c=0 +rf291 (\2\:Z4 \3\:Z4) resistor r=0.2973 c=0 +rf292 (\3\:Z4 \1\:Z4) resistor r=0.08276 c=0 +rf293 (\1\:Z4 \4\:Z4) resistor r=0.2905 c=0 +rf294 (\3\:Z4 \5\:Z4) resistor r=0.4127 c=0 +rf295 (\5\:Z4 \6\:Z4) resistor r=0.5859 c=0 +rf296 (\5\:Z4 \7\:Z4) resistor r=0.3748 c=0 +rf297 (\2\:I1\|I3\|Ai \4\:I1\|I3\|Ai) resistor r=0.04192 c=0 +rf298 (\4\:I1\|I3\|Ai \5\:I1\|I3\|Ai) resistor r=0.6961 c=0 +rf299 (\4\:I1\|I3\|Ai \6\:I1\|I3\|Ai) resistor r=0.4006 c=0 +rf300 (\10\:net31 \11\:net31) resistor r=0.1956 c=0 +rf301 (\11\:net31 \12\:net31) resistor r=1.0615 c=0 +rf302 (net44 \2\:net44) resistor r=0.2973 c=0 +rf303 (\2\:net44 \3\:net44) resistor r=0.08276 c=0 +rf304 (\3\:net44 \4\:net44) resistor r=0.2905 c=0 +rf305 (\2\:net44 \5\:net44) resistor r=0.4127 c=0 +rf306 (\5\:net44 \6\:net44) resistor r=0.5859 c=0 +rf307 (\5\:net44 \7\:net44) resistor r=0.3748 c=0 +rf308 (net5 \2\:net5) resistor r=2.1 c=0 +rf309 (\8\:I1\|net3 \12\:I1\|net3) resistor r=0.01 c=0 +rf310 (\4\:I11\|net3 \7\:I11\|net3) resistor r=2.0847 c=0 +rf311 (I11\|net6 \2\:I11\|net6) resistor r=0.7681 c=0 +rf312 (\2\:I11\|net6 \3\:I11\|net6) resistor r=0.4319 c=0 +rf313 (\2\:I11\|net6 \4\:I11\|net6) resistor r=0.8057 c=0 +rf314 (net095 \2\:net095) resistor r=2.0233 c=0 +rf315 (net45 \2\:net45) resistor r=2.1 c=0 +rf316 (\4\:I2\|net3 \7\:I2\|net3) resistor r=2.0847 c=0 +rf317 (I2\|net6 \2\:I2\|net6) resistor r=0.7681 c=0 +rf318 (\2\:I2\|net6 \3\:I2\|net6) resistor r=0.4319 c=0 +rf319 (\2\:I2\|net6 \4\:I2\|net6) resistor r=0.8057 c=0 +rf320 (\2\:I11\|I3\|Ai \4\:I11\|I3\|Ai) resistor r=0.04192 c=0 +rf321 (\4\:I11\|I3\|Ai \5\:I11\|I3\|Ai) resistor r=0.6961 c=0 +rf322 (\4\:I11\|I3\|Ai \6\:I11\|I3\|Ai) resistor r=0.4006 c=0 +rf323 (\10\:net1 \11\:net1) resistor r=0.1956 c=0 +rf324 (\11\:net1 \12\:net1) resistor r=1.0615 c=0 +rf325 (net34 \2\:net34) resistor r=0.02222 c=0 +rf326 (\3\:net34 \4\:net34) resistor r=2.0267 c=0 +rf327 (\5\:I1\|net1 \6\:I1\|net1) resistor r=0.7023 c=0 +rf328 (\6\:I1\|net1 I1\|net1) resistor r=0.5108 c=0 +rf329 (\6\:I1\|net1 \7\:I1\|net1) resistor r=0.5764 c=0 +rf330 (\8\:I11\|net3 \12\:I11\|net3) resistor r=0.01 c=0 +rf331 (\2\:I2\|I3\|Ai \4\:I2\|I3\|Ai) resistor r=0.04192 c=0 +rf332 (\4\:I2\|I3\|Ai \5\:I2\|I3\|Ai) resistor r=0.6961 c=0 +rf333 (\4\:I2\|I3\|Ai \6\:I2\|I3\|Ai) resistor r=0.4006 c=0 +rf334 (I1\|I4\|Ai \2\:I1\|I4\|Ai) resistor r=0.3634 c=0 +rf335 (\2\:I1\|I4\|Ai \3\:I1\|I4\|Ai) resistor r=0.3789 c=0 +rf336 (\2\:I1\|I4\|Ai \4\:I1\|I4\|Ai) resistor r=0.2425 c=0 +rf337 (\10\:net26 \11\:net26) resistor r=0.1956 c=0 +rf338 (\11\:net26 \12\:net26) resistor r=1.0615 c=0 +rf339 (I1\|I4\|Bi \2\:I1\|I4\|Bi) resistor r=0.84 c=0 +rf340 (\2\:I1\|I4\|Bi \3\:I1\|I4\|Bi) resistor r=0.2475 c=0 +rf341 (\9\:net0100 \10\:net0100) resistor r=2.0233 c=0 +rf342 (\8\:I2\|net3 \9\:I2\|net3) resistor r=0.01 c=0 +rf343 (\9\:net29 \10\:net29) resistor r=2.0233 c=0 +rf344 (net078 \2\:net078) resistor r=0.02222 c=0 +rf345 (\3\:net078 \4\:net078) resistor r=2.0267 c=0 +rf346 (\5\:I11\|net1 \6\:I11\|net1) resistor r=0.7023 c=0 +rf347 (\6\:I11\|net1 I11\|net1) resistor r=0.5108 c=0 +rf348 (\6\:I11\|net1 \7\:I11\|net1) resistor r=0.5764 c=0 +rf349 (\19\:X2 \20\:X2) resistor r=0.01 c=0 +rf350 (\12\:net34 \13\:net34) resistor r=2.0022 c=0 +rf351 (I11\|I4\|Bi \2\:I11\|I4\|Bi) resistor r=0.3634 c=0 +rf352 (\2\:I11\|I4\|Bi \3\:I11\|I4\|Bi) resistor r=0.3789 c=0 +rf353 (\2\:I11\|I4\|Bi \4\:I11\|I4\|Bi) resistor r=0.2425 c=0 +rf354 (net28 \2\:net28) resistor r=0.02222 c=0 +rf355 (\3\:net28 \4\:net28) resistor r=2.0267 c=0 +rf356 (\5\:I2\|net1 \6\:I2\|net1) resistor r=0.7023 c=0 +rf357 (\6\:I2\|net1 I2\|net1) resistor r=0.5108 c=0 +rf358 (\6\:I2\|net1 \7\:I2\|net1) resistor r=0.5764 c=0 +rf359 (I11\|I4\|Ai \2\:I11\|I4\|Ai) resistor r=0.84 c=0 +rf360 (\2\:I11\|I4\|Ai \3\:I11\|I4\|Ai) resistor r=0.2475 c=0 +rf361 (\15\:I1\|net3 \16\:I1\|net3) resistor r=0.7213 c=0 +rf362 (\16\:I1\|net3 \17\:I1\|net3) resistor r=0.4087 c=0 +rf363 (\17\:I1\|net3 \13\:I1\|net3) resistor r=0.2056 c=0 +rf364 (\16\:I1\|net3 \18\:I1\|net3) resistor r=0.2841 c=0 +rf365 (\17\:I1\|net3 \19\:I1\|net3) resistor r=0.2896 c=0 +rf366 (\17\:I1\|net3 \20\:I1\|net3) resistor r=0.7396 c=0 +rf367 (I2\|I4\|Bi \2\:I2\|I4\|Bi) resistor r=0.3634 c=0 +rf368 (\2\:I2\|I4\|Bi \3\:I2\|I4\|Bi) resistor r=0.3789 c=0 +rf369 (\2\:I2\|I4\|Bi \4\:I2\|I4\|Bi) resistor r=0.2425 c=0 +rf370 (I2\|I4\|Ai \2\:I2\|I4\|Ai) resistor r=0.84 c=0 +rf371 (\2\:I2\|I4\|Ai \3\:I2\|I4\|Ai) resistor r=0.2475 c=0 +rf373 (I13\|net013 \2\:I13\|net013) resistor r=0.2434 c=0 +rf374 (\2\:I13\|net013 \3\:I13\|net013) resistor r=0.3205 c=0 +rf375 (\2\:I13\|net013 \4\:I13\|net013) resistor r=0.5422 c=0 +rf376 (\12\:net078 \13\:net078) resistor r=2.0022 c=0 +rf377 (\15\:I11\|net3 \16\:I11\|net3) resistor r=0.7213 c=0 +rf378 (\16\:I11\|net3 \17\:I11\|net3) resistor r=0.4087 c=0 +rf379 (\17\:I11\|net3 \13\:I11\|net3) resistor r=0.2056 c=0 +rf380 (\16\:I11\|net3 \18\:I11\|net3) resistor r=0.2841 c=0 +rf381 (\17\:I11\|net3 \19\:I11\|net3) resistor r=0.2896 c=0 +rf382 (\17\:I11\|net3 \20\:I11\|net3) resistor r=0.7396 c=0 +rf383 (\12\:net28 \13\:net28) resistor r=2.0022 c=0 +rf384 (\17\:net34 \18\:net34) resistor r=0.2066 c=0 +rf385 (\18\:net34 \19\:net34) resistor r=0.6132 c=0 +rf386 (\14\:net078 \15\:net078) resistor r=0.2066 c=0 +rf387 (\15\:net078 \16\:net078) resistor r=0.6132 c=0 +rf388 (\15\:net28 \14\:net28) resistor r=0.2066 c=0 +rf389 (\14\:net28 \16\:net28) resistor r=0.6132 c=0 +rf390 (\15\:I2\|net3 \16\:I2\|net3) resistor r=0.7213 c=0 +rf391 (\16\:I2\|net3 \17\:I2\|net3) resistor r=0.4087 c=0 +rf392 (\17\:I2\|net3 \13\:I2\|net3) resistor r=0.2056 c=0 +rf393 (\16\:I2\|net3 \18\:I2\|net3) resistor r=0.2841 c=0 +rf394 (\17\:I2\|net3 \19\:I2\|net3) resistor r=0.2896 c=0 +rf395 (\17\:I2\|net3 \20\:I2\|net3) resistor r=0.7396 c=0 +rf396 (\5\:net0115 \3\:net0115) resistor r=0.01 c=0 +rf397 (\1\:X1 \2\:X1) resistor r=0.01 c=0 +rf398 (\7\:X1 \8\:X1) resistor r=2.01 c=0 +rf399 (I6\|I1\|Ai \2\:I6\|I1\|Ai) resistor r=0.04519 c=0 +rf400 (\2\:I6\|I1\|Ai \3\:I6\|I1\|Ai) resistor r=0.7634 c=0 +rf401 (\2\:I6\|I1\|Ai \4\:I6\|I1\|Ai) resistor r=0.2765 c=0 +rf402 (\13\:X1 \14\:X1) resistor r=2.01 c=0 +rf404 (I16\|net013 \2\:I16\|net013) resistor r=0.2434 c=0 +rf405 (\2\:I16\|net013 \3\:I16\|net013) resistor r=0.3205 c=0 +rf406 (\2\:I16\|net013 \4\:I16\|net013) resistor r=0.5422 c=0 +rf407 (\11\:Y3 \15\:Y3) resistor r=0.01 c=0 +rf408 (\5\:I24\|net013 \6\:I24\|net013) resistor r=0.236 c=0 +rf409 (\6\:I24\|net013 I24\|net013) resistor r=0.2322 c=0 +rf410 (\6\:I24\|net013 \7\:I24\|net013) resistor r=0.5701 c=0 +rf411 (\6\:net0115 \7\:net0115) resistor r=0.01 c=0 +rf412 (\11\:Y2 \15\:Y2) resistor r=0.01 c=0 +rf413 (\5\:I23\|net013 \6\:I23\|net013) resistor r=0.236 c=0 +rf414 (\6\:I23\|net013 I23\|net013) resistor r=0.2322 c=0 +rf415 (\6\:I23\|net013 \7\:I23\|net013) resistor r=0.5701 c=0 +rf416 (\11\:net095 \12\:net095) resistor r=0.2066 c=0 +rf417 (\12\:net095 \13\:net095) resistor r=0.6132 c=0 +rf418 (\8\:net0115 \9\:net0115) resistor r=0.002222 c=0 +rf419 (\10\:net0115 \11\:net0115) resistor r=0.002222 c=0 +rf420 (\1\:Z1 \2\:Z1) resistor r=0.4382 c=0 +rf421 (\2\:Z1 \3\:Z1) resistor r=0.1123 c=0 +rf422 (\3\:Z1 \4\:Z1) resistor r=0.1083 c=0 +rf423 (\4\:Z1 \5\:Z1) resistor r=0.629 c=0 +rf424 (\2\:Z1 \6\:Z1) resistor r=0.6387 c=0 +rf425 (\4\:Z1 \7\:Z1) resistor r=0.4386 c=0 +rf426 (\15\:net0115 \20\:net0115) resistor r=2.01 c=0 +rf427 (\12\:net5 \13\:net5) resistor r=0.285 c=0 +rf428 (\12\:net5 \14\:net5) resistor r=0.8307 c=0 +rf429 (\12\:net45 \13\:net45) resistor r=0.285 c=0 +rf430 (\12\:net45 \14\:net45) resistor r=0.8307 c=0 +rf431 (net0127 \2\:net0127) resistor r=2.0111 c=0 +rf432 (\9\:net44 \10\:net44) resistor r=2.0111 c=0 +rf433 (I8\|I1\|Bi \2\:I8\|I1\|Bi) resistor r=0.3619 c=0 +rf434 (\2\:I8\|I1\|Bi \3\:I8\|I1\|Bi) resistor r=0.6109 c=0 +rf435 (\2\:I8\|I1\|Bi \4\:I8\|I1\|Bi) resistor r=0.2422 c=0 +rf436 (\9\:net32 \10\:net32) resistor r=2.0111 c=0 +rf437 (I7\|I1\|Bi \2\:I7\|I1\|Bi) resistor r=0.3619 c=0 +rf438 (\2\:I7\|I1\|Bi \3\:I7\|I1\|Bi) resistor r=0.6109 c=0 +rf439 (\2\:I7\|I1\|Bi \4\:I7\|I1\|Bi) resistor r=0.2422 c=0 +rf440 (\5\:I6\|I1\|Bi \6\:I6\|I1\|Bi) resistor r=0.3619 c=0 +rf441 (\6\:I6\|I1\|Bi I6\|I1\|Bi) resistor r=0.2422 c=0 +rf442 (\6\:I6\|I1\|Bi \7\:I6\|I1\|Bi) resistor r=0.6109 c=0 +rf443 (\5\:I6\|I3\|net013 \6\:I6\|I3\|net013) resistor r=0.4307 c=0 +rf444 (\6\:I6\|I3\|net013 \7\:I6\|I3\|net013) resistor r=0.8338 c=0 +rf445 (\6\:I6\|I3\|net013 \3\:I6\|I3\|net013) resistor r=0.5507 c=0 +rf446 (net075 \2\:net075) resistor r=2.01 c=0 +rf447 (net47 \2\:net47) resistor r=2.01 c=0 +rf448 (\10\:net35 \11\:net35) resistor r=0.8307 c=0 +rf449 (\11\:net35 \12\:net35) resistor r=0.285 c=0 +rf450 (\5\:I8\|I3\|net013 \6\:I8\|I3\|net013) resistor r=0.4307 c=0 +rf451 (\6\:I8\|I3\|net013 I8\|I3\|net013) resistor r=0.5507 c=0 +rf452 (\6\:I8\|I3\|net013 \7\:I8\|I3\|net013) resistor r=0.8338 c=0 +rf453 (\5\:I7\|I3\|net013 \6\:I7\|I3\|net013) resistor r=0.4307 c=0 +rf454 (\6\:I7\|I3\|net013 I7\|I3\|net013) resistor r=0.5507 c=0 +rf455 (\6\:I7\|I3\|net013 \7\:I7\|I3\|net013) resistor r=0.8338 c=0 +rf456 (\3\:net075 \4\:net075) resistor r=0.002222 c=0 +rf457 (\3\:net47 \4\:net47) resistor r=0.002222 c=0 +rf458 (\5\:net075 \6\:net075) resistor r=0.002222 c=0 +rf459 (\5\:net47 \6\:net47) resistor r=0.002222 c=0 +rf460 (\10\:net075 \11\:net075) resistor r=0.2066 c=0 +rf461 (\11\:net075 \12\:net075) resistor r=0.6132 c=0 +rf462 (\10\:net47 \11\:net47) resistor r=0.2066 c=0 +rf463 (\11\:net47 \12\:net47) resistor r=0.6132 c=0 +rf464 (\23\:X1 \21\:X1) resistor r=0.01 c=0 +rf466 (\1\:Z3 \2\:Z3) resistor r=0.629 c=0 +rf467 (\2\:Z3 \3\:Z3) resistor r=0.1083 c=0 +rf468 (\3\:Z3 \4\:Z3) resistor r=0.1123 c=0 +rf469 (\4\:Z3 \5\:Z3) resistor r=0.4382 c=0 +rf470 (\2\:Z3 \6\:Z3) resistor r=0.4386 c=0 +rf471 (\4\:Z3 \7\:Z3) resistor r=0.6387 c=0 +rf472 (\1\:Z2 \2\:Z2) resistor r=0.629 c=0 +rf473 (\2\:Z2 \3\:Z2) resistor r=0.1083 c=0 +rf474 (\3\:Z2 \4\:Z2) resistor r=0.1123 c=0 +rf475 (\4\:Z2 \5\:Z2) resistor r=0.4382 c=0 +rf476 (\2\:Z2 \6\:Z2) resistor r=0.4386 c=0 +rf477 (\4\:Z2 \7\:Z2) resistor r=0.6387 c=0 +rf478 (\17\:net075 \18\:net075) resistor r=0.01 c=0 +rf479 (\17\:net47 \18\:net47) resistor r=0.01 c=0 +rf481 (\6\:X0 \7\:X0) resistor r=2.01 c=0 +rf482 (I14\|net013 \2\:I14\|net013) resistor r=0.2434 c=0 +rf483 (\2\:I14\|net013 \3\:I14\|net013) resistor r=0.3205 c=0 +rf484 (\2\:I14\|net013 \4\:I14\|net013) resistor r=0.5422 c=0 +rf485 (I17\|net013 \2\:I17\|net013) resistor r=0.2434 c=0 +rf486 (\2\:I17\|net013 \3\:I17\|net013) resistor r=0.3205 c=0 +rf487 (\2\:I17\|net013 \4\:I17\|net013) resistor r=0.5422 c=0 +rf488 (\16\:Y3 \17\:Y3) resistor r=2.01 c=0 +rf489 (\16\:Y2 \17\:Y2) resistor r=2.01 c=0 +rf490 (\4\:I8\|I1\|Ai \5\:I8\|I1\|Ai) resistor r=0.2765 c=0 +rf491 (\5\:I8\|I1\|Ai \2\:I8\|I1\|Ai) resistor r=0.04519 c=0 +rf492 (\5\:I8\|I1\|Ai \6\:I8\|I1\|Ai) resistor r=0.7634 c=0 +rf493 (\4\:I7\|I1\|Ai \5\:I7\|I1\|Ai) resistor r=0.2765 c=0 +rf494 (\5\:I7\|I1\|Ai \2\:I7\|I1\|Ai) resistor r=0.04519 c=0 +rf495 (\5\:I7\|I1\|Ai \6\:I7\|I1\|Ai) resistor r=0.7634 c=0 +rf496 (\12\:X0 \20\:X0) resistor r=0.01 c=0 +rf497 (\16\:X0 \21\:X0) resistor r=0.01 c=0 +rf498 (\11\:net0127 \12\:net0127) resistor r=0.2066 c=0 +rf499 (\12\:net0127 \13\:net0127) resistor r=0.6132 c=0 +rf500 (\21\:net0115 \22\:net0115) resistor r=0.6132 c=0 +rf501 (\22\:net0115 \23\:net0115) resistor r=0.2066 c=0 +rf502 (\5\:I25\|net013 \6\:I25\|net013) resistor r=0.236 c=0 +rf503 (\6\:I25\|net013 I25\|net013) resistor r=0.2322 c=0 +rf504 (\6\:I25\|net013 \7\:I25\|net013) resistor r=0.5701 c=0 +rf505 (\5\:I22\|net013 \6\:I22\|net013) resistor r=0.236 c=0 +rf506 (\6\:I22\|net013 I22\|net013) resistor r=0.2322 c=0 +rf507 (\6\:I22\|net013 \7\:I22\|net013) resistor r=0.5701 c=0 +rf508 (\19\:net075 \23\:net075) resistor r=0.01 c=0 +rf509 (\19\:net47 \23\:net47) resistor r=0.01 c=0 +rf510 (\1\:gnd! \2\:gnd!) resistor r=0.5373 c=0 +rf511 (\2\:gnd! \3\:gnd!) resistor r=0.06105 c=0 +rf512 (\3\:gnd! \4\:gnd!) resistor r=0.089 c=0 +rf513 (\4\:gnd! \5\:gnd!) resistor r=0.1325 c=0 +rf514 (\5\:gnd! \6\:gnd!) resistor r=0.0567 c=0 +rf515 (\6\:gnd! \7\:gnd!) resistor r=0.05137 c=0 +rf516 (\7\:gnd! \8\:gnd!) resistor r=0.04013 c=0 +rf517 (\8\:gnd! \9\:gnd!) resistor r=0.1485 c=0 +rf518 (\9\:gnd! \10\:gnd!) resistor r=0.07027 c=0 +rf519 (\10\:gnd! \11\:gnd!) resistor r=0.07573 c=0 +rf520 (\11\:gnd! \12\:gnd!) resistor r=0.1984 c=0 +rf521 (\12\:gnd! \13\:gnd!) resistor r=0.1201 c=0 +rf522 (\13\:gnd! \14\:gnd!) resistor r=0.02927 c=0 +rf523 (\14\:gnd! \15\:gnd!) resistor r=0.03312 c=0 +rf524 (\15\:gnd! \16\:gnd!) resistor r=0.09389 c=0 +rf525 (\16\:gnd! \17\:gnd!) resistor r=0.07629 c=0 +rf526 (\17\:gnd! \18\:gnd!) resistor r=0.05008 c=0 +rf527 (\18\:gnd! \19\:gnd!) resistor r=0.02223 c=0 +rf528 (\19\:gnd! \20\:gnd!) resistor r=0.1485 c=0 +rf529 (\2\:gnd! \21\:gnd!) resistor r=0.4051 c=0 +rf530 (\2\:gnd! \22\:gnd!) resistor r=0.4778 c=0 +rf531 (\3\:gnd! \23\:gnd!) resistor r=0.3083 c=0 +rf532 (\5\:gnd! \24\:gnd!) resistor r=0.4782 c=0 +rf533 (\5\:gnd! \25\:gnd!) resistor r=0.4924 c=0 +rf534 (\6\:gnd! \26\:gnd!) resistor r=0.3585 c=0 +rf535 (\7\:gnd! \27\:gnd!) resistor r=0.3845 c=0 +rf536 (\10\:gnd! \28\:gnd!) resistor r=0.3925 c=0 +rf537 (\10\:gnd! \29\:gnd!) resistor r=0.4802 c=0 +rf538 (\11\:gnd! \30\:gnd!) resistor r=0.44 c=0 +rf539 (\12\:gnd! \31\:gnd!) resistor r=0.3843 c=0 +rf540 (\12\:gnd! \32\:gnd!) resistor r=0.4444 c=0 +rf541 (\13\:gnd! \33\:gnd!) resistor r=0.3833 c=0 +rf542 (\15\:gnd! \34\:gnd!) resistor r=0.3817 c=0 +rf543 (\15\:gnd! \35\:gnd!) resistor r=0.4721 c=0 +rf544 (\16\:gnd! \36\:gnd!) resistor r=0.4967 c=0 +rf545 (\17\:gnd! \37\:gnd!) resistor r=0.3196 c=0 +rf546 (\18\:gnd! \38\:gnd!) resistor r=0.3196 c=0 +rf547 (\20\:gnd! \39\:gnd!) resistor r=0.4346 c=0 +rf548 (\20\:gnd! \40\:gnd!) resistor r=0.486 c=0 +rf549 (\20\:gnd! \41\:gnd!) resistor r=0.1486 c=0 +rf550 (\41\:gnd! \42\:gnd!) resistor r=0.03801 c=0 +rf551 (\42\:gnd! \43\:gnd!) resistor r=0.07419 c=0 +rf552 (\43\:gnd! \44\:gnd!) resistor r=0.3142 c=0 +rf553 (\42\:gnd! \45\:gnd!) resistor r=0.3864 c=0 +rf554 (\43\:gnd! \46\:gnd!) resistor r=0.0911 c=0 +rf555 (\46\:gnd! \47\:gnd!) resistor r=0.06504 c=0 +rf556 (\47\:gnd! \48\:gnd!) resistor r=0.3175 c=0 +rf557 (\47\:gnd! \49\:gnd!) resistor r=0.04775 c=0 +rf558 (\49\:gnd! \50\:gnd!) resistor r=0.4116 c=0 +rf559 (\49\:gnd! \51\:gnd!) resistor r=0.03353 c=0 +rf560 (\51\:gnd! \52\:gnd!) resistor r=0.07914 c=0 +rf561 (\52\:gnd! \53\:gnd!) resistor r=0.05225 c=0 +rf562 (\53\:gnd! \54\:gnd!) resistor r=0.4218 c=0 +rf563 (\49\:gnd! \55\:gnd!) resistor r=0.4813 c=0 +rf564 (\52\:gnd! \56\:gnd!) resistor r=0.3864 c=0 +rf565 (\53\:gnd! \57\:gnd!) resistor r=0.1034 c=0 +rf566 (\57\:gnd! \58\:gnd!) resistor r=0.04537 c=0 +rf567 (\58\:gnd! \59\:gnd!) resistor r=0.05274 c=0 +rf568 (\59\:gnd! \60\:gnd!) resistor r=0.3142 c=0 +rf569 (\53\:gnd! \61\:gnd!) resistor r=0.4674 c=0 +rf570 (\57\:gnd! \62\:gnd!) resistor r=0.3864 c=0 +rf571 (\59\:gnd! \63\:gnd!) resistor r=0.09297 c=0 +rf572 (\63\:gnd! \64\:gnd!) resistor r=0.03064 c=0 +rf573 (\64\:gnd! \65\:gnd!) resistor r=0.3023 c=0 +rf574 (\64\:gnd! \66\:gnd!) resistor r=0.06745 c=0 +rf575 (\66\:gnd! \67\:gnd!) resistor r=0.3835 c=0 +rf576 (\66\:gnd! \68\:gnd!) resistor r=0.04394 c=0 +rf577 (\68\:gnd! \69\:gnd!) resistor r=0.1358 c=0 +rf578 (\69\:gnd! \70\:gnd!) resistor r=0.04148 c=0 +rf579 (\70\:gnd! \71\:gnd!) resistor r=0.4407 c=0 +rf580 (\66\:gnd! \72\:gnd!) resistor r=0.4754 c=0 +rf581 (\69\:gnd! \73\:gnd!) resistor r=0.3833 c=0 +rf582 (\70\:gnd! \74\:gnd!) resistor r=0.1489 c=0 +rf583 (\74\:gnd! \75\:gnd!) resistor r=0.4043 c=0 +rf584 (\74\:gnd! \76\:gnd!) resistor r=0.07477 c=0 +rf585 (\76\:gnd! \77\:gnd!) resistor r=0.3848 c=0 +rf586 (\76\:gnd! \78\:gnd!) resistor r=0.1353 c=0 +rf587 (\78\:gnd! \79\:gnd!) resistor r=0.3869 c=0 +rf588 (\76\:gnd! \80\:gnd!) resistor r=0.47 c=0 +rf589 (\78\:gnd! \81\:gnd!) resistor r=0.0387 c=0 +rf590 (\81\:gnd! \82\:gnd!) resistor r=0.1067 c=0 +rf591 (\78\:gnd! \83\:gnd!) resistor r=0.4452 c=0 +rf592 (\81\:gnd! \84\:gnd!) resistor r=0.3793 c=0 +rf593 (\82\:gnd! \85\:gnd!) resistor r=0.0706 c=0 +rf594 (\85\:gnd! \86\:gnd!) resistor r=0.3122 c=0 +rf595 (\82\:gnd! \87\:gnd!) resistor r=0.4967 c=0 +rf596 (\85\:gnd! \88\:gnd!) resistor r=0.06608 c=0 +rf597 (\88\:gnd! \89\:gnd!) resistor r=0.04684 c=0 +rf598 (\89\:gnd! \90\:gnd!) resistor r=0.306 c=0 +rf599 (\89\:gnd! \91\:gnd!) resistor r=0.09403 c=0 +rf600 (\91\:gnd! \92\:gnd!) resistor r=0.3596 c=0 +rf601 (\91\:gnd! \93\:gnd!) resistor r=0.3451 c=0 +rf602 (\93\:gnd! \94\:gnd!) resistor r=4.7066 c=0 +rf603 (\94\:gnd! \95\:gnd!) resistor r=0.476 c=0 +rf604 (\91\:gnd! \96\:gnd!) resistor r=0.442 c=0 +rf605 (\93\:gnd! \97\:gnd!) resistor r=4.2632 c=0 +rf606 (\97\:gnd! \98\:gnd!) resistor r=4.2744 c=0 +rf607 (\98\:gnd! 0) resistor r=0.4005 c=0 +rf608 (\94\:gnd! \99\:gnd!) resistor r=0.1317 c=0 +rf609 (\99\:gnd! \100\:gnd!) resistor r=0.1396 c=0 +rf610 (\100\:gnd! \101\:gnd!) resistor r=0.52 c=0 +rf611 (\97\:gnd! \102\:gnd!) resistor r=0.3328 c=0 +rf612 (\102\:gnd! \103\:gnd!) resistor r=0.05392 c=0 +rf613 (\103\:gnd! \104\:gnd!) resistor r=0.3949 c=0 +rf614 (\98\:gnd! \105\:gnd!) resistor r=0.359 c=0 +rf615 (\105\:gnd! \106\:gnd!) resistor r=0.09621 c=0 +rf616 (\106\:gnd! \107\:gnd!) resistor r=0.2996 c=0 +rf617 (\100\:gnd! \108\:gnd!) resistor r=0.1085 c=0 +rf618 (\108\:gnd! \109\:gnd!) resistor r=0.3877 c=0 +rf619 (\103\:gnd! \110\:gnd!) resistor r=0.3965 c=0 +rf620 (\103\:gnd! \111\:gnd!) resistor r=0.09221 c=0 +rf621 (\111\:gnd! \112\:gnd!) resistor r=0.3649 c=0 +rf622 (\106\:gnd! \113\:gnd!) resistor r=0.07337 c=0 +rf623 (\113\:gnd! \114\:gnd!) resistor r=0.3083 c=0 +rf624 (\108\:gnd! \115\:gnd!) resistor r=0.03889 c=0 +rf625 (\115\:gnd! \116\:gnd!) resistor r=0.4877 c=0 +rf626 (\111\:gnd! \117\:gnd!) resistor r=0.3954 c=0 +rf627 (\111\:gnd! \118\:gnd!) resistor r=0.09227 c=0 +rf628 (\118\:gnd! \119\:gnd!) resistor r=0.3971 c=0 +rf629 (\113\:gnd! \120\:gnd!) resistor r=0.03456 c=0 +rf630 (\120\:gnd! \121\:gnd!) resistor r=0.1383 c=0 +rf631 (\121\:gnd! \122\:gnd!) resistor r=0.4467 c=0 +rf632 (\115\:gnd! \123\:gnd!) resistor r=0.1292 c=0 +rf633 (\123\:gnd! \124\:gnd!) resistor r=0.3918 c=0 +rf634 (\118\:gnd! \125\:gnd!) resistor r=0.473 c=0 +rf635 (\118\:gnd! \126\:gnd!) resistor r=0.06553 c=0 +rf636 (\126\:gnd! \127\:gnd!) resistor r=0.046 c=0 +rf637 (\127\:gnd! \128\:gnd!) resistor r=0.3896 c=0 +rf638 (\121\:gnd! \129\:gnd!) resistor r=0.04511 c=0 +rf639 (\129\:gnd! \130\:gnd!) resistor r=0.358 c=0 +rf640 (\123\:gnd! \131\:gnd!) resistor r=0.08824 c=0 +rf641 (\131\:gnd! \132\:gnd!) resistor r=0.1508 c=0 +rf642 (\132\:gnd! \133\:gnd!) resistor r=0.04236 c=0 +rf643 (\133\:gnd! \134\:gnd!) resistor r=0.3918 c=0 +rf644 (\127\:gnd! \135\:gnd!) resistor r=0.1014 c=0 +rf645 (\135\:gnd! \136\:gnd!) resistor r=0.3965 c=0 +rf646 (\129\:gnd! \137\:gnd!) resistor r=0.09948 c=0 +rf647 (\137\:gnd! \138\:gnd!) resistor r=0.2186 c=0 +rf648 (\138\:gnd! \139\:gnd!) resistor r=0.3811 c=0 +rf649 (\133\:gnd! \140\:gnd!) resistor r=0.1372 c=0 +rf650 (\135\:gnd! \141\:gnd!) resistor r=0.15 c=0 +rf651 (\141\:gnd! \142\:gnd!) resistor r=0.3196 c=0 +rf652 (\138\:gnd! \143\:gnd!) resistor r=0.07421 c=0 +rf653 (\143\:gnd! \144\:gnd!) resistor r=0.3105 c=0 +rf654 (\140\:gnd! \145\:gnd!) resistor r=0.0255 c=0 +rf655 (\145\:gnd! \146\:gnd!) resistor r=0.3873 c=0 +rf656 (\141\:gnd! \147\:gnd!) resistor r=0.06745 c=0 +rf657 (\147\:gnd! \148\:gnd!) resistor r=0.3617 c=0 +rf658 (\143\:gnd! \149\:gnd!) resistor r=0.07653 c=0 +rf659 (\149\:gnd! \150\:gnd!) resistor r=0.1347 c=0 +rf660 (\150\:gnd! \151\:gnd!) resistor r=0.3038 c=0 +rf661 (\145\:gnd! \152\:gnd!) resistor r=0.1216 c=0 +rf662 (\152\:gnd! \153\:gnd!) resistor r=0.148 c=0 +rf663 (\147\:gnd! \154\:gnd!) resistor r=0.4707 c=0 +rf664 (\147\:gnd! \155\:gnd!) resistor r=0.09352 c=0 +rf665 (\155\:gnd! \156\:gnd!) resistor r=0.3896 c=0 +rf666 (\150\:gnd! \157\:gnd!) resistor r=0.0463 c=0 +rf667 (\157\:gnd! \158\:gnd!) resistor r=0.02722 c=0 +rf668 (\158\:gnd! \159\:gnd!) resistor r=0.3 c=0 +rf669 (\153\:gnd! \160\:gnd!) resistor r=0.02188 c=0 +rf670 (\160\:gnd! \161\:gnd!) resistor r=0.3873 c=0 +rf671 (\155\:gnd! \162\:gnd!) resistor r=0.05615 c=0 +rf672 (\162\:gnd! \163\:gnd!) resistor r=0.3941 c=0 +rf673 (\158\:gnd! \164\:gnd!) resistor r=0.1173 c=0 +rf674 (\164\:gnd! \165\:gnd!) resistor r=0.4044 c=0 +rf675 (\160\:gnd! \166\:gnd!) resistor r=0.1038 c=0 +rf676 (\166\:gnd! \167\:gnd!) resistor r=0.3833 c=0 +rf677 (\162\:gnd! \168\:gnd!) resistor r=0.1077 c=0 +rf678 (\168\:gnd! \169\:gnd!) resistor r=0.3874 c=0 +rf679 (\164\:gnd! \170\:gnd!) resistor r=0.1447 c=0 +rf680 (\170\:gnd! \171\:gnd!) resistor r=0.05704 c=0 +rf681 (\171\:gnd! \172\:gnd!) resistor r=0.3215 c=0 +rf682 (\166\:gnd! \173\:gnd!) resistor r=0.02269 c=0 +rf683 (\168\:gnd! \174\:gnd!) resistor r=0.0715 c=0 +rf684 (\174\:gnd! \175\:gnd!) resistor r=0.05637 c=0 +rf685 (\175\:gnd! \176\:gnd!) resistor r=0.3019 c=0 +rf686 (\171\:gnd! \177\:gnd!) resistor r=0.08887 c=0 +rf687 (\177\:gnd! \178\:gnd!) resistor r=0.06637 c=0 +rf688 (\178\:gnd! \179\:gnd!) resistor r=0.3215 c=0 +rf689 (\173\:gnd! \180\:gnd!) resistor r=0.02879 c=0 +rf690 (\180\:gnd! \181\:gnd!) resistor r=0.3873 c=0 +rf691 (\175\:gnd! \182\:gnd!) resistor r=0.09058 c=0 +rf692 (\182\:gnd! \183\:gnd!) resistor r=0.3708 c=0 +rf693 (\178\:gnd! \184\:gnd!) resistor r=0.06251 c=0 +rf694 (\184\:gnd! \185\:gnd!) resistor r=0.3843 c=0 +rf695 (\180\:gnd! \186\:gnd!) resistor r=0.1034 c=0 +rf696 (\182\:gnd! \187\:gnd!) resistor r=0.07183 c=0 +rf697 (\187\:gnd! \188\:gnd!) resistor r=0.3874 c=0 +rf698 (\184\:gnd! \189\:gnd!) resistor r=0.1469 c=0 +rf699 (\189\:gnd! \190\:gnd!) resistor r=0.4044 c=0 +rf700 (\186\:gnd! \191\:gnd!) resistor r=0.4477 c=0 +rf701 (\186\:gnd! \192\:gnd!) resistor r=0.1503 c=0 +rf702 (\187\:gnd! \193\:gnd!) resistor r=0.04481 c=0 +rf703 (\193\:gnd! \194\:gnd!) resistor r=0.3163 c=0 +rf704 (\189\:gnd! \195\:gnd!) resistor r=0.2039 c=0 +rf705 (\195\:gnd! \196\:gnd!) resistor r=0.4022 c=0 +rf706 (\192\:gnd! \197\:gnd!) resistor r=0.1433 c=0 +rf707 (\197\:gnd! \198\:gnd!) resistor r=0.3873 c=0 +rf708 (\193\:gnd! \199\:gnd!) resistor r=0.02922 c=0 +rf709 (\199\:gnd! \200\:gnd!) resistor r=0.02857 c=0 +rf710 (\200\:gnd! \201\:gnd!) resistor r=0.3834 c=0 +rf711 (\195\:gnd! \202\:gnd!) resistor r=0.1456 c=0 +rf712 (\202\:gnd! \203\:gnd!) resistor r=0.3767 c=0 +rf713 (\197\:gnd! \204\:gnd!) resistor r=0.06184 c=0 +rf714 (\204\:gnd! \205\:gnd!) resistor r=0.109 c=0 +rf715 (\205\:gnd! \206\:gnd!) resistor r=0.3873 c=0 +rf716 (\200\:gnd! \207\:gnd!) resistor r=0.05138 c=0 +rf717 (\207\:gnd! \208\:gnd!) resistor r=0.3874 c=0 +rf718 (\202\:gnd! \209\:gnd!) resistor r=0.06647 c=0 +rf719 (\209\:gnd! \210\:gnd!) resistor r=0.3213 c=0 +rf720 (\205\:gnd! \211\:gnd!) resistor r=0.03833 c=0 +rf721 (\211\:gnd! \212\:gnd!) resistor r=0.148 c=0 +rf722 (\207\:gnd! \213\:gnd!) resistor r=0.06821 c=0 +rf723 (\213\:gnd! \214\:gnd!) resistor r=0.03653 c=0 +rf724 (\214\:gnd! \215\:gnd!) resistor r=0.3929 c=0 +rf725 (\209\:gnd! \216\:gnd!) resistor r=0.07812 c=0 +rf726 (\216\:gnd! \217\:gnd!) resistor r=0.07812 c=0 +rf727 (\217\:gnd! \218\:gnd!) resistor r=0.3213 c=0 +rf728 (\212\:gnd! \219\:gnd!) resistor r=0.09425 c=0 +rf729 (\219\:gnd! \220\:gnd!) resistor r=0.3873 c=0 +rf730 (\214\:gnd! \221\:gnd!) resistor r=0.4741 c=0 +rf731 (\214\:gnd! \222\:gnd!) resistor r=0.09179 c=0 +rf732 (\222\:gnd! \223\:gnd!) resistor r=0.0567 c=0 +rf733 (\223\:gnd! \224\:gnd!) resistor r=0.3197 c=0 +rf734 (\217\:gnd! \225\:gnd!) resistor r=0.06873 c=0 +rf735 (\225\:gnd! \226\:gnd!) resistor r=0.1307 c=0 +rf736 (\226\:gnd! \227\:gnd!) resistor r=0.4022 c=0 +rf737 (\219\:gnd! \228\:gnd!) resistor r=0.0551 c=0 +rf738 (\223\:gnd! \229\:gnd!) resistor r=0.04991 c=0 +rf739 (\229\:gnd! \230\:gnd!) resistor r=0.3197 c=0 +rf740 (\226\:gnd! \231\:gnd!) resistor r=0.1662 c=0 +rf741 (\231\:gnd! \232\:gnd!) resistor r=0.3027 c=0 +rf742 (\228\:gnd! \233\:gnd!) resistor r=0.06004 c=0 +rf743 (\233\:gnd! \234\:gnd!) resistor r=0.3873 c=0 +rf744 (\229\:gnd! \235\:gnd!) resistor r=0.04157 c=0 +rf745 (\235\:gnd! \236\:gnd!) resistor r=0.04519 c=0 +rf746 (\236\:gnd! \237\:gnd!) resistor r=0.3874 c=0 +rf747 (\231\:gnd! \238\:gnd!) resistor r=0.05028 c=0 +rf748 (\238\:gnd! \239\:gnd!) resistor r=0.02337 c=0 +rf749 (\239\:gnd! \240\:gnd!) resistor r=0.3093 c=0 +rf750 (\233\:gnd! \241\:gnd!) resistor r=0.07188 c=0 +rf751 (\236\:gnd! \242\:gnd!) resistor r=0.06896 c=0 +rf752 (\242\:gnd! \243\:gnd!) resistor r=0.3173 c=0 +rf753 (\239\:gnd! \244\:gnd!) resistor r=0.1061 c=0 +rf754 (\244\:gnd! \245\:gnd!) resistor r=0.148 c=0 +rf755 (\245\:gnd! \246\:gnd!) resistor r=0.3515 c=0 +rf756 (\241\:gnd! \247\:gnd!) resistor r=0.442 c=0 +rf757 (\241\:gnd! \248\:gnd!) resistor r=0.08461 c=0 +rf758 (\248\:gnd! \249\:gnd!) resistor r=0.3873 c=0 +rf759 (\242\:gnd! \250\:gnd!) resistor r=0.04495 c=0 +rf760 (\250\:gnd! \251\:gnd!) resistor r=0.3896 c=0 +rf761 (\245\:gnd! \252\:gnd!) resistor r=0.0544 c=0 +rf762 (\252\:gnd! \253\:gnd!) resistor r=0.3085 c=0 +rf763 (\248\:gnd! \254\:gnd!) resistor r=0.06497 c=0 +rf764 (\254\:gnd! \255\:gnd!) resistor r=0.1977 c=0 +rf765 (\250\:gnd! \256\:gnd!) resistor r=0.04402 c=0 +rf766 (\256\:gnd! \257\:gnd!) resistor r=0.1485 c=0 +rf767 (\257\:gnd! \258\:gnd!) resistor r=0.07299 c=0 +rf768 (\258\:gnd! \259\:gnd!) resistor r=0.3788 c=0 +rf769 (\252\:gnd! \260\:gnd!) resistor r=0.09236 c=0 +rf770 (\260\:gnd! \261\:gnd!) resistor r=0.1489 c=0 +rf771 (\261\:gnd! \262\:gnd!) resistor r=0.4122 c=0 +rf772 (\255\:gnd! \263\:gnd!) resistor r=0.02879 c=0 +rf773 (\263\:gnd! \264\:gnd!) resistor r=0.3873 c=0 +rf774 (\258\:gnd! \265\:gnd!) resistor r=0.4741 c=0 +rf775 (\258\:gnd! \266\:gnd!) resistor r=0.06936 c=0 +rf776 (\266\:gnd! \267\:gnd!) resistor r=0.06287 c=0 +rf777 (\267\:gnd! \268\:gnd!) resistor r=0.3949 c=0 +rf778 (\261\:gnd! \269\:gnd!) resistor r=0.03693 c=0 +rf779 (\269\:gnd! \270\:gnd!) resistor r=0.3611 c=0 +rf780 (\263\:gnd! \271\:gnd!) resistor r=0.1186 c=0 +rf781 (\271\:gnd! \272\:gnd!) resistor r=0.1485 c=0 +rf782 (\272\:gnd! \273\:gnd!) resistor r=0.03889 c=0 +rf783 (\273\:gnd! \274\:gnd!) resistor r=0.3844 c=0 +rf784 (\267\:gnd! \275\:gnd!) resistor r=0.4764 c=0 +rf785 (\267\:gnd! \276\:gnd!) resistor r=0.04763 c=0 +rf786 (\276\:gnd! \277\:gnd!) resistor r=0.3962 c=0 +rf787 (\269\:gnd! \278\:gnd!) resistor r=0.09408 c=0 +rf788 (\278\:gnd! \279\:gnd!) resistor r=0.1513 c=0 +rf789 (\279\:gnd! \280\:gnd!) resistor r=0.3627 c=0 +rf790 (\273\:gnd! \281\:gnd!) resistor r=0.1108 c=0 +rf791 (\281\:gnd! \282\:gnd!) resistor r=0.5167 c=0 +rf792 (\276\:gnd! \283\:gnd!) resistor r=0.4722 c=0 +rf793 (\276\:gnd! \284\:gnd!) resistor r=0.03195 c=0 +rf794 (\284\:gnd! \285\:gnd!) resistor r=0.06382 c=0 +rf795 (\285\:gnd! \286\:gnd!) resistor r=0.3896 c=0 +rf796 (\279\:gnd! \287\:gnd!) resistor r=0.3647 c=0 +rf797 (\281\:gnd! \288\:gnd!) resistor r=0.1333 c=0 +rf798 (\288\:gnd! \289\:gnd!) resistor r=0.1508 c=0 +rf799 (\289\:gnd! \290\:gnd!) resistor r=0.5167 c=0 +rf800 (\285\:gnd! \291\:gnd!) resistor r=0.06844 c=0 +rf801 (\291\:gnd! \292\:gnd!) resistor r=0.4133 c=0 +rf802 (\289\:gnd! \293\:gnd!) resistor r=0.521 c=0 +rf803 (\291\:gnd! \294\:gnd!) resistor r=0.1508 c=0 +rf804 (\294\:gnd! \295\:gnd!) resistor r=0.06482 c=0 +rf805 (\295\:gnd! \296\:gnd!) resistor r=0.3936 c=0 +rf806 (\295\:gnd! \297\:gnd!) resistor r=0.4764 c=0 +rf807 (\295\:gnd! \298\:gnd!) resistor r=0.1289 c=0 +rf808 (\298\:gnd! \299\:gnd!) resistor r=0.364 c=0 +rf809 (\298\:gnd! \300\:gnd!) resistor r=0.4713 c=0 +rf810 (\298\:gnd! \301\:gnd!) resistor r=0.09652 c=0 +rf811 (\301\:gnd! \302\:gnd!) resistor r=0.302 c=0 +rf812 (\301\:gnd! \303\:gnd!) resistor r=0.04996 c=0 +rf813 (\303\:gnd! \304\:gnd!) resistor r=0.5113 c=0 +rf814 (\303\:gnd! \305\:gnd!) resistor r=0.1477 c=0 +rf815 (\305\:gnd! \306\:gnd!) resistor r=0.0937 c=0 +rf816 (\306\:gnd! \307\:gnd!) resistor r=0.3575 c=0 +rf817 (\306\:gnd! \308\:gnd!) resistor r=0.0552 c=0 +rf818 (\308\:gnd! \309\:gnd!) resistor r=0.4108 c=0 +rf819 (\308\:gnd! \310\:gnd!) resistor r=0.4821 c=0 +rf820 (\308\:gnd! \311\:gnd!) resistor r=0.09077 c=0 +rf821 (\311\:gnd! \312\:gnd!) resistor r=0.3857 c=0 +rf822 (\311\:gnd! \313\:gnd!) resistor r=0.07145 c=0 +rf823 (\313\:gnd! \314\:gnd!) resistor r=0.05835 c=0 +rf824 (\314\:gnd! \315\:gnd!) resistor r=0.3063 c=0 +rf825 (\314\:gnd! \316\:gnd!) resistor r=0.09091 c=0 +rf826 (\316\:gnd! \317\:gnd!) resistor r=0.3306 c=0 +rf827 (\316\:gnd! \318\:gnd!) resistor r=0.3711 c=0 +rf828 (\316\:gnd! \319\:gnd!) resistor r=0.3343 c=0 +rf829 (Y1 \21\:Y1) resistor r=0.2212 c=0 +rf830 (\21\:Y1 \18\:Y1) resistor r=3.8017 c=0 +rf831 (\18\:Y1 \12\:Y1) resistor r=10.0519 c=0 +rf832 (\12\:Y1 \5\:Y1) resistor r=4.0448 c=0 +rf833 (vdd! \1\:vdd!) resistor r=1.9259 c=0 +rf834 (\1\:vdd! \2\:vdd!) resistor r=4.4079 c=0 +rf835 (\2\:vdd! \3\:vdd!) resistor r=4.3331 c=0 +rf836 (\3\:vdd! \4\:vdd!) resistor r=0.1142 c=0 +rf837 (\4\:vdd! \5\:vdd!) resistor r=0.07026 c=0 +rf838 (\5\:vdd! \6\:vdd!) resistor r=0.1185 c=0 +rf839 (\6\:vdd! \7\:vdd!) resistor r=0.1058 c=0 +rf840 (\7\:vdd! \8\:vdd!) resistor r=0.05382 c=0 +rf841 (\8\:vdd! \9\:vdd!) resistor r=0.05336 c=0 +rf842 (\9\:vdd! \10\:vdd!) resistor r=0.1554 c=0 +rf843 (\10\:vdd! \11\:vdd!) resistor r=0.1068 c=0 +rf844 (\11\:vdd! \12\:vdd!) resistor r=0.0441 c=0 +rf845 (\12\:vdd! \13\:vdd!) resistor r=0.02879 c=0 +rf846 (\13\:vdd! \14\:vdd!) resistor r=0.1886 c=0 +rf847 (\14\:vdd! \15\:vdd!) resistor r=0.07569 c=0 +rf848 (\15\:vdd! \16\:vdd!) resistor r=0.03265 c=0 +rf849 (\16\:vdd! \17\:vdd!) resistor r=0.07166 c=0 +rf850 (\17\:vdd! \18\:vdd!) resistor r=0.02575 c=0 +rf851 (\18\:vdd! \19\:vdd!) resistor r=0.02916 c=0 +rf852 (\19\:vdd! \20\:vdd!) resistor r=0.0265 c=0 +rf853 (\20\:vdd! \21\:vdd!) resistor r=0.1023 c=0 +rf854 (\21\:vdd! \22\:vdd!) resistor r=0.05449 c=0 +rf855 (\22\:vdd! \23\:vdd!) resistor r=0.1069 c=0 +rf856 (\23\:vdd! \24\:vdd!) resistor r=0.05069 c=0 +rf857 (\24\:vdd! \25\:vdd!) resistor r=0.05136 c=0 +rf858 (\25\:vdd! \26\:vdd!) resistor r=0.1725 c=0 +rf859 (\26\:vdd! \27\:vdd!) resistor r=0.05118 c=0 +rf860 (\27\:vdd! \28\:vdd!) resistor r=0.0506 c=0 +rf861 (\28\:vdd! \29\:vdd!) resistor r=0.1064 c=0 +rf862 (\29\:vdd! \30\:vdd!) resistor r=0.05445 c=0 +rf863 (\30\:vdd! \31\:vdd!) resistor r=0.1029 c=0 +rf864 (\31\:vdd! \32\:vdd!) resistor r=0.03453 c=0 +rf865 (\32\:vdd! \33\:vdd!) resistor r=0.03083 c=0 +rf866 (\33\:vdd! \34\:vdd!) resistor r=0.0257 c=0 +rf867 (\34\:vdd! \35\:vdd!) resistor r=0.07181 c=0 +rf868 (\35\:vdd! \36\:vdd!) resistor r=0.03262 c=0 +rf869 (\36\:vdd! \37\:vdd!) resistor r=0.07526 c=0 +rf870 (\37\:vdd! \38\:vdd!) resistor r=0.1245 c=0 +rf871 (\38\:vdd! \39\:vdd!) resistor r=0.06644 c=0 +rf872 (\39\:vdd! \40\:vdd!) resistor r=0.02911 c=0 +rf873 (\40\:vdd! \41\:vdd!) resistor r=0.08239 c=0 +rf874 (\41\:vdd! \42\:vdd!) resistor r=0.07195 c=0 +rf875 (\42\:vdd! \43\:vdd!) resistor r=0.05037 c=0 +rf876 (\43\:vdd! \44\:vdd!) resistor r=0.04978 c=0 +rf877 (\44\:vdd! \45\:vdd!) resistor r=0.1047 c=0 +rf878 (\45\:vdd! \46\:vdd!) resistor r=0.05363 c=0 +rf879 (\46\:vdd! \47\:vdd!) resistor r=0.1009 c=0 +rf880 (\47\:vdd! \48\:vdd!) resistor r=0.02613 c=0 +rf881 (\48\:vdd! \49\:vdd!) resistor r=0.02876 c=0 +rf882 (\49\:vdd! \50\:vdd!) resistor r=0.02535 c=0 +rf883 (\50\:vdd! \51\:vdd!) resistor r=0.07067 c=0 +rf884 (\51\:vdd! \52\:vdd!) resistor r=0.03216 c=0 +rf885 (\52\:vdd! \53\:vdd!) resistor r=0.07448 c=0 +rf886 (\53\:vdd! \54\:vdd!) resistor r=0.1082 c=0 +rf887 (\54\:vdd! \55\:vdd!) resistor r=0.07267 c=0 +rf888 (\55\:vdd! \56\:vdd!) resistor r=0.0317 c=0 +rf889 (\56\:vdd! \57\:vdd!) resistor r=0.06006 c=0 +rf890 (\57\:vdd! \58\:vdd!) resistor r=0.429 c=0 +rf891 (\1\:vdd! \59\:vdd!) resistor r=0.2893 c=0 +rf892 (\59\:vdd! \60\:vdd!) resistor r=0.3835 c=0 +rf893 (\2\:vdd! \61\:vdd!) resistor r=0.08985 c=0 +rf894 (\61\:vdd! \62\:vdd!) resistor r=0.5222 c=0 +rf895 (\3\:vdd! \63\:vdd!) resistor r=0.7491 c=0 +rf896 (\3\:vdd! \64\:vdd!) resistor r=0.7418 c=0 +rf897 (\4\:vdd! \65\:vdd!) resistor r=0.5159 c=0 +rf898 (\4\:vdd! \66\:vdd!) resistor r=0.5159 c=0 +rf899 (\5\:vdd! \67\:vdd!) resistor r=0.4015 c=0 +rf900 (\6\:vdd! \68\:vdd!) resistor r=0.3716 c=0 +rf901 (\7\:vdd! \69\:vdd!) resistor r=0.4979 c=0 +rf902 (\7\:vdd! \70\:vdd!) resistor r=0.468 c=0 +rf903 (\8\:vdd! \71\:vdd!) resistor r=0.3726 c=0 +rf904 (\9\:vdd! \72\:vdd!) resistor r=0.3984 c=0 +rf905 (\10\:vdd! \73\:vdd!) resistor r=0.4004 c=0 +rf906 (\11\:vdd! \74\:vdd!) resistor r=0.3994 c=0 +rf907 (\12\:vdd! \75\:vdd!) resistor r=0.3996 c=0 +rf908 (\13\:vdd! \76\:vdd!) resistor r=0.3997 c=0 +rf909 (\14\:vdd! \77\:vdd!) resistor r=0.3775 c=0 +rf910 (\15\:vdd! \78\:vdd!) resistor r=0.4015 c=0 +rf911 (\16\:vdd! \79\:vdd!) resistor r=0.522 c=0 +rf912 (\17\:vdd! \80\:vdd!) resistor r=0.3972 c=0 +rf913 (\18\:vdd! \81\:vdd!) resistor r=0.3878 c=0 +rf914 (\19\:vdd! \82\:vdd!) resistor r=0.4068 c=0 +rf915 (\20\:vdd! \83\:vdd!) resistor r=0.3805 c=0 +rf916 (\21\:vdd! \84\:vdd!) resistor r=0.521 c=0 +rf917 (\21\:vdd! \85\:vdd!) resistor r=0.5021 c=0 +rf918 (\22\:vdd! \86\:vdd!) resistor r=0.3815 c=0 +rf919 (\23\:vdd! \87\:vdd!) resistor r=0.3815 c=0 +rf920 (\24\:vdd! \88\:vdd!) resistor r=0.3775 c=0 +rf921 (\25\:vdd! \89\:vdd!) resistor r=0.4015 c=0 +rf922 (\26\:vdd! \90\:vdd!) resistor r=0.3994 c=0 +rf923 (\27\:vdd! \91\:vdd!) resistor r=0.3774 c=0 +rf924 (\28\:vdd! \92\:vdd!) resistor r=0.3815 c=0 +rf925 (\29\:vdd! \93\:vdd!) resistor r=0.3815 c=0 +rf926 (\30\:vdd! \94\:vdd!) resistor r=0.521 c=0 +rf927 (\30\:vdd! \95\:vdd!) resistor r=0.5021 c=0 +rf928 (\31\:vdd! \96\:vdd!) resistor r=0.3805 c=0 +rf929 (\32\:vdd! \97\:vdd!) resistor r=0.3968 c=0 +rf930 (\33\:vdd! \98\:vdd!) resistor r=0.3878 c=0 +rf931 (\34\:vdd! \99\:vdd!) resistor r=0.3973 c=0 +rf932 (\35\:vdd! \100\:vdd!) resistor r=0.5236 c=0 +rf933 (\36\:vdd! \101\:vdd!) resistor r=0.3994 c=0 +rf934 (\37\:vdd! \102\:vdd!) resistor r=0.3733 c=0 +rf935 (\38\:vdd! \103\:vdd!) resistor r=0.4019 c=0 +rf936 (\39\:vdd! \104\:vdd!) resistor r=0.4246 c=0 +rf937 (\40\:vdd! \105\:vdd!) resistor r=0.4226 c=0 +rf938 (\41\:vdd! \106\:vdd!) resistor r=0.4019 c=0 +rf939 (\42\:vdd! \107\:vdd!) resistor r=0.3955 c=0 +rf940 (\43\:vdd! \108\:vdd!) resistor r=0.3769 c=0 +rf941 (\44\:vdd! \109\:vdd!) resistor r=0.3809 c=0 +rf942 (\45\:vdd! \110\:vdd!) resistor r=0.3809 c=0 +rf943 (\46\:vdd! \111\:vdd!) resistor r=0.5188 c=0 +rf944 (\46\:vdd! \112\:vdd!) resistor r=0.5043 c=0 +rf945 (\47\:vdd! \113\:vdd!) resistor r=0.3809 c=0 +rf946 (\48\:vdd! \114\:vdd!) resistor r=0.4028 c=0 +rf947 (\49\:vdd! \115\:vdd!) resistor r=0.3882 c=0 +rf948 (\50\:vdd! \116\:vdd!) resistor r=0.3934 c=0 +rf949 (\51\:vdd! \117\:vdd!) resistor r=0.5224 c=0 +rf950 (\52\:vdd! \118\:vdd!) resistor r=0.3975 c=0 +rf951 (\53\:vdd! \119\:vdd!) resistor r=0.3769 c=0 +rf952 (\54\:vdd! \120\:vdd!) resistor r=0.3965 c=0 +rf953 (\55\:vdd! \121\:vdd!) resistor r=0.3965 c=0 +rf954 (\56\:vdd! \122\:vdd!) resistor r=0.3975 c=0 +rf955 (\59\:vdd! \123\:vdd!) resistor r=0.09153 c=0 +rf956 (\123\:vdd! \124\:vdd!) resistor r=0.4738 c=0 +rf957 (\59\:vdd! \125\:vdd!) resistor r=0.4236 c=0 +rf958 (\61\:vdd! \126\:vdd!) resistor r=0.08918 c=0 +rf959 (\126\:vdd! \127\:vdd!) resistor r=0.02324 c=0 +rf960 (\127\:vdd! \128\:vdd!) resistor r=0.5125 c=0 +rf961 (\61\:vdd! \129\:vdd!) resistor r=0.5256 c=0 +rf962 (\123\:vdd! \130\:vdd!) resistor r=0.08497 c=0 +rf963 (\130\:vdd! \131\:vdd!) resistor r=0.4974 c=0 +rf964 (\123\:vdd! \132\:vdd!) resistor r=0.4853 c=0 +rf965 (\127\:vdd! \133\:vdd!) resistor r=0.08278 c=0 +rf966 (\133\:vdd! \134\:vdd!) resistor r=0.1069 c=0 +rf967 (\134\:vdd! \135\:vdd!) resistor r=0.1034 c=0 +rf968 (\135\:vdd! \136\:vdd!) resistor r=0.4972 c=0 +rf969 (\127\:vdd! \137\:vdd!) resistor r=0.5158 c=0 +rf970 (\130\:vdd! \138\:vdd!) resistor r=0.0271 c=0 +rf971 (\138\:vdd! \139\:vdd!) resistor r=0.04574 c=0 +rf972 (\139\:vdd! \140\:vdd!) resistor r=0.3976 c=0 +rf973 (\130\:vdd! \141\:vdd!) resistor r=0.5029 c=0 +rf974 (\133\:vdd! \142\:vdd!) resistor r=0.4829 c=0 +rf975 (\134\:vdd! \143\:vdd!) resistor r=0.4789 c=0 +rf976 (\135\:vdd! \144\:vdd!) resistor r=0.06491 c=0 +rf977 (\144\:vdd! \145\:vdd!) resistor r=0.04205 c=0 +rf978 (\145\:vdd! \146\:vdd!) resistor r=0.3944 c=0 +rf979 (\135\:vdd! \147\:vdd!) resistor r=0.4717 c=0 +rf980 (\139\:vdd! \148\:vdd!) resistor r=0.06326 c=0 +rf981 (\148\:vdd! \149\:vdd!) resistor r=0.04045 c=0 +rf982 (\149\:vdd! \150\:vdd!) resistor r=0.5014 c=0 +rf983 (\144\:vdd! \151\:vdd!) resistor r=0.4564 c=0 +rf984 (\145\:vdd! \152\:vdd!) resistor r=0.06014 c=0 +rf985 (\152\:vdd! \153\:vdd!) resistor r=0.0715 c=0 +rf986 (\153\:vdd! \154\:vdd!) resistor r=0.03861 c=0 +rf987 (\154\:vdd! \155\:vdd!) resistor r=0.06161 c=0 +rf988 (\155\:vdd! \156\:vdd!) resistor r=0.02915 c=0 +rf989 (\156\:vdd! \157\:vdd!) resistor r=0.4154 c=0 +rf990 (\148\:vdd! \158\:vdd!) resistor r=0.4621 c=0 +rf991 (\149\:vdd! \159\:vdd!) resistor r=0.1028 c=0 +rf992 (\159\:vdd! \160\:vdd!) resistor r=0.06303 c=0 +rf993 (\160\:vdd! \161\:vdd!) resistor r=0.05368 c=0 +rf994 (\161\:vdd! \162\:vdd!) resistor r=0.05529 c=0 +rf995 (\162\:vdd! \163\:vdd!) resistor r=0.52 c=0 +rf996 (\149\:vdd! \164\:vdd!) resistor r=0.467 c=0 +rf997 (\153\:vdd! \165\:vdd!) resistor r=0.3985 c=0 +rf998 (\155\:vdd! \166\:vdd!) resistor r=0.4154 c=0 +rf999 (\156\:vdd! \167\:vdd!) resistor r=0.04924 c=0 +rf1000 (\167\:vdd! \168\:vdd!) resistor r=0.1599 c=0 +rf1001 (\168\:vdd! \169\:vdd!) resistor r=0.07474 c=0 +rf1002 (\169\:vdd! \170\:vdd!) resistor r=0.3985 c=0 +rf1003 (\159\:vdd! \171\:vdd!) resistor r=0.3658 c=0 +rf1004 (\161\:vdd! \172\:vdd!) resistor r=0.4003 c=0 +rf1005 (\162\:vdd! \173\:vdd!) resistor r=0.1145 c=0 +rf1006 (\173\:vdd! \174\:vdd!) resistor r=0.4992 c=0 +rf1007 (\162\:vdd! \175\:vdd!) resistor r=0.5011 c=0 +rf1008 (\167\:vdd! \176\:vdd!) resistor r=0.3985 c=0 +rf1009 (\168\:vdd! \177\:vdd!) resistor r=0.3768 c=0 +rf1010 (\169\:vdd! \178\:vdd!) resistor r=0.03227 c=0 +rf1011 (\178\:vdd! \179\:vdd!) resistor r=0.07091 c=0 +rf1012 (\179\:vdd! \180\:vdd!) resistor r=0.3944 c=0 +rf1013 (\173\:vdd! \181\:vdd!) resistor r=0.11 c=0 +rf1014 (\181\:vdd! \182\:vdd!) resistor r=0.01688 c=0 +rf1015 (\182\:vdd! \183\:vdd!) resistor r=0.02859 c=0 +rf1016 (\183\:vdd! \184\:vdd!) resistor r=0.4171 c=0 +rf1017 (\173\:vdd! \185\:vdd!) resistor r=0.5267 c=0 +rf1018 (\178\:vdd! \186\:vdd!) resistor r=0.5222 c=0 +rf1019 (\179\:vdd! \187\:vdd!) resistor r=0.02544 c=0 +rf1020 (\187\:vdd! \188\:vdd!) resistor r=0.02894 c=0 +rf1021 (\188\:vdd! \189\:vdd!) resistor r=0.4059 c=0 +rf1022 (\182\:vdd! \190\:vdd!) resistor r=0.4193 c=0 +rf1023 (\183\:vdd! \191\:vdd!) resistor r=0.04829 c=0 +rf1024 (\191\:vdd! \192\:vdd!) resistor r=0.1035 c=0 +rf1025 (\192\:vdd! \193\:vdd!) resistor r=0.05234 c=0 +rf1026 (\193\:vdd! \194\:vdd!) resistor r=0.07331 c=0 +rf1027 (\194\:vdd! \195\:vdd!) resistor r=0.4003 c=0 +rf1028 (\187\:vdd! \196\:vdd!) resistor r=0.3881 c=0 +rf1029 (\188\:vdd! \197\:vdd!) resistor r=0.02627 c=0 +rf1030 (\197\:vdd! \198\:vdd!) resistor r=0.02216 c=0 +rf1031 (\198\:vdd! \199\:vdd!) resistor r=0.07917 c=0 +rf1032 (\199\:vdd! \200\:vdd!) resistor r=0.5204 c=0 +rf1033 (\191\:vdd! \201\:vdd!) resistor r=0.4025 c=0 +rf1034 (\192\:vdd! \202\:vdd!) resistor r=0.4025 c=0 +rf1035 (\193\:vdd! \203\:vdd!) resistor r=0.3697 c=0 +rf1036 (\194\:vdd! \204\:vdd!) resistor r=0.03166 c=0 +rf1037 (\204\:vdd! \205\:vdd!) resistor r=0.06955 c=0 +rf1038 (\205\:vdd! \206\:vdd!) resistor r=0.3961 c=0 +rf1039 (\197\:vdd! \207\:vdd!) resistor r=0.3808 c=0 +rf1040 (\199\:vdd! \208\:vdd!) resistor r=0.01667 c=0 +rf1041 (\208\:vdd! \209\:vdd!) resistor r=0.03729 c=0 +rf1042 (\209\:vdd! \210\:vdd!) resistor r=0.1055 c=0 +rf1043 (\210\:vdd! \211\:vdd!) resistor r=0.05007 c=0 +rf1044 (\211\:vdd! \212\:vdd!) resistor r=0.05073 c=0 +rf1045 (\212\:vdd! \213\:vdd!) resistor r=0.3985 c=0 +rf1046 (\199\:vdd! \214\:vdd!) resistor r=0.5026 c=0 +rf1047 (\204\:vdd! \215\:vdd!) resistor r=0.511 c=0 +rf1048 (\205\:vdd! \216\:vdd!) resistor r=0.02496 c=0 +rf1049 (\216\:vdd! \217\:vdd!) resistor r=0.02839 c=0 +rf1050 (\217\:vdd! \218\:vdd!) resistor r=0.4076 c=0 +rf1051 (\209\:vdd! \219\:vdd!) resistor r=0.3808 c=0 +rf1052 (\210\:vdd! \220\:vdd!) resistor r=0.3808 c=0 +rf1053 (\211\:vdd! \221\:vdd!) resistor r=0.3768 c=0 +rf1054 (\212\:vdd! \222\:vdd!) resistor r=0.1583 c=0 +rf1055 (\222\:vdd! \223\:vdd!) resistor r=0.03795 c=0 +rf1056 (\223\:vdd! \224\:vdd!) resistor r=0.3997 c=0 +rf1057 (\216\:vdd! \225\:vdd!) resistor r=0.3809 c=0 +rf1058 (\217\:vdd! \226\:vdd!) resistor r=0.02577 c=0 +rf1059 (\226\:vdd! \227\:vdd!) resistor r=0.08626 c=0 +rf1060 (\227\:vdd! \228\:vdd!) resistor r=0.444 c=0 +rf1061 (\223\:vdd! \229\:vdd!) resistor r=0.05073 c=0 +rf1062 (\229\:vdd! \230\:vdd!) resistor r=0.05007 c=0 +rf1063 (\230\:vdd! \231\:vdd!) resistor r=0.1055 c=0 +rf1064 (\231\:vdd! \232\:vdd!) resistor r=0.05397 c=0 +rf1065 (\232\:vdd! \233\:vdd!) resistor r=0.5215 c=0 +rf1066 (\226\:vdd! \234\:vdd!) resistor r=0.3736 c=0 +rf1067 (\227\:vdd! \235\:vdd!) resistor r=0.06722 c=0 +rf1068 (\235\:vdd! \236\:vdd!) resistor r=0.1035 c=0 +rf1069 (\236\:vdd! \237\:vdd!) resistor r=0.04912 c=0 +rf1070 (\237\:vdd! \238\:vdd!) resistor r=0.04976 c=0 +rf1071 (\238\:vdd! \239\:vdd!) resistor r=0.4003 c=0 +rf1072 (\227\:vdd! \240\:vdd!) resistor r=0.4204 c=0 +rf1073 (\229\:vdd! \241\:vdd!) resistor r=0.3757 c=0 +rf1074 (\230\:vdd! \242\:vdd!) resistor r=0.3797 c=0 +rf1075 (\231\:vdd! \243\:vdd!) resistor r=0.3797 c=0 +rf1076 (\232\:vdd! \244\:vdd!) resistor r=0.0772 c=0 +rf1077 (\244\:vdd! \245\:vdd!) resistor r=0.02413 c=0 +rf1078 (\245\:vdd! \246\:vdd!) resistor r=0.02627 c=0 +rf1079 (\246\:vdd! \247\:vdd!) resistor r=0.407 c=0 +rf1080 (\232\:vdd! \248\:vdd!) resistor r=0.5015 c=0 +rf1081 (\235\:vdd! \249\:vdd!) resistor r=0.3736 c=0 +rf1082 (\236\:vdd! \250\:vdd!) resistor r=0.3736 c=0 +rf1083 (\237\:vdd! \251\:vdd!) resistor r=0.3697 c=0 +rf1084 (\238\:vdd! \252\:vdd!) resistor r=0.08109 c=0 +rf1085 (\252\:vdd! \253\:vdd!) resistor r=0.03142 c=0 +rf1086 (\253\:vdd! \254\:vdd!) resistor r=0.4025 c=0 +rf1087 (\245\:vdd! \255\:vdd!) resistor r=0.3797 c=0 +rf1088 (\246\:vdd! \256\:vdd!) resistor r=0.02894 c=0 +rf1089 (\256\:vdd! \257\:vdd!) resistor r=0.02544 c=0 +rf1090 (\257\:vdd! \258\:vdd!) resistor r=0.3954 c=0 +rf1091 (\253\:vdd! \259\:vdd!) resistor r=0.04976 c=0 +rf1092 (\259\:vdd! \260\:vdd!) resistor r=0.04912 c=0 +rf1093 (\260\:vdd! \261\:vdd!) resistor r=0.1035 c=0 +rf1094 (\261\:vdd! \262\:vdd!) resistor r=0.039 c=0 +rf1095 (\262\:vdd! \263\:vdd!) resistor r=0.4719 c=0 +rf1096 (\256\:vdd! \264\:vdd!) resistor r=0.387 c=0 +rf1097 (\257\:vdd! \265\:vdd!) resistor r=0.0506 c=0 +rf1098 (\265\:vdd! \266\:vdd!) resistor r=0.02031 c=0 +rf1099 (\266\:vdd! \267\:vdd!) resistor r=0.03227 c=0 +rf1100 (\267\:vdd! \268\:vdd!) resistor r=0.3997 c=0 +rf1101 (\259\:vdd! \269\:vdd!) resistor r=0.3675 c=0 +rf1102 (\260\:vdd! \270\:vdd!) resistor r=0.3714 c=0 +rf1103 (\261\:vdd! \271\:vdd!) resistor r=0.3714 c=0 +rf1104 (\262\:vdd! \272\:vdd!) resistor r=0.03309 c=0 +rf1105 (\272\:vdd! \273\:vdd!) resistor r=0.07884 c=0 +rf1106 (\273\:vdd! \274\:vdd!) resistor r=0.0398 c=0 +rf1107 (\274\:vdd! \275\:vdd!) resistor r=0.457 c=0 +rf1108 (\262\:vdd! \276\:vdd!) resistor r=0.469 c=0 +rf1109 (\266\:vdd! \277\:vdd!) resistor r=0.5205 c=0 +rf1110 (\267\:vdd! \278\:vdd!) resistor r=0.07474 c=0 +rf1111 (\278\:vdd! \279\:vdd!) resistor r=0.1343 c=0 +rf1112 (\279\:vdd! \280\:vdd!) resistor r=0.07645 c=0 +rf1113 (\280\:vdd! \281\:vdd!) resistor r=0.5178 c=0 +rf1114 (\273\:vdd! \282\:vdd!) resistor r=0.3714 c=0 +rf1115 (\274\:vdd! \283\:vdd!) resistor r=0.0406 c=0 +rf1116 (\283\:vdd! \284\:vdd!) resistor r=0.3983 c=0 +rf1117 (\274\:vdd! \285\:vdd!) resistor r=0.4394 c=0 +rf1118 (\278\:vdd! \286\:vdd!) resistor r=0.3757 c=0 +rf1119 (\279\:vdd! \287\:vdd!) resistor r=0.3997 c=0 +rf1120 (\280\:vdd! \288\:vdd!) resistor r=0.1145 c=0 +rf1121 (\288\:vdd! \289\:vdd!) resistor r=0.07545 c=0 +rf1122 (\289\:vdd! \290\:vdd!) resistor r=0.3985 c=0 +rf1123 (\280\:vdd! \291\:vdd!) resistor r=0.5178 c=0 +rf1124 (\283\:vdd! \292\:vdd!) resistor r=0.06955 c=0 +rf1125 (\292\:vdd! \293\:vdd!) resistor r=0.03166 c=0 +rf1126 (\293\:vdd! \294\:vdd!) resistor r=0.4025 c=0 +rf1127 (\288\:vdd! \295\:vdd!) resistor r=0.4804 c=0 +rf1128 (\289\:vdd! \296\:vdd!) resistor r=0.05073 c=0 +rf1129 (\296\:vdd! \297\:vdd!) resistor r=0.05007 c=0 +rf1130 (\297\:vdd! \298\:vdd!) resistor r=0.1055 c=0 +rf1131 (\298\:vdd! \299\:vdd!) resistor r=0.05397 c=0 +rf1132 (\299\:vdd! \300\:vdd!) resistor r=0.5204 c=0 +rf1133 (\292\:vdd! \301\:vdd!) resistor r=0.5076 c=0 +rf1134 (\293\:vdd! \302\:vdd!) resistor r=0.07331 c=0 +rf1135 (\302\:vdd! \303\:vdd!) resistor r=0.1136 c=0 +rf1136 (\303\:vdd! \304\:vdd!) resistor r=0.06973 c=0 +rf1137 (\304\:vdd! \305\:vdd!) resistor r=0.02618 c=0 +rf1138 (\305\:vdd! \306\:vdd!) resistor r=0.4025 c=0 +rf1139 (\296\:vdd! \307\:vdd!) resistor r=0.3768 c=0 +rf1140 (\297\:vdd! \308\:vdd!) resistor r=0.3808 c=0 +rf1141 (\298\:vdd! \309\:vdd!) resistor r=0.3808 c=0 +rf1142 (\299\:vdd! \310\:vdd!) resistor r=0.06371 c=0 +rf1143 (\310\:vdd! \311\:vdd!) resistor r=0.03762 c=0 +rf1144 (\311\:vdd! \312\:vdd!) resistor r=0.02627 c=0 +rf1145 (\312\:vdd! \313\:vdd!) resistor r=0.4059 c=0 +rf1146 (\299\:vdd! \314\:vdd!) resistor r=0.5026 c=0 +rf1147 (\302\:vdd! \315\:vdd!) resistor r=0.3675 c=0 +rf1148 (\303\:vdd! \316\:vdd!) resistor r=0.4014 c=0 +rf1149 (\304\:vdd! \317\:vdd!) resistor r=0.4044 c=0 +rf1150 (\305\:vdd! \318\:vdd!) resistor r=0.09561 c=0 +rf1151 (\318\:vdd! \319\:vdd!) resistor r=0.0604 c=0 +rf1152 (\319\:vdd! \320\:vdd!) resistor r=0.4159 c=0 +rf1153 (\311\:vdd! \321\:vdd!) resistor r=0.3808 c=0 +rf1154 (\312\:vdd! \322\:vdd!) resistor r=0.02894 c=0 +rf1155 (\322\:vdd! \323\:vdd!) resistor r=0.02544 c=0 +rf1156 (\323\:vdd! \324\:vdd!) resistor r=0.3944 c=0 +rf1157 (\318\:vdd! \325\:vdd!) resistor r=0.4861 c=0 +rf1158 (\319\:vdd! \326\:vdd!) resistor r=0.02853 c=0 +rf1159 (\326\:vdd! \327\:vdd!) resistor r=0.03782 c=0 +rf1160 (\327\:vdd! \328\:vdd!) resistor r=0.0281 c=0 +rf1161 (\328\:vdd! \329\:vdd!) resistor r=0.02813 c=0 +rf1162 (\329\:vdd! \330\:vdd!) resistor r=0.4038 c=0 +rf1163 (\322\:vdd! \331\:vdd!) resistor r=0.3881 c=0 +rf1164 (\323\:vdd! \332\:vdd!) resistor r=0.05784 c=0 +rf1165 (\332\:vdd! \333\:vdd!) resistor r=0.04585 c=0 +rf1166 (\333\:vdd! \334\:vdd!) resistor r=0.3985 c=0 +rf1167 (\326\:vdd! \335\:vdd!) resistor r=0.4148 c=0 +rf1168 (\328\:vdd! \336\:vdd!) resistor r=0.4027 c=0 +rf1169 (\329\:vdd! \337\:vdd!) resistor r=0.06649 c=0 +rf1170 (\337\:vdd! \338\:vdd!) resistor r=0.1013 c=0 +rf1171 (\338\:vdd! \339\:vdd!) resistor r=0.1159 c=0 +rf1172 (\339\:vdd! \340\:vdd!) resistor r=0.5024 c=0 +rf1173 (\332\:vdd! \341\:vdd!) resistor r=0.617 c=0 +rf1174 (\333\:vdd! \342\:vdd!) resistor r=0.07474 c=0 +rf1175 (\342\:vdd! \343\:vdd!) resistor r=0.1076 c=0 +rf1176 (\343\:vdd! \344\:vdd!) resistor r=0.07294 c=0 +rf1177 (\344\:vdd! \345\:vdd!) resistor r=0.03281 c=0 +rf1178 (\345\:vdd! \346\:vdd!) resistor r=0.3985 c=0 +rf1179 (\337\:vdd! \347\:vdd!) resistor r=0.5065 c=0 +rf1180 (\338\:vdd! \348\:vdd!) resistor r=0.4589 c=0 +rf1181 (\339\:vdd! \349\:vdd!) resistor r=0.04944 c=0 +rf1182 (\349\:vdd! \350\:vdd!) resistor r=0.04887 c=0 +rf1183 (\350\:vdd! \351\:vdd!) resistor r=0.4238 c=0 +rf1184 (\339\:vdd! \352\:vdd!) resistor r=0.4635 c=0 +rf1185 (\342\:vdd! \353\:vdd!) resistor r=0.3768 c=0 +rf1186 (\343\:vdd! \354\:vdd!) resistor r=0.4019 c=0 +rf1187 (\344\:vdd! \355\:vdd!) resistor r=0.4019 c=0 +rf1188 (\345\:vdd! \356\:vdd!) resistor r=0.06262 c=0 +rf1189 (\349\:vdd! \357\:vdd!) resistor r=0.49 c=0 +rf1190 (\350\:vdd! \358\:vdd!) resistor r=0.1152 c=0 +rf1191 (\358\:vdd! \359\:vdd!) resistor r=0.4926 c=0 +rf1192 (\356\:vdd! \360\:vdd!) resistor r=0.4309 c=0 +rf1193 (\358\:vdd! \361\:vdd!) resistor r=0.02438 c=0 +rf1194 (\361\:vdd! \362\:vdd!) resistor r=0.04862 c=0 +rf1195 (\362\:vdd! \363\:vdd!) resistor r=0.5103 c=0 +rf1196 (\358\:vdd! \364\:vdd!) resistor r=0.5128 c=0 +rf1197 (\362\:vdd! \365\:vdd!) resistor r=0.07402 c=0 +rf1198 (\365\:vdd! \366\:vdd!) resistor r=0.0174 c=0 +rf1199 (\366\:vdd! \367\:vdd!) resistor r=0.4537 c=0 +rf1200 (\362\:vdd! \368\:vdd!) resistor r=0.5159 c=0 +rf1201 (\366\:vdd! \369\:vdd!) resistor r=0.5053 c=0 +rg1 (\7\:X3 \8\:X3) resistor r=91.5933 c=0 +rg2 (\8\:X3 \2\:X3) resistor r=3.7604 c=0 +rg3 (\8\:X3 \9\:X3) resistor r=62.0099 c=0 +rg4 (\10\:X3 \11\:X3) resistor r=91.5933 c=0 +rg5 (\11\:X3 \4\:X3) resistor r=3.7604 c=0 +rg6 (\11\:X3 \12\:X3) resistor r=62.0099 c=0 +rg7 (\13\:X3 \14\:X3) resistor r=91.5933 c=0 +rg8 (\14\:X3 \6\:X3) resistor r=3.7604 c=0 +rg9 (\14\:X3 \15\:X3) resistor r=62.0099 c=0 +rg10 (\1\:Y3 \2\:Y3) resistor r=3.7604 c=0 +rg11 (\2\:Y3 \3\:Y3) resistor r=62.0099 c=0 +rg12 (\2\:Y3 \4\:Y3) resistor r=91.5933 c=0 +rg13 (\1\:Y2 \2\:Y2) resistor r=3.7604 c=0 +rg14 (\2\:Y2 \3\:Y2) resistor r=62.0099 c=0 +rg15 (\2\:Y2 \4\:Y2) resistor r=91.5933 c=0 +rg16 (\1\:X0 \2\:X0) resistor r=3.7604 c=0 +rg17 (\2\:X0 \3\:X0) resistor r=91.5933 c=0 +rg18 (\2\:X0 \4\:X0) resistor r=62.0099 c=0 +rg20 (\2\:Y1 \3\:Y1) resistor r=62.0099 c=0 +rg21 (\2\:Y1 \4\:Y1) resistor r=91.5933 c=0 +rg22 (\4\:Y1 \5\:Y1) resistor r=134.735 c=0 +rg23 (\5\:I27\|net013 \6\:I27\|net013) resistor r=37.6755 c=0 +rg24 (\6\:I27\|net013 I27\|net013) resistor r=19.7812 c=0 +rg25 (\6\:I27\|net013 \7\:I27\|net013) resistor r=115.592 c=0 +rg26 (\5\:I20\|net013 \6\:I20\|net013) resistor r=37.6755 c=0 +rg27 (\6\:I20\|net013 I20\|net013) resistor r=19.7812 c=0 +rg28 (\6\:I20\|net013 \7\:I20\|net013) resistor r=115.592 c=0 +rg29 (\5\:I15\|net013 \6\:I15\|net013) resistor r=115.592 c=0 +rg30 (\6\:I15\|net013 I15\|net013) resistor r=19.7812 c=0 +rg31 (\6\:I15\|net013 \7\:I15\|net013) resistor r=37.6755 c=0 +rg32 (\5\:I19\|net013 \6\:I19\|net013) resistor r=37.6755 c=0 +rg33 (\6\:I19\|net013 I19\|net013) resistor r=19.7812 c=0 +rg34 (\6\:I19\|net013 \7\:I19\|net013) resistor r=115.592 c=0 +rg35 (\6\:net090 \7\:net090) resistor r=132.954 c=0 +rg36 (\7\:net090 \8\:net090) resistor r=83.7878 c=0 +rg37 (\7\:net090 net090) resistor r=15.5249 c=0 +rg38 (\6\:net13 \7\:net13) resistor r=132.954 c=0 +rg39 (\7\:net13 \8\:net13) resistor r=83.7878 c=0 +rg40 (\7\:net13 net13) resistor r=15.5249 c=0 +rg41 (I5\|I3\|net013 \2\:I5\|I3\|net013) resistor r=3.7604 c=0 +rg42 (\2\:I5\|I3\|net013 \3\:I5\|I3\|net013) resistor r=109.302 c=0 +rg43 (\2\:I5\|I3\|net013 \4\:I5\|I3\|net013) resistor r=43.2599 c=0 +rg44 (I4\|I4\|Bi \2\:I4\|I4\|Bi) resistor r=3.4479 c=0 +rg45 (\2\:I4\|I4\|Bi \3\:I4\|I4\|Bi) resistor r=70.5516 c=0 +rg46 (\2\:I4\|I4\|Bi \4\:I4\|I4\|Bi) resistor r=68.2599 c=0 +rg47 (\4\:I4\|I4\|Ai \5\:I4\|I4\|Ai) resistor r=426.762 c=0 +rg48 (\5\:I4\|I4\|Ai \3\:I4\|I4\|Ai) resistor r=295.399 c=0 +rg49 (I9\|I4\|Bi \2\:I9\|I4\|Bi) resistor r=3.4479 c=0 +rg50 (\2\:I9\|I4\|Bi \3\:I9\|I4\|Bi) resistor r=70.5516 c=0 +rg51 (\2\:I9\|I4\|Bi \4\:I9\|I4\|Bi) resistor r=68.2599 c=0 +rg52 (\4\:I9\|I4\|Ai \5\:I9\|I4\|Ai) resistor r=426.762 c=0 +rg53 (\5\:I9\|I4\|Ai \3\:I9\|I4\|Ai) resistor r=295.399 c=0 +rg54 (\9\:net090 \10\:net090) resistor r=68.6766 c=0 +rg55 (\10\:net090 \11\:net090) resistor r=39.0198 c=0 +rg56 (\11\:net090 \12\:net090) resistor r=3.7604 c=0 +rg57 (\12\:net090 \13\:net090) resistor r=42.4747 c=0 +rg58 (\13\:net090 \14\:net090) resistor r=51.4263 c=0 +rg59 (\10\:net090 \15\:net090) resistor r=3.6562 c=0 +rg60 (\11\:net090 \16\:net090) resistor r=47.6349 c=0 +rg61 (\13\:net090 \17\:net090) resistor r=106.01 c=0 +rg62 (\9\:net13 \10\:net13) resistor r=68.6766 c=0 +rg63 (\10\:net13 \11\:net13) resistor r=39.0198 c=0 +rg64 (\11\:net13 \12\:net13) resistor r=3.7604 c=0 +rg65 (\12\:net13 \13\:net13) resistor r=42.4747 c=0 +rg66 (\13\:net13 \14\:net13) resistor r=51.4263 c=0 +rg67 (\10\:net13 \15\:net13) resistor r=3.6562 c=0 +rg68 (\11\:net13 \16\:net13) resistor r=47.6349 c=0 +rg69 (\13\:net13 \17\:net13) resistor r=106.01 c=0 +rg70 (\5\:I5\|I1\|Bi \6\:I5\|I1\|Bi) resistor r=53.0516 c=0 +rg71 (\6\:I5\|I1\|Bi \4\:I5\|I1\|Bi) resistor r=3.6562 c=0 +rg72 (\6\:I5\|I1\|Bi \7\:I5\|I1\|Bi) resistor r=84.0933 c=0 +rg73 (\7\:net19 \9\:net19) resistor r=3.7604 c=0 +rg74 (\9\:net19 \10\:net19) resistor r=47.6349 c=0 +rg75 (\10\:net19 \11\:net19) resistor r=149.112 c=0 +rg76 (\11\:net19 \12\:net19) resistor r=237.862 c=0 +rg77 (\12\:net19 \13\:net19) resistor r=167.131 c=0 +rg78 (\9\:net19 \14\:net19) resistor r=109.093 c=0 +rg79 (\11\:net19 \15\:net19) resistor r=54.2235 c=0 +rg80 (\15\:net19 \16\:net19) resistor r=140.208 c=0 +rg81 (\2\:net16 \4\:net16) resistor r=3.7604 c=0 +rg82 (\4\:net16 \5\:net16) resistor r=47.6349 c=0 +rg83 (\5\:net16 \6\:net16) resistor r=149.112 c=0 +rg84 (\6\:net16 \7\:net16) resistor r=237.862 c=0 +rg85 (\7\:net16 \8\:net16) resistor r=167.131 c=0 +rg86 (\4\:net16 \9\:net16) resistor r=109.093 c=0 +rg87 (\6\:net16 \10\:net16) resistor r=54.2235 c=0 +rg88 (\10\:net16 \11\:net16) resistor r=140.208 c=0 +rg89 (\10\:I4\|net3 \11\:I4\|net3) resistor r=97.8433 c=0 +rg90 (\11\:I4\|net3 \9\:I4\|net3) resistor r=3.7604 c=0 +rg91 (\11\:I4\|net3 \12\:I4\|net3) resistor r=40.9683 c=0 +rg92 (\10\:I9\|net3 \11\:I9\|net3) resistor r=97.8433 c=0 +rg93 (\11\:I9\|net3 \9\:I9\|net3) resistor r=3.7604 c=0 +rg94 (\11\:I9\|net3 \12\:I9\|net3) resistor r=40.9683 c=0 +rg95 (\2\:net55 \7\:net55) resistor r=3.7604 c=0 +rg96 (\7\:net55 \8\:net55) resistor r=73.0516 c=0 +rg97 (\7\:net55 \9\:net55) resistor r=79.5099 c=0 +rg98 (\8\:net55 \5\:net55) resistor r=77.3221 c=0 +rg99 (\5\:I4\|net1 \6\:I4\|net1) resistor r=80.5516 c=0 +rg100 (\6\:I4\|net1 \4\:I4\|net1) resistor r=3.5521 c=0 +rg101 (\6\:I4\|net1 \7\:I4\|net1) resistor r=76.1766 c=0 +rg102 (\5\:I9\|net1 \6\:I9\|net1) resistor r=80.5516 c=0 +rg103 (\6\:I9\|net1 \4\:I9\|net1) resistor r=3.5521 c=0 +rg104 (\6\:I9\|net1 \7\:I9\|net1) resistor r=76.1766 c=0 +rg105 (\21\:X3 \22\:X3) resistor r=91.5933 c=0 +rg106 (\22\:X3 \20\:X3) resistor r=3.7604 c=0 +rg107 (\22\:X3 \23\:X3) resistor r=62.0099 c=0 +rg108 (\10\:net55 \11\:net55) resistor r=47.3355 c=0 +rg109 (\11\:net55 \12\:net55) resistor r=120.434 c=0 +rg110 (\12\:net55 \13\:net55) resistor r=41.6577 c=0 +rg111 (\11\:net55 \14\:net55) resistor r=7.4762 c=0 +rg112 (\12\:net55 \3\:net55) resistor r=32.1097 c=0 +rg113 (I4\|net6 \2\:I4\|net6) resistor r=3.5521 c=0 +rg114 (\2\:I4\|net6 \3\:I4\|net6) resistor r=77.0099 c=0 +rg115 (\2\:I4\|net6 \4\:I4\|net6) resistor r=79.7183 c=0 +rg116 (I9\|net6 \2\:I9\|net6) resistor r=3.5521 c=0 +rg117 (\2\:I9\|net6 \3\:I9\|net6) resistor r=77.0099 c=0 +rg118 (\2\:I9\|net6 \4\:I9\|net6) resistor r=79.7183 c=0 +rg119 (\6\:net093 \7\:net093) resistor r=174.262 c=0 +rg120 (\7\:net093 \8\:net093) resistor r=165.153 c=0 +rg121 (\8\:net093 \9\:net093) resistor r=116.403 c=0 +rg122 (\9\:net093 \10\:net093) resistor r=138.542 c=0 +rg123 (\8\:net093 \11\:net093) resistor r=135.474 c=0 +rg124 (\11\:net093 \12\:net093) resistor r=72.4266 c=0 +rg125 (\12\:net093 \4\:net093) resistor r=3.7604 c=0 +rg126 (\12\:net093 \13\:net093) resistor r=80.1349 c=0 +rg127 (I5\|I1\|Ai \2\:I5\|I1\|Ai) resistor r=77.852 c=0 +rg128 (\2\:I5\|I1\|Ai \3\:I5\|I1\|Ai) resistor r=333.882 c=0 +rg129 (\16\:net55 \17\:net55) resistor r=3.7604 c=0 +rg130 (\17\:net55 \18\:net55) resistor r=55.3433 c=0 +rg131 (\17\:net55 \19\:net55) resistor r=81.8016 c=0 +rg132 (\5\:I12\|net013 \6\:I12\|net013) resistor r=37.6755 c=0 +rg133 (\6\:I12\|net013 I12\|net013) resistor r=19.7812 c=0 +rg134 (\6\:I12\|net013 \7\:I12\|net013) resistor r=115.592 c=0 +rg135 (\16\:I4\|net3 \17\:I4\|net3) resistor r=158.125 c=0 +rg136 (\17\:I4\|net3 \18\:I4\|net3) resistor r=211.449 c=0 +rg137 (\18\:I4\|net3 \19\:I4\|net3) resistor r=168.536 c=0 +rg138 (\19\:I4\|net3 \15\:I4\|net3) resistor r=6.3083 c=0 +rg139 (\19\:I4\|net3 \20\:I4\|net3) resistor r=38.7601 c=0 +rg140 (\5\:I4\|I3\|Ai I4\|I3\|Ai) resistor r=317.339 c=0 +rg141 (I4\|I3\|Ai \6\:I4\|I3\|Ai) resistor r=91.8988 c=0 +rg142 (\16\:I9\|net3 \17\:I9\|net3) resistor r=158.125 c=0 +rg143 (\17\:I9\|net3 \18\:I9\|net3) resistor r=211.449 c=0 +rg144 (\18\:I9\|net3 \19\:I9\|net3) resistor r=168.536 c=0 +rg145 (\19\:I9\|net3 \15\:I9\|net3) resistor r=6.3083 c=0 +rg146 (\19\:I9\|net3 \20\:I9\|net3) resistor r=38.7601 c=0 +rg147 (\5\:I9\|I3\|Ai I9\|I3\|Ai) resistor r=317.339 c=0 +rg148 (I9\|I3\|Ai \6\:I9\|I3\|Ai) resistor r=91.8988 c=0 +rg149 (\4\:net21 \5\:net21) resistor r=181.923 c=0 +rg150 (\5\:net21 \6\:net21) resistor r=107.843 c=0 +rg151 (\6\:net21 \7\:net21) resistor r=48.8849 c=0 +rg152 (\7\:net21 \8\:net21) resistor r=189.671 c=0 +rg153 (\8\:net21 \9\:net21) resistor r=180.126 c=0 +rg154 (\4\:net21 \10\:net21) resistor r=158.125 c=0 +rg155 (\6\:net21 \3\:net21) resistor r=3.4479 c=0 +rg156 (\4\:net15 \5\:net15) resistor r=181.923 c=0 +rg157 (\5\:net15 \6\:net15) resistor r=107.843 c=0 +rg158 (\6\:net15 \7\:net15) resistor r=48.8849 c=0 +rg159 (\7\:net15 \8\:net15) resistor r=189.671 c=0 +rg160 (\8\:net15 \9\:net15) resistor r=180.126 c=0 +rg161 (\4\:net15 \10\:net15) resistor r=158.125 c=0 +rg162 (\6\:net15 \3\:net15) resistor r=3.4479 c=0 +rg163 (\9\:Y1 \10\:Y1) resistor r=62.0099 c=0 +rg165 (\10\:Y1 \11\:Y1) resistor r=91.5933 c=0 +rg166 (\11\:Y1 \12\:Y1) resistor r=135.03 c=0 +rg167 (I4\|I3\|Bi \2\:I4\|I3\|Bi) resistor r=271.714 c=0 +rg168 (\2\:I4\|I3\|Bi \3\:I4\|I3\|Bi) resistor r=140.208 c=0 +rg169 (I9\|I3\|Bi \2\:I9\|I3\|Bi) resistor r=271.714 c=0 +rg170 (\2\:I9\|I3\|Bi \3\:I9\|I3\|Bi) resistor r=140.208 c=0 +rg171 (\1\:X2 \2\:X2) resistor r=3.7604 c=0 +rg172 (\2\:X2 \3\:X2) resistor r=62.0099 c=0 +rg173 (\2\:X2 \4\:X2) resistor r=91.5933 c=0 +rg174 (\8\:Y3 \9\:Y3) resistor r=91.5933 c=0 +rg175 (\9\:Y3 \7\:Y3) resistor r=3.7604 c=0 +rg176 (\9\:Y3 \10\:Y3) resistor r=62.0099 c=0 +rg177 (\8\:Y2 \9\:Y2) resistor r=91.5933 c=0 +rg178 (\9\:Y2 \7\:Y2) resistor r=3.7604 c=0 +rg179 (\9\:Y2 \10\:Y2) resistor r=62.0099 c=0 +rg180 (\7\:X2 \8\:X2) resistor r=3.7604 c=0 +rg181 (\8\:X2 \9\:X2) resistor r=62.0099 c=0 +rg182 (\8\:X2 \10\:X2) resistor r=91.5933 c=0 +rg183 (\13\:X2 \16\:X2) resistor r=3.7604 c=0 +rg184 (\16\:X2 \17\:X2) resistor r=62.0099 c=0 +rg185 (\16\:X2 \18\:X2) resistor r=91.5933 c=0 +rg186 (\5\:I18\|net013 \6\:I18\|net013) resistor r=37.6755 c=0 +rg187 (\6\:I18\|net013 I18\|net013) resistor r=19.7812 c=0 +rg188 (\6\:I18\|net013 \7\:I18\|net013) resistor r=115.592 c=0 +rg189 (\6\:net38 \7\:net38) resistor r=132.954 c=0 +rg190 (\7\:net38 \8\:net38) resistor r=83.7878 c=0 +rg191 (\7\:net38 net38) resistor r=15.5249 c=0 +rg192 (\5\:I26\|net013 \6\:I26\|net013) resistor r=37.6755 c=0 +rg193 (\6\:I26\|net013 I26\|net013) resistor r=19.7812 c=0 +rg194 (\6\:I26\|net013 \7\:I26\|net013) resistor r=115.592 c=0 +rg195 (\5\:I21\|net013 \6\:I21\|net013) resistor r=37.6755 c=0 +rg196 (\6\:I21\|net013 I21\|net013) resistor r=19.7812 c=0 +rg197 (\6\:I21\|net013 \7\:I21\|net013) resistor r=115.592 c=0 +rg198 (I0\|I4\|Bi \2\:I0\|I4\|Bi) resistor r=3.4479 c=0 +rg199 (\2\:I0\|I4\|Bi \3\:I0\|I4\|Bi) resistor r=70.5516 c=0 +rg200 (\2\:I0\|I4\|Bi \4\:I0\|I4\|Bi) resistor r=68.2599 c=0 +rg201 (\4\:I0\|I4\|Ai \5\:I0\|I4\|Ai) resistor r=426.762 c=0 +rg202 (\5\:I0\|I4\|Ai \3\:I0\|I4\|Ai) resistor r=295.399 c=0 +rg203 (\6\:net8 \7\:net8) resistor r=132.954 c=0 +rg204 (\7\:net8 \8\:net8) resistor r=83.7878 c=0 +rg205 (\7\:net8 \4\:net8) resistor r=15.5249 c=0 +rg206 (\6\:net087 \7\:net087) resistor r=132.954 c=0 +rg207 (\7\:net087 \8\:net087) resistor r=83.7878 c=0 +rg208 (\7\:net087 \4\:net087) resistor r=15.5249 c=0 +rg209 (\13\:net38 \14\:net38) resistor r=68.6766 c=0 +rg210 (\14\:net38 \15\:net38) resistor r=39.0198 c=0 +rg211 (\15\:net38 \9\:net38) resistor r=3.7604 c=0 +rg212 (\9\:net38 \16\:net38) resistor r=42.4747 c=0 +rg213 (\16\:net38 \17\:net38) resistor r=51.4263 c=0 +rg214 (\14\:net38 \12\:net38) resistor r=3.6562 c=0 +rg215 (\15\:net38 \18\:net38) resistor r=47.6349 c=0 +rg216 (\16\:net38 \19\:net38) resistor r=106.01 c=0 +rg217 (I10\|I4\|Bi \2\:I10\|I4\|Bi) resistor r=3.4479 c=0 +rg218 (\2\:I10\|I4\|Bi \3\:I10\|I4\|Bi) resistor r=70.5516 c=0 +rg219 (\2\:I10\|I4\|Bi \4\:I10\|I4\|Bi) resistor r=68.2599 c=0 +rg220 (I10\|I4\|Ai \2\:I10\|I4\|Ai) resistor r=426.762 c=0 +rg221 (\2\:I10\|I4\|Ai \3\:I10\|I4\|Ai) resistor r=295.399 c=0 +rg222 (I3\|I4\|Bi \2\:I3\|I4\|Bi) resistor r=3.4479 c=0 +rg223 (\2\:I3\|I4\|Bi \3\:I3\|I4\|Bi) resistor r=70.5516 c=0 +rg224 (\2\:I3\|I4\|Bi \4\:I3\|I4\|Bi) resistor r=68.2599 c=0 +rg225 (\4\:I3\|I4\|Ai \5\:I3\|I4\|Ai) resistor r=426.762 c=0 +rg226 (\5\:I3\|I4\|Ai \3\:I3\|I4\|Ai) resistor r=295.399 c=0 +rg227 (\4\:net39 \5\:net39) resistor r=3.7604 c=0 +rg228 (\5\:net39 \6\:net39) resistor r=47.6349 c=0 +rg229 (\6\:net39 \7\:net39) resistor r=149.112 c=0 +rg230 (\7\:net39 \8\:net39) resistor r=237.862 c=0 +rg231 (\8\:net39 \9\:net39) resistor r=167.131 c=0 +rg232 (\5\:net39 \10\:net39) resistor r=109.093 c=0 +rg233 (\7\:net39 \11\:net39) resistor r=54.2235 c=0 +rg234 (\11\:net39 \12\:net39) resistor r=140.208 c=0 +rg235 (\13\:net8 \14\:net8) resistor r=68.6766 c=0 +rg236 (\14\:net8 \15\:net8) resistor r=39.0198 c=0 +rg237 (\15\:net8 \10\:net8) resistor r=3.7604 c=0 +rg238 (\10\:net8 \16\:net8) resistor r=42.4747 c=0 +rg239 (\16\:net8 \17\:net8) resistor r=51.4263 c=0 +rg240 (\14\:net8 \12\:net8) resistor r=3.6562 c=0 +rg241 (\15\:net8 \18\:net8) resistor r=47.6349 c=0 +rg242 (\16\:net8 \19\:net8) resistor r=106.01 c=0 +rg243 (\13\:net087 \14\:net087) resistor r=68.6766 c=0 +rg244 (\14\:net087 \15\:net087) resistor r=39.0198 c=0 +rg245 (\15\:net087 \9\:net087) resistor r=3.7604 c=0 +rg246 (\9\:net087 \16\:net087) resistor r=42.4747 c=0 +rg247 (\16\:net087 \17\:net087) resistor r=51.4263 c=0 +rg248 (\14\:net087 \12\:net087) resistor r=3.6562 c=0 +rg249 (\15\:net087 \18\:net087) resistor r=47.6349 c=0 +rg250 (\16\:net087 \19\:net087) resistor r=106.01 c=0 +rg251 (\10\:I0\|net3 \11\:I0\|net3) resistor r=97.8433 c=0 +rg252 (\11\:I0\|net3 \9\:I0\|net3) resistor r=3.7604 c=0 +rg253 (\11\:I0\|net3 \12\:I0\|net3) resistor r=40.9683 c=0 +rg254 (\5\:I0\|net1 \6\:I0\|net1) resistor r=80.5516 c=0 +rg255 (\6\:I0\|net1 \4\:I0\|net1) resistor r=3.5521 c=0 +rg256 (\6\:I0\|net1 \7\:I0\|net1) resistor r=76.1766 c=0 +rg257 (\10\:net17 \11\:net17) resistor r=3.7604 c=0 +rg258 (\11\:net17 \12\:net17) resistor r=47.6349 c=0 +rg259 (\12\:net17 \13\:net17) resistor r=149.112 c=0 +rg260 (\13\:net17 \14\:net17) resistor r=237.862 c=0 +rg261 (\14\:net17 \15\:net17) resistor r=167.131 c=0 +rg262 (\11\:net17 \16\:net17) resistor r=109.093 c=0 +rg263 (\13\:net17 \17\:net17) resistor r=54.2235 c=0 +rg264 (\17\:net17 \18\:net17) resistor r=140.208 c=0 +rg265 (\10\:net54 \11\:net54) resistor r=3.7604 c=0 +rg266 (\11\:net54 \12\:net54) resistor r=47.6349 c=0 +rg267 (\12\:net54 \13\:net54) resistor r=149.112 c=0 +rg268 (\13\:net54 \14\:net54) resistor r=237.862 c=0 +rg269 (\14\:net54 \15\:net54) resistor r=167.131 c=0 +rg270 (\11\:net54 \16\:net54) resistor r=109.093 c=0 +rg271 (\13\:net54 \17\:net54) resistor r=54.2235 c=0 +rg272 (\17\:net54 \18\:net54) resistor r=140.208 c=0 +rg273 (\10\:I10\|net3 \11\:I10\|net3) resistor r=97.8433 c=0 +rg274 (\11\:I10\|net3 \9\:I10\|net3) resistor r=3.7604 c=0 +rg275 (\11\:I10\|net3 \12\:I10\|net3) resistor r=40.9683 c=0 +rg276 (I0\|net6 \2\:I0\|net6) resistor r=3.5521 c=0 +rg277 (\2\:I0\|net6 \3\:I0\|net6) resistor r=77.0099 c=0 +rg278 (\2\:I0\|net6 \4\:I0\|net6) resistor r=79.7183 c=0 +rg279 (\10\:I3\|net3 \11\:I3\|net3) resistor r=97.8433 c=0 +rg280 (\11\:I3\|net3 \9\:I3\|net3) resistor r=3.7604 c=0 +rg281 (\11\:I3\|net3 \12\:I3\|net3) resistor r=40.9683 c=0 +rg282 (\5\:I10\|net1 \6\:I10\|net1) resistor r=80.5516 c=0 +rg283 (\6\:I10\|net1 \4\:I10\|net1) resistor r=3.5521 c=0 +rg284 (\6\:I10\|net1 \7\:I10\|net1) resistor r=76.1766 c=0 +rg285 (\5\:I3\|net1 \6\:I3\|net1) resistor r=80.5516 c=0 +rg286 (\6\:I3\|net1 \4\:I3\|net1) resistor r=3.5521 c=0 +rg287 (\6\:I3\|net1 \7\:I3\|net1) resistor r=76.1766 c=0 +rg288 (I10\|net6 \2\:I10\|net6) resistor r=3.5521 c=0 +rg289 (\2\:I10\|net6 \3\:I10\|net6) resistor r=77.0099 c=0 +rg290 (\2\:I10\|net6 \4\:I10\|net6) resistor r=79.7183 c=0 +rg291 (I3\|net6 \2\:I3\|net6) resistor r=3.5521 c=0 +rg292 (\2\:I3\|net6 \3\:I3\|net6) resistor r=77.0099 c=0 +rg293 (\2\:I3\|net6 \4\:I3\|net6) resistor r=79.7183 c=0 +rg294 (\16\:I0\|net3 \17\:I0\|net3) resistor r=158.125 c=0 +rg295 (\17\:I0\|net3 \18\:I0\|net3) resistor r=211.449 c=0 +rg296 (\18\:I0\|net3 \19\:I0\|net3) resistor r=168.536 c=0 +rg297 (\19\:I0\|net3 \13\:I0\|net3) resistor r=6.3083 c=0 +rg298 (\19\:I0\|net3 \20\:I0\|net3) resistor r=38.7601 c=0 +rg299 (\5\:I0\|I3\|Ai I0\|I3\|Ai) resistor r=317.339 c=0 +rg300 (I0\|I3\|Ai \6\:I0\|I3\|Ai) resistor r=91.8988 c=0 +rg301 (\3\:net31 \4\:net31) resistor r=181.923 c=0 +rg302 (\4\:net31 \5\:net31) resistor r=107.843 c=0 +rg303 (\5\:net31 \6\:net31) resistor r=48.8849 c=0 +rg304 (\6\:net31 \7\:net31) resistor r=189.671 c=0 +rg305 (\7\:net31 \8\:net31) resistor r=180.126 c=0 +rg306 (\3\:net31 \9\:net31) resistor r=158.125 c=0 +rg307 (\5\:net31 net31) resistor r=3.4479 c=0 +rg308 (\16\:I10\|net3 \17\:I10\|net3) resistor r=158.125 c=0 +rg309 (\17\:I10\|net3 \18\:I10\|net3) resistor r=211.449 c=0 +rg310 (\18\:I10\|net3 \19\:I10\|net3) resistor r=168.536 c=0 +rg311 (\19\:I10\|net3 \15\:I10\|net3) resistor r=6.3083 c=0 +rg312 (\19\:I10\|net3 \20\:I10\|net3) resistor r=38.7601 c=0 +rg313 (\5\:I10\|I3\|Ai I10\|I3\|Ai) resistor r=317.339 c=0 +rg314 (I10\|I3\|Ai \6\:I10\|I3\|Ai) resistor r=91.8988 c=0 +rg315 (I0\|I3\|Bi \5\:I0\|I3\|Bi) resistor r=271.714 c=0 +rg316 (\5\:I0\|I3\|Bi \6\:I0\|I3\|Bi) resistor r=140.208 c=0 +rg317 (\16\:I3\|net3 \17\:I3\|net3) resistor r=158.125 c=0 +rg318 (\17\:I3\|net3 \18\:I3\|net3) resistor r=211.449 c=0 +rg319 (\18\:I3\|net3 \19\:I3\|net3) resistor r=168.536 c=0 +rg320 (\19\:I3\|net3 \13\:I3\|net3) resistor r=6.3083 c=0 +rg321 (\19\:I3\|net3 \20\:I3\|net3) resistor r=38.7601 c=0 +rg322 (\5\:I3\|I3\|Ai I3\|I3\|Ai) resistor r=317.339 c=0 +rg323 (I3\|I3\|Ai \6\:I3\|I3\|Ai) resistor r=91.8988 c=0 +rg324 (\3\:net1 \4\:net1) resistor r=181.923 c=0 +rg325 (\4\:net1 \5\:net1) resistor r=107.843 c=0 +rg326 (\5\:net1 \6\:net1) resistor r=48.8849 c=0 +rg327 (\6\:net1 \7\:net1) resistor r=189.671 c=0 +rg328 (\7\:net1 \8\:net1) resistor r=180.126 c=0 +rg329 (\3\:net1 \9\:net1) resistor r=158.125 c=0 +rg330 (\5\:net1 net1) resistor r=3.4479 c=0 +rg331 (\3\:net26 \4\:net26) resistor r=181.923 c=0 +rg332 (\4\:net26 \5\:net26) resistor r=107.843 c=0 +rg333 (\5\:net26 \6\:net26) resistor r=48.8849 c=0 +rg334 (\6\:net26 \7\:net26) resistor r=189.671 c=0 +rg335 (\7\:net26 \8\:net26) resistor r=180.126 c=0 +rg336 (\3\:net26 \9\:net26) resistor r=158.125 c=0 +rg337 (\5\:net26 net26) resistor r=3.4479 c=0 +rg338 (I10\|I3\|Bi \2\:I10\|I3\|Bi) resistor r=271.714 c=0 +rg339 (\2\:I10\|I3\|Bi \3\:I10\|I3\|Bi) resistor r=140.208 c=0 +rg340 (\5\:I1\|I3\|Bi \3\:I1\|I3\|Bi) resistor r=271.714 c=0 +rg341 (\5\:I1\|I3\|Bi \6\:I1\|I3\|Bi) resistor r=140.208 c=0 +rg342 (I3\|I3\|Bi \2\:I3\|I3\|Bi) resistor r=271.714 c=0 +rg343 (\2\:I3\|I3\|Bi \3\:I3\|I3\|Bi) resistor r=140.208 c=0 +rg344 (\5\:I11\|I3\|Bi \3\:I11\|I3\|Bi) resistor r=271.714 c=0 +rg345 (\5\:I11\|I3\|Bi \6\:I11\|I3\|Bi) resistor r=140.208 c=0 +rg346 (I1\|net3 \2\:I1\|net3) resistor r=38.7601 c=0 +rg347 (\2\:I1\|net3 \3\:I1\|net3) resistor r=168.536 c=0 +rg348 (\2\:I1\|net3 \4\:I1\|net3) resistor r=6.3083 c=0 +rg349 (\3\:I1\|net3 \5\:I1\|net3) resistor r=211.449 c=0 +rg350 (\5\:I1\|net3 \6\:I1\|net3) resistor r=158.125 c=0 +rg351 (\5\:I2\|I3\|Bi \3\:I2\|I3\|Bi) resistor r=271.714 c=0 +rg352 (\5\:I2\|I3\|Bi \6\:I2\|I3\|Bi) resistor r=140.208 c=0 +rg353 (\3\:net35 \4\:net35) resistor r=180.126 c=0 +rg354 (\4\:net35 \5\:net35) resistor r=193.622 c=0 +rg355 (\5\:net35 \6\:net35) resistor r=48.8849 c=0 +rg356 (\6\:net35 \7\:net35) resistor r=107.843 c=0 +rg357 (\7\:net35 \8\:net35) resistor r=181.923 c=0 +rg358 (\8\:net35 \9\:net35) resistor r=158.125 c=0 +rg359 (\6\:net35 net35) resistor r=3.4479 c=0 +rg360 (\5\:I1\|net6 \6\:I1\|net6) resistor r=79.7183 c=0 +rg361 (\6\:I1\|net6 \4\:I1\|net6) resistor r=3.5521 c=0 +rg362 (\6\:I1\|net6 \7\:I1\|net6) resistor r=77.0099 c=0 +rg363 (I1\|I3\|Ai \2\:I1\|I3\|Ai) resistor r=91.8988 c=0 +rg364 (\2\:I1\|I3\|Ai \3\:I1\|I3\|Ai) resistor r=317.339 c=0 +rg365 (I1\|net1 \2\:I1\|net1) resistor r=3.5521 c=0 +rg366 (\2\:I1\|net1 \3\:I1\|net1) resistor r=76.1766 c=0 +rg367 (\2\:I1\|net1 \4\:I1\|net1) resistor r=80.5516 c=0 +rg368 (I11\|net3 \2\:I11\|net3) resistor r=38.7601 c=0 +rg369 (\2\:I11\|net3 \3\:I11\|net3) resistor r=168.536 c=0 +rg370 (\2\:I11\|net3 \4\:I11\|net3) resistor r=6.3083 c=0 +rg371 (\3\:I11\|net3 \5\:I11\|net3) resistor r=211.449 c=0 +rg372 (\5\:I11\|net3 \6\:I11\|net3) resistor r=158.125 c=0 +rg373 (\8\:I1\|net3 \9\:I1\|net3) resistor r=3.7604 c=0 +rg374 (\9\:I1\|net3 \10\:I1\|net3) resistor r=40.9683 c=0 +rg375 (\9\:I1\|net3 \11\:I1\|net3) resistor r=97.8433 c=0 +rg376 (\4\:net5 \5\:net5) resistor r=180.126 c=0 +rg377 (\5\:net5 \6\:net5) resistor r=193.622 c=0 +rg378 (\6\:net5 \7\:net5) resistor r=48.8849 c=0 +rg379 (\7\:net5 \8\:net5) resistor r=107.843 c=0 +rg380 (\8\:net5 \9\:net5) resistor r=181.923 c=0 +rg381 (\9\:net5 \10\:net5) resistor r=158.125 c=0 +rg382 (\7\:net5 net5) resistor r=3.4479 c=0 +rg383 (I2\|net3 \2\:I2\|net3) resistor r=38.7601 c=0 +rg384 (\2\:I2\|net3 \3\:I2\|net3) resistor r=168.536 c=0 +rg385 (\2\:I2\|net3 \4\:I2\|net3) resistor r=6.3083 c=0 +rg386 (\3\:I2\|net3 \5\:I2\|net3) resistor r=211.449 c=0 +rg387 (\5\:I2\|net3 \6\:I2\|net3) resistor r=158.125 c=0 +rg388 (\5\:I11\|net6 \6\:I11\|net6) resistor r=79.7183 c=0 +rg389 (\6\:I11\|net6 \4\:I11\|net6) resistor r=3.5521 c=0 +rg390 (\6\:I11\|net6 \7\:I11\|net6) resistor r=77.0099 c=0 +rg391 (\3\:net45 \4\:net45) resistor r=180.126 c=0 +rg392 (\4\:net45 \5\:net45) resistor r=193.622 c=0 +rg393 (\5\:net45 \6\:net45) resistor r=48.8849 c=0 +rg394 (\6\:net45 \7\:net45) resistor r=107.843 c=0 +rg395 (\7\:net45 \8\:net45) resistor r=181.923 c=0 +rg396 (\8\:net45 \9\:net45) resistor r=158.125 c=0 +rg397 (\6\:net45 net45) resistor r=3.4479 c=0 +rg398 (I11\|I3\|Ai \2\:I11\|I3\|Ai) resistor r=91.8988 c=0 +rg399 (\2\:I11\|I3\|Ai \3\:I11\|I3\|Ai) resistor r=317.339 c=0 +rg400 (\5\:I2\|net6 \6\:I2\|net6) resistor r=79.7183 c=0 +rg401 (\6\:I2\|net6 \4\:I2\|net6) resistor r=3.5521 c=0 +rg402 (\6\:I2\|net6 \7\:I2\|net6) resistor r=77.0099 c=0 +rg403 (I11\|net1 \2\:I11\|net1) resistor r=3.5521 c=0 +rg404 (\2\:I11\|net1 \3\:I11\|net1) resistor r=76.1766 c=0 +rg405 (\2\:I11\|net1 \4\:I11\|net1) resistor r=80.5516 c=0 +rg406 (I2\|I3\|Ai \2\:I2\|I3\|Ai) resistor r=91.8988 c=0 +rg407 (\2\:I2\|I3\|Ai \3\:I2\|I3\|Ai) resistor r=317.339 c=0 +rg408 (\8\:I11\|net3 \9\:I11\|net3) resistor r=3.7604 c=0 +rg409 (\9\:I11\|net3 \10\:I11\|net3) resistor r=40.9683 c=0 +rg410 (\9\:I11\|net3 \11\:I11\|net3) resistor r=97.8433 c=0 +rg411 (I2\|net1 \2\:I2\|net1) resistor r=3.5521 c=0 +rg412 (\2\:I2\|net1 \3\:I2\|net1) resistor r=76.1766 c=0 +rg413 (\2\:I2\|net1 \4\:I2\|net1) resistor r=80.5516 c=0 +rg414 (\5\:I1\|I4\|Ai \6\:I1\|I4\|Ai) resistor r=68.2599 c=0 +rg415 (\6\:I1\|I4\|Ai \4\:I1\|I4\|Ai) resistor r=3.4479 c=0 +rg416 (\6\:I1\|I4\|Ai \7\:I1\|I4\|Ai) resistor r=70.5516 c=0 +rg417 (\8\:I2\|net3 \10\:I2\|net3) resistor r=3.7604 c=0 +rg418 (\10\:I2\|net3 \11\:I2\|net3) resistor r=40.9683 c=0 +rg419 (\10\:I2\|net3 \12\:I2\|net3) resistor r=97.8433 c=0 +rg420 (\5\:net34 \6\:net34) resistor r=106.125 c=0 +rg421 (\6\:net34 \4\:net34) resistor r=42.5281 c=0 +rg422 (\4\:net34 \7\:net34) resistor r=3.7604 c=0 +rg423 (\7\:net34 \8\:net34) resistor r=47.6349 c=0 +rg424 (\6\:net34 \9\:net34) resistor r=51.3337 c=0 +rg425 (\7\:net34 \10\:net34) resistor r=39.0198 c=0 +rg426 (\10\:net34 \11\:net34) resistor r=68.6766 c=0 +rg427 (\10\:net34 net34) resistor r=3.6562 c=0 +rg428 (\22\:X2 \23\:X2) resistor r=91.5933 c=0 +rg429 (\23\:X2 \20\:X2) resistor r=3.7604 c=0 +rg430 (\23\:X2 \24\:X2) resistor r=62.0099 c=0 +rg431 (\5\:I11\|I4\|Bi \6\:I11\|I4\|Bi) resistor r=68.2599 c=0 +rg432 (\6\:I11\|I4\|Bi \4\:I11\|I4\|Bi) resistor r=3.4479 c=0 +rg433 (\6\:I11\|I4\|Bi \7\:I11\|I4\|Bi) resistor r=70.5516 c=0 +rg434 (\5\:net078 \6\:net078) resistor r=106.125 c=0 +rg435 (\6\:net078 \4\:net078) resistor r=42.5281 c=0 +rg436 (\4\:net078 \7\:net078) resistor r=3.7604 c=0 +rg437 (\7\:net078 \8\:net078) resistor r=47.6349 c=0 +rg438 (\6\:net078 \9\:net078) resistor r=51.3337 c=0 +rg439 (\7\:net078 \10\:net078) resistor r=39.0198 c=0 +rg440 (\10\:net078 \11\:net078) resistor r=68.6766 c=0 +rg441 (\10\:net078 net078) resistor r=3.6562 c=0 +rg442 (\14\:net34 \15\:net34) resistor r=83.7878 c=0 +rg443 (\15\:net34 \16\:net34) resistor r=132.954 c=0 +rg444 (\15\:net34 \12\:net34) resistor r=15.5249 c=0 +rg445 (\5\:I2\|I4\|Bi \6\:I2\|I4\|Bi) resistor r=68.2599 c=0 +rg446 (\6\:I2\|I4\|Bi \4\:I2\|I4\|Bi) resistor r=3.4479 c=0 +rg447 (\6\:I2\|I4\|Bi \7\:I2\|I4\|Bi) resistor r=70.5516 c=0 +rg448 (\5\:net28 \6\:net28) resistor r=106.125 c=0 +rg449 (\6\:net28 \4\:net28) resistor r=42.5281 c=0 +rg450 (\4\:net28 \7\:net28) resistor r=3.7604 c=0 +rg451 (\7\:net28 \8\:net28) resistor r=47.6349 c=0 +rg452 (\6\:net28 \9\:net28) resistor r=51.3337 c=0 +rg453 (\7\:net28 \10\:net28) resistor r=39.0198 c=0 +rg454 (\10\:net28 \11\:net28) resistor r=68.6766 c=0 +rg455 (\10\:net28 net28) resistor r=3.6562 c=0 +rg456 (\3\:net095 \4\:net095) resistor r=167.131 c=0 +rg457 (\4\:net095 \5\:net095) resistor r=237.862 c=0 +rg458 (\5\:net095 \6\:net095) resistor r=149.112 c=0 +rg459 (\6\:net095 \7\:net095) resistor r=47.6349 c=0 +rg460 (\7\:net095 net095) resistor r=3.7604 c=0 +rg461 (\5\:net095 \8\:net095) resistor r=54.2235 c=0 +rg462 (\8\:net095 \9\:net095) resistor r=140.208 c=0 +rg463 (\7\:net095 \10\:net095) resistor r=109.093 c=0 +rg464 (\4\:I1\|I4\|Bi \5\:I1\|I4\|Bi) resistor r=426.762 c=0 +rg465 (\5\:I1\|I4\|Bi \3\:I1\|I4\|Bi) resistor r=295.399 c=0 +rg466 (\5\:I13\|net013 \6\:I13\|net013) resistor r=37.6755 c=0 +rg467 (\6\:I13\|net013 I13\|net013) resistor r=19.7812 c=0 +rg468 (\6\:I13\|net013 \7\:I13\|net013) resistor r=115.592 c=0 +rg469 (\17\:net078 \18\:net078) resistor r=83.7878 c=0 +rg470 (\18\:net078 \19\:net078) resistor r=132.954 c=0 +rg471 (\18\:net078 \12\:net078) resistor r=15.5249 c=0 +rg472 (\17\:net28 \18\:net28) resistor r=83.7878 c=0 +rg473 (\18\:net28 \19\:net28) resistor r=132.954 c=0 +rg474 (\18\:net28 \12\:net28) resistor r=15.5249 c=0 +rg475 (\12\:net0100 \13\:net0100) resistor r=167.131 c=0 +rg476 (\13\:net0100 \14\:net0100) resistor r=237.862 c=0 +rg477 (\14\:net0100 \15\:net0100) resistor r=149.112 c=0 +rg478 (\15\:net0100 \16\:net0100) resistor r=47.6349 c=0 +rg479 (\16\:net0100 \9\:net0100) resistor r=3.7604 c=0 +rg480 (\14\:net0100 \17\:net0100) resistor r=54.2235 c=0 +rg481 (\17\:net0100 \18\:net0100) resistor r=140.208 c=0 +rg482 (\16\:net0100 \19\:net0100) resistor r=109.093 c=0 +rg483 (net0115 \2\:net0115) resistor r=81.8016 c=0 +rg484 (\2\:net0115 \3\:net0115) resistor r=3.7604 c=0 +rg485 (\2\:net0115 \4\:net0115) resistor r=55.3433 c=0 +rg486 (\4\:X1 \5\:X1) resistor r=91.5933 c=0 +rg487 (\5\:X1 \2\:X1) resistor r=3.7604 c=0 +rg488 (\5\:X1 \6\:X1) resistor r=62.0099 c=0 +rg489 (\12\:net29 \13\:net29) resistor r=167.131 c=0 +rg490 (\13\:net29 \14\:net29) resistor r=237.862 c=0 +rg491 (\14\:net29 \15\:net29) resistor r=149.112 c=0 +rg492 (\15\:net29 \16\:net29) resistor r=47.6349 c=0 +rg493 (\16\:net29 \9\:net29) resistor r=3.7604 c=0 +rg494 (\14\:net29 \17\:net29) resistor r=54.2235 c=0 +rg495 (\17\:net29 \18\:net29) resistor r=140.208 c=0 +rg496 (\16\:net29 \19\:net29) resistor r=109.093 c=0 +rg497 (\4\:I11\|I4\|Ai \5\:I11\|I4\|Ai) resistor r=426.762 c=0 +rg498 (\5\:I11\|I4\|Ai \3\:I11\|I4\|Ai) resistor r=295.399 c=0 +rg499 (I24\|net013 \2\:I24\|net013) resistor r=19.7812 c=0 +rg500 (\2\:I24\|net013 \3\:I24\|net013) resistor r=115.592 c=0 +rg501 (\2\:I24\|net013 \4\:I24\|net013) resistor r=37.6755 c=0 +rg502 (I23\|net013 \2\:I23\|net013) resistor r=19.7812 c=0 +rg503 (\2\:I23\|net013 \3\:I23\|net013) resistor r=115.592 c=0 +rg504 (\2\:I23\|net013 \4\:I23\|net013) resistor r=37.6755 c=0 +rg505 (\10\:X1 \11\:X1) resistor r=91.5933 c=0 +rg506 (\11\:X1 \7\:X1) resistor r=3.7604 c=0 +rg507 (\11\:X1 \12\:X1) resistor r=62.0099 c=0 +rg508 (\4\:I2\|I4\|Ai \5\:I2\|I4\|Ai) resistor r=426.762 c=0 +rg509 (\5\:I2\|I4\|Ai \3\:I2\|I4\|Ai) resistor r=295.399 c=0 +rg510 (\15\:X1 \16\:X1) resistor r=91.5933 c=0 +rg511 (\16\:X1 \13\:X1) resistor r=3.7604 c=0 +rg512 (\16\:X1 \17\:X1) resistor r=62.0099 c=0 +rg514 (\15\:Y1 \16\:Y1) resistor r=62.0099 c=0 +rg515 (\15\:Y1 \17\:Y1) resistor r=91.5933 c=0 +rg516 (\17\:Y1 \18\:Y1) resistor r=135.482 c=0 +rg517 (\11\:Y3 \12\:Y3) resistor r=3.7604 c=0 +rg518 (\12\:Y3 \13\:Y3) resistor r=62.0099 c=0 +rg519 (\12\:Y3 \14\:Y3) resistor r=91.5933 c=0 +rg520 (\11\:Y2 \12\:Y2) resistor r=3.7604 c=0 +rg521 (\12\:Y2 \13\:Y2) resistor r=62.0099 c=0 +rg522 (\12\:Y2 \14\:Y2) resistor r=91.5933 c=0 +rg523 (\5\:I16\|net013 \6\:I16\|net013) resistor r=37.6755 c=0 +rg524 (\6\:I16\|net013 I16\|net013) resistor r=19.7812 c=0 +rg525 (\6\:I16\|net013 \7\:I16\|net013) resistor r=115.592 c=0 +rg526 (\12\:net0115 \13\:net0115) resistor r=79.5099 c=0 +rg527 (\13\:net0115 \14\:net0115) resistor r=73.0516 c=0 +rg528 (\14\:net0115 \8\:net0115) resistor r=77.3221 c=0 +rg529 (\13\:net0115 \15\:net0115) resistor r=3.7604 c=0 +rg530 (\16\:net0115 \17\:net0115) resistor r=41.6577 c=0 +rg531 (\17\:net0115 \18\:net0115) resistor r=120.434 c=0 +rg532 (\18\:net0115 \7\:net0115) resistor r=7.4762 c=0 +rg533 (\17\:net0115 \11\:net0115) resistor r=32.1097 c=0 +rg534 (\18\:net0115 \19\:net0115) resistor r=47.3355 c=0 +rg535 (\5\:I6\|I1\|Ai I6\|I1\|Ai) resistor r=333.423 c=0 +rg536 (I6\|I1\|Ai \6\:I6\|I1\|Ai) resistor r=76.0655 c=0 +rg537 (I8\|I3\|net013 \2\:I8\|I3\|net013) resistor r=3.7604 c=0 +rg538 (\2\:I8\|I3\|net013 \3\:I8\|I3\|net013) resistor r=109.302 c=0 +rg539 (\2\:I8\|I3\|net013 \4\:I8\|I3\|net013) resistor r=43.2599 c=0 +rg540 (I7\|I3\|net013 \2\:I7\|I3\|net013) resistor r=3.7604 c=0 +rg541 (\2\:I7\|I3\|net013 \3\:I7\|I3\|net013) resistor r=109.302 c=0 +rg542 (\2\:I7\|I3\|net013 \4\:I7\|I3\|net013) resistor r=43.2599 c=0 +rg543 (I6\|I1\|Bi \2\:I6\|I1\|Bi) resistor r=3.6562 c=0 +rg544 (\2\:I6\|I1\|Bi \3\:I6\|I1\|Bi) resistor r=84.0933 c=0 +rg545 (\2\:I6\|I1\|Bi \4\:I6\|I1\|Bi) resistor r=53.0516 c=0 +rg546 (\5\:I8\|I1\|Bi \6\:I8\|I1\|Bi) resistor r=53.0516 c=0 +rg547 (\6\:I8\|I1\|Bi \4\:I8\|I1\|Bi) resistor r=3.6562 c=0 +rg548 (\6\:I8\|I1\|Bi \7\:I8\|I1\|Bi) resistor r=84.0933 c=0 +rg549 (\5\:I7\|I1\|Bi \6\:I7\|I1\|Bi) resistor r=53.0516 c=0 +rg550 (\6\:I7\|I1\|Bi \4\:I7\|I1\|Bi) resistor r=3.6562 c=0 +rg551 (\6\:I7\|I1\|Bi \7\:I7\|I1\|Bi) resistor r=84.0933 c=0 +rg552 (I6\|I3\|net013 \2\:I6\|I3\|net013) resistor r=43.2599 c=0 +rg553 (\2\:I6\|I3\|net013 \3\:I6\|I3\|net013) resistor r=3.7604 c=0 +rg554 (\2\:I6\|I3\|net013 \4\:I6\|I3\|net013) resistor r=109.302 c=0 +rg555 (\3\:net0127 \4\:net0127) resistor r=116.403 c=0 +rg556 (\4\:net0127 \5\:net0127) resistor r=165.153 c=0 +rg557 (\5\:net0127 \6\:net0127) resistor r=174.262 c=0 +rg558 (\3\:net0127 \7\:net0127) resistor r=138.542 c=0 +rg559 (\4\:net0127 \8\:net0127) resistor r=135.474 c=0 +rg560 (\8\:net0127 \9\:net0127) resistor r=72.4266 c=0 +rg561 (\9\:net0127 \10\:net0127) resistor r=80.1349 c=0 +rg562 (\9\:net0127 \2\:net0127) resistor r=3.7604 c=0 +rg563 (\2\:net075 \7\:net075) resistor r=3.7604 c=0 +rg564 (\7\:net075 \8\:net075) resistor r=73.0516 c=0 +rg565 (\7\:net075 \9\:net075) resistor r=79.5099 c=0 +rg566 (\8\:net075 \5\:net075) resistor r=77.3221 c=0 +rg567 (\2\:net47 \7\:net47) resistor r=3.7604 c=0 +rg568 (\7\:net47 \8\:net47) resistor r=73.0516 c=0 +rg569 (\7\:net47 \9\:net47) resistor r=79.5099 c=0 +rg570 (\8\:net47 \5\:net47) resistor r=77.3221 c=0 +rg571 (\19\:X1 \20\:X1) resistor r=91.5933 c=0 +rg572 (\20\:X1 \21\:X1) resistor r=3.7604 c=0 +rg573 (\20\:X1 \22\:X1) resistor r=62.0099 c=0 +rg574 (\13\:net075 \14\:net075) resistor r=47.3355 c=0 +rg575 (\14\:net075 \15\:net075) resistor r=120.434 c=0 +rg576 (\15\:net075 \16\:net075) resistor r=41.6577 c=0 +rg577 (\14\:net075 \17\:net075) resistor r=7.4762 c=0 +rg578 (\15\:net075 \3\:net075) resistor r=32.1097 c=0 +rg579 (\13\:net47 \14\:net47) resistor r=47.3355 c=0 +rg580 (\14\:net47 \15\:net47) resistor r=120.434 c=0 +rg581 (\15\:net47 \16\:net47) resistor r=41.6577 c=0 +rg582 (\14\:net47 \17\:net47) resistor r=7.4762 c=0 +rg583 (\15\:net47 \3\:net47) resistor r=32.1097 c=0 +rg584 (\7\:X0 \8\:X0) resistor r=3.7604 c=0 +rg585 (\8\:X0 \9\:X0) resistor r=91.5933 c=0 +rg586 (\8\:X0 \10\:X0) resistor r=62.0099 c=0 +rg587 (\12\:net44 \13\:net44) resistor r=174.262 c=0 +rg588 (\13\:net44 \14\:net44) resistor r=165.153 c=0 +rg589 (\14\:net44 \15\:net44) resistor r=116.403 c=0 +rg590 (\15\:net44 \16\:net44) resistor r=138.542 c=0 +rg591 (\14\:net44 \17\:net44) resistor r=135.474 c=0 +rg592 (\17\:net44 \18\:net44) resistor r=72.4266 c=0 +rg593 (\18\:net44 \9\:net44) resistor r=3.7604 c=0 +rg594 (\18\:net44 \19\:net44) resistor r=80.1349 c=0 +rg595 (\12\:net32 \13\:net32) resistor r=174.262 c=0 +rg596 (\13\:net32 \14\:net32) resistor r=165.153 c=0 +rg597 (\14\:net32 \15\:net32) resistor r=116.403 c=0 +rg598 (\15\:net32 \16\:net32) resistor r=138.542 c=0 +rg599 (\14\:net32 \17\:net32) resistor r=135.474 c=0 +rg600 (\17\:net32 \18\:net32) resistor r=72.4266 c=0 +rg601 (\18\:net32 \9\:net32) resistor r=3.7604 c=0 +rg602 (\18\:net32 \19\:net32) resistor r=80.1349 c=0 +rg603 (I25\|net013 \2\:I25\|net013) resistor r=19.7812 c=0 +rg604 (\2\:I25\|net013 \3\:I25\|net013) resistor r=115.592 c=0 +rg605 (\2\:I25\|net013 \4\:I25\|net013) resistor r=37.6755 c=0 +rg606 (I22\|net013 \2\:I22\|net013) resistor r=19.7812 c=0 +rg607 (\2\:I22\|net013 \3\:I22\|net013) resistor r=115.592 c=0 +rg608 (\2\:I22\|net013 \4\:I22\|net013) resistor r=37.6755 c=0 +rg609 (\18\:Y3 \19\:Y3) resistor r=91.5933 c=0 +rg610 (\19\:Y3 \16\:Y3) resistor r=3.7604 c=0 +rg611 (\19\:Y3 \20\:Y3) resistor r=62.0099 c=0 +rg612 (\18\:Y2 \19\:Y2) resistor r=91.5933 c=0 +rg613 (\19\:Y2 \16\:Y2) resistor r=3.7604 c=0 +rg614 (\19\:Y2 \20\:Y2) resistor r=62.0099 c=0 +rg615 (I8\|I1\|Ai \2\:I8\|I1\|Ai) resistor r=77.852 c=0 +rg616 (\2\:I8\|I1\|Ai \3\:I8\|I1\|Ai) resistor r=333.882 c=0 +rg617 (I7\|I1\|Ai \2\:I7\|I1\|Ai) resistor r=77.852 c=0 +rg618 (\2\:I7\|I1\|Ai \3\:I7\|I1\|Ai) resistor r=333.882 c=0 +rg619 (\5\:I14\|net013 \6\:I14\|net013) resistor r=37.6755 c=0 +rg620 (\6\:I14\|net013 I14\|net013) resistor r=19.7812 c=0 +rg621 (\6\:I14\|net013 \7\:I14\|net013) resistor r=115.592 c=0 +rg622 (\5\:I17\|net013 \6\:I17\|net013) resistor r=115.592 c=0 +rg623 (\6\:I17\|net013 I17\|net013) resistor r=19.7812 c=0 +rg624 (\6\:I17\|net013 \7\:I17\|net013) resistor r=37.6755 c=0 +rg625 (\12\:X0 \13\:X0) resistor r=3.7604 c=0 +rg626 (\13\:X0 \14\:X0) resistor r=62.0099 c=0 +rg627 (\13\:X0 \15\:X0) resistor r=91.5933 c=0 +rg628 (\16\:X0 \17\:X0) resistor r=3.7604 c=0 +rg629 (\17\:X0 \18\:X0) resistor r=62.0099 c=0 +rg630 (\17\:X0 \19\:X0) resistor r=91.5933 c=0 +rg631 (\19\:net075 \20\:net075) resistor r=3.7604 c=0 +rg632 (\20\:net075 \21\:net075) resistor r=55.3433 c=0 +rg633 (\20\:net075 \22\:net075) resistor r=81.8016 c=0 +rg634 (\19\:net47 \20\:net47) resistor r=3.7604 c=0 +rg635 (\20\:net47 \21\:net47) resistor r=55.3433 c=0 +rg636 (\20\:net47 \22\:net47) resistor r=81.8016 c=0 +rg637 (\21\:Y1 \22\:Y1) resistor r=627.236 c=0 +rg638 (\22\:Y1 \23\:Y1) resistor r=62.0099 c=0 +rg640 (\23\:Y1 \24\:Y1) resistor r=91.5933 c=0 +rg641 (Y0 \9\:Y0) resistor r=129.31 c=0 +rg642 (\9\:Y0 \10\:Y0) resistor r=455.086 c=0 +rg643 (\10\:Y0 \11\:Y0) resistor r=1019.75 c=0 +rg644 (\11\:Y0 \12\:Y0) resistor r=948.15 c=0 +rg645 (\12\:Y0 \13\:Y0) resistor r=62.0099 c=0 +rg647 (\9\:Y0 \14\:Y0) resistor r=165.202 c=0 +rg648 (\14\:Y0 \15\:Y0) resistor r=91.5933 c=0 +rg649 (\15\:Y0 \16\:Y0) resistor r=62.0099 c=0 +rg650 (\10\:Y0 \17\:Y0) resistor r=165.41 c=0 +rg651 (\17\:Y0 \18\:Y0) resistor r=91.5933 c=0 +rg652 (\18\:Y0 \19\:Y0) resistor r=62.0099 c=0 +rg653 (\11\:Y0 \20\:Y0) resistor r=165.618 c=0 +rg654 (\20\:Y0 \21\:Y0) resistor r=91.5933 c=0 +rg655 (\21\:Y0 \22\:Y0) resistor r=62.0099 c=0 +rg656 (\13\:Y0 \23\:Y0) resistor r=91.5933 c=0 +I25\|MP0 (\7\:I25\|net013 \20\:Y3 \66\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP0 (\7\:I22\|net013 \20\:Y2 \137\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP2 (\13\:net0127 \7\:I14\|net013 \125\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP2 (\21\:net0115 \5\:I17\|net013 \60\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MP1 (\64\:vdd! \14\:X0 \7\:I25\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP1 (\129\:vdd! \18\:X0 \7\:I22\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP4 (\63\:vdd! \22\:net075 \4\:I8\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP4 (\62\:vdd! \22\:net47 \4\:I7\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP1 (\4\:I14\|net013 \22\:X1 \141\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP0 (\4\:I17\|net013 \22\:Y1 \131\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MP2 (\67\:vdd! \3\:I25\|net013 \12\:net075 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP2 (\142\:vdd! \3\:I22\|net013 \12\:net47 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP1 (I8\|I1\|net8 \13\:net44 \1\:Z3 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP1 (I7\|I1\|net8 \13\:net32 \1\:Z2 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP0 (\132\:vdd! \16\:Y0 \4\:I14\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP1 (\124\:vdd! \10\:X0 \4\:I17\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP0 (\65\:vdd! I8\|I1\|Ai I8\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP0 (\128\:vdd! I7\|I1\|Ai I7\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP1 (\7\:I8\|I3\|net013 \17\:net44 \70\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP2 (I8\|I1\|net022 \5\:I8\|I1\|Bi \69\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP1 (\7\:I7\|I3\|net013 \17\:net32 \147\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP2 (I7\|I1\|net022 \5\:I7\|I1\|Bi \136\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP2 (\12\:net35 \4\:I6\|I3\|net013 \158\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP5 (\140\:vdd! \3\:net0127 \5\:I6\|I1\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP0 (\68\:vdd! \8\:net075 \7\:I8\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP3 (\7\:Z3 \16\:net075 I8\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP0 (\143\:vdd! \8\:net47 \7\:I7\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP3 (\7\:Z2 \16\:net47 I7\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP1 (\164\:vdd! \8\:net0127 \7\:I6\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP2 (\150\:vdd! \4\:I6\|I1\|Bi I6\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP0 (\73\:vdd! \13\:Y3 \7\:I24\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP0 (I6\|I1\|net8 \6\:I6\|I1\|Ai \163\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP0 (\165\:vdd! \13\:Y2 \7\:I23\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP1 (\5\:Z1 \5\:net0127 I6\|I1\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP2 (\13\:net095 \7\:I16\|net013 \172\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP0 (\7\:I6\|I3\|net013 \14\:net0115 \171\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP3 (I6\|I1\|net022 \16\:net0115 \6\:Z1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP5 (I8\|I1\|Bi \15\:net44 \72\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP2 (\71\:vdd! \3\:I8\|I3\|net013 \13\:net5 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP5 (I7\|I1\|Bi \15\:net32 \146\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP2 (\151\:vdd! \3\:I7\|I3\|net013 \13\:net45 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP4 (\4\:I6\|I1\|Ai net0115 \174\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP1 (\4\:I16\|net013 \6\:X1 \185\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP0 (\157\:vdd! \5\:I2\|I4\|Ai I2\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP1 (\7\:I24\|net013 \12\:X1 \74\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP0 (\175\:vdd! \16\:Y1 \4\:I16\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP1 (\7\:I23\|net013 \17\:X1 \166\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP2 (\19\:net34 \7\:I13\|net013 \190\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP1 (I11\|I4\|net8 \13\:net0100 \15\:I11\|net3 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP2 (\76\:vdd! \3\:I24\|net013 \16\:net078 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP2 (\176\:vdd! \3\:I23\|net013 \16\:net28 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP1 (I2\|I4\|net8 \13\:net29 \15\:I2\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP0 (\75\:vdd! \5\:I11\|I4\|Ai I11\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MP0 (\7\:I1\|net1 \6\:net095 \225\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP4 (I1\|I4\|Ai \8\:net095 \206\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MP1 (\215\:vdd! \8\:net34 \7\:I1\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP0 (I1\|I4\|net8 \5\:I1\|I4\|Ai \195\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP5 (\203\:vdd! \9\:net34 \2\:I1\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP1 (\20\:I1\|net3 \16\:net34 I1\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP1 (\4\:I13\|net013 \24\:X2 \202\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP0 (\201\:vdd! \19\:Y0 \4\:I13\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP3 (I1\|I4\|net022 \4\:net095 \15\:I1\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP2 (\184\:vdd! \5\:I1\|I4\|Bi I1\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MP1 (\12\:net26 \7\:I2\|net6 \214\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MP0 (\207\:vdd! \3\:I2\|net1 \12\:net26 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MP1 (\7\:I2\|net1 \15\:net29 \196\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MP0 (\186\:vdd! \8\:net28 \7\:I2\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP4 (\177\:vdd! \9\:net28 \2\:I2\|I4\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP5 (\251\:vdd! \9\:net35 I1\|I3\|Bi vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP2 (I1\|I3\|net022 \5\:I1\|I3\|Bi \239\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP3 (\6\:net32 \3\:I1\|net3 I1\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MP0 (I1\|net6 \5\:I1\|net3 \250\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MP1 (\249\:vdd! \5\:net35 I1\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP1 (I1\|I3\|net8 \4\:net35 \7\:net32 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP0 (\228\:vdd! I1\|I3\|Ai I1\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MP1 (\12\:net31 \7\:I1\|net6 \240\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MP0 (\234\:vdd! \3\:I1\|net1 \12\:net31 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP4 (\218\:vdd! \11\:I1\|net3 \6\:I1\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP5 (\5\:I3\|I3\|Bi \9\:net26 \241\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP5 (\221\:vdd! \9\:net45 I2\|I3\|Bi vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MP0 (I2\|net6 \5\:I2\|net3 \220\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MP1 (\219\:vdd! \5\:net45 I2\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP2 (\224\:vdd! \2\:I3\|I3\|Bi I3\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP2 (I2\|I3\|net022 \5\:I2\|I3\|Bi \213\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP3 (\6\:net44 \3\:I2\|net3 I2\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP1 (I2\|I3\|net8 \4\:net45 \7\:net44 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP0 (\200\:vdd! I2\|I3\|Ai I2\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP4 (\189\:vdd! \12\:I2\|net3 \6\:I2\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP5 (I2\|I4\|Bi \17\:net29 \180\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP2 (I2\|I4\|net022 \5\:I2\|I4\|Bi \170\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP3 (\20\:I2\|net3 \19\:net28 I2\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP0 (\84\:vdd! I11\|I3\|Ai I11\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MP1 (\12\:net1 \7\:I11\|net6 \85\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MP0 (\83\:vdd! \3\:I11\|net1 \12\:net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP4 (\82\:vdd! \11\:I11\|net3 \6\:I11\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MP1 (\7\:I11\|net1 \15\:net0100 \81\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP5 (I11\|I4\|Bi \17\:net0100 \80\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MP0 (\79\:vdd! \8\:net078 \7\:I11\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP2 (I11\|I4\|net022 \5\:I11\|I4\|Bi \78\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP4 (\77\:vdd! \9\:net078 \2\:I11\|I4\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP3 (\20\:I11\|net3 \19\:net078 I11\|I4\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP2 (\90\:vdd! \2\:I10\|I3\|Bi I10\|I3\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP5 (\5\:I10\|I3\|Bi \9\:net1 \91\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP5 (\88\:vdd! \10\:net5 I11\|I3\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP2 (I11\|I3\|net022 \5\:I11\|I3\|Bi \89\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP3 (\6\:Z4 \3\:I11\|net3 I11\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MP0 (I11\|net6 \5\:I11\|net3 \87\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MP1 (\86\:vdd! \6\:net5 I11\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP1 (I11\|I3\|net8 \5\:net5 \7\:Z4 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP4 (\4\:I0\|I3\|Ai \10\:I0\|net3 \275\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MP1 (\23\:net55 \7\:I0\|net1 \282\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MP0 (\276\:vdd! \3\:I0\|net6 \23\:net55 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP0 (I0\|I3\|net8 \6\:I0\|I3\|Ai \263\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP1 (\6\:net29 \7\:net31 I0\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MP1 (\5\:I0\|net6 \6\:net31 \271\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MP0 (\270\:vdd! \17\:I0\|net3 \5\:I0\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP3 (I0\|I3\|net022 \18\:I0\|net3 \7\:net29 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP2 (\254\:vdd! \5\:I0\|I3\|Bi I0\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP5 (\3\:I0\|I3\|Bi \9\:net31 \269\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MP0 (\3\:I3\|net1 \18\:net087 \277\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MP1 (\264\:vdd! \12\:net54 \3\:I3\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MP1 (\13\:net21 \7\:I3\|net1 \255\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MP0 (\248\:vdd! \3\:I3\|net6 \13\:net21 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MP1 (\5\:I3\|net6 \6\:net26 \243\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MP0 (\242\:vdd! \17\:I3\|net3 \5\:I3\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP3 (I0\|I4\|net022 \6\:net38 I0\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP2 (\3\:net087 \7\:I21\|net013 \287\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP4 (I0\|I4\|Ai \17\:net38 \315\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP2 (\294\:vdd! \4\:I0\|I4\|Bi I0\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MP0 (\3\:I0\|net1 \18\:net38 \301\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP4 (I3\|I4\|Ai \17\:net087 \286\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP5 (\284\:vdd! \11\:net39 \7\:I0\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MP1 (\285\:vdd! \6\:net39 \3\:I0\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP1 (\317\:vdd! \3\:X2 \4\:I18\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP0 (I0\|I4\|net8 \5\:I0\|I4\|Ai \306\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP0 (\4\:I21\|net013 \10\:Y2 \295\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP1 (\4\:I0\|net3 \8\:net39 I0\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP1 (\291\:vdd! \17\:X2 \4\:I21\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP2 (\5\:net38 \7\:I18\|net013 \316\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP0 (I10\|I3\|net8 \6\:I10\|I3\|Ai \94\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP0 (I3\|I3\|net8 \6\:I3\|I3\|Ai \233\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP1 (\6\:Z5 \7\:net1 I10\|I3\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MP1 (\5\:I10\|net6 \6\:net1 \93\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP1 (\6\:net0100 \7\:net26 I3\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MP0 (\92\:vdd! \17\:I10\|net3 \5\:I10\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP3 (I10\|I3\|net022 \18\:I10\|net3 \7\:Z5 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP3 (I3\|I3\|net022 \18\:I3\|net3 \7\:net0100 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP5 (\99\:vdd! \17\:net17 \7\:I10\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP5 (\258\:vdd! \17\:net54 \7\:I3\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MP1 (\98\:vdd! \12\:net17 \3\:I10\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP4 (\4\:I10\|I3\|Ai \10\:I10\|net3 \97\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP4 (\4\:I3\|I3\|Ai \10\:I3\|net3 \247\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MP1 (\14\:net15 \7\:I10\|net1 \96\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MP0 (\95\:vdd! \3\:I10\|net6 \14\:net15 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP3 (I10\|I4\|net022 \6\:net8 I10\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP3 (I3\|I4\|net022 \6\:net087 I3\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP4 (\4\:I10\|I4\|Ai \17\:net8 \102\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP2 (\101\:vdd! \4\:I10\|I4\|Bi I10\|I4\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP2 (\268\:vdd! \4\:I3\|I4\|Bi I3\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MP0 (\3\:I10\|net1 \18\:net8 \100\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP0 (\4\:I26\|net013 \10\:Y3 \106\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP1 (\104\:vdd! \9\:X2 \4\:I26\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP0 (I10\|I4\|net8 \2\:I10\|I4\|Ai \105\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP0 (I3\|I4\|net8 \5\:I3\|I4\|Ai \281\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP1 (\4\:I10\|net3 \14\:net17 I10\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP1 (\4\:I3\|net3 \14\:net54 I3\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP2 (\3\:net8 \7\:I26\|net013 \103\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MP1 (\5\:I4\|net6 \7\:net21 \309\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MP0 (\308\:vdd! \17\:I4\|net3 \5\:I4\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP4 (\320\:vdd! \19\:net55 \4\:I5\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP2 (\3\:net39 \7\:I12\|net013 \335\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP5 (\5\:I4\|I3\|Bi \10\:net21 \307\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP0 (\4\:I18\|net013 \9\:Y1 \325\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP0 (\348\:vdd! \8\:net55 \7\:I5\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP3 (\7\:net54 \13\:net55 I5\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MP1 (\15\:net16 \7\:I4\|net1 \321\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP1 (I5\|I1\|net8 \7\:net093 net54 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MP0 (\314\:vdd! \3\:I4\|net6 \15\:net16 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP1 (\4\:I12\|net013 \23\:X3 \347\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP0 (\330\:vdd! I5\|I1\|Ai I5\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP0 (\336\:vdd! \22\:Y0 \4\:I12\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP4 (I4\|I4\|Ai \14\:net090 \353\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP5 (I5\|I1\|Bi \9\:net093 \351\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP2 (\357\:vdd! \3\:I5\|I3\|net013 \2\:net19 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MP0 (\3\:I4\|net1 \16\:net090 \341\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP1 (\7\:I5\|I3\|net013 \11\:net093 \352\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP2 (I5\|I1\|net022 \5\:I5\|I1\|Bi \340\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MP1 (\331\:vdd! \10\:net19 \3\:I4\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP1 (\4\:I20\|net013 \12\:X3 \360\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP0 (\4\:I15\|net013 \12\:Y0 \367\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP1 (\4\:I19\|net013 \15\:X3 \369\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP0 (\355\:vdd! \3\:Y2 \4\:I20\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP1 (\363\:vdd! \4\:X0 \4\:I15\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP0 (\368\:vdd! \3\:Y1 \4\:I19\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP2 (\5\:net090 \7\:I20\|net013 \354\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP2 (\1\:Z0 \5\:I15\|net013 \359\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP2 (\3\:net093 \7\:I19\|net013 \364\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP4 (\4\:I4\|I3\|Ai \10\:I4\|net3 \313\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP0 (I4\|I3\|net8 \6\:I4\|I3\|Ai \300\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP1 (\8\:net17 \8\:net21 I4\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP3 (I4\|I3\|net022 \18\:I4\|net3 \9\:net17 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP2 (\290\:vdd! \2\:I4\|I3\|Bi I4\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MP1 (\115\:vdd! \5\:net16 \3\:I9\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP4 (\4\:I9\|I3\|Ai \10\:I9\|net3 \114\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MP1 (\3\:Z7 \7\:I9\|net1 \113\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MP0 (\112\:vdd! \3\:I9\|net6 \3\:Z7 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP0 (I9\|I3\|net8 \6\:I9\|I3\|Ai \111\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP1 (\6\:Z6 \8\:net15 I9\|I3\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MP1 (\5\:I9\|net6 \7\:net15 \110\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MP0 (\109\:vdd! \17\:I9\|net3 \5\:I9\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP3 (I9\|I3\|net022 \18\:I9\|net3 \7\:Z6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP2 (\107\:vdd! \2\:I9\|I3\|Bi I9\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP5 (\5\:I9\|I3\|Bi \10\:net15 \108\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP3 (I4\|I4\|net022 \6\:net090 I4\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP3 (I9\|I4\|net022 \6\:net13 I9\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP4 (I9\|I4\|Ai \14\:net13 \119\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP2 (\334\:vdd! \4\:I4\|I4\|Bi I4\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP2 (\118\:vdd! \4\:I9\|I4\|Bi I9\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MP0 (\3\:I9\|net1 \16\:net13 \117\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP5 (\324\:vdd! \15\:net19 \7\:I4\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP5 (\116\:vdd! \10\:net16 \7\:I9\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP1 (\4\:I27\|net013 \9\:X3 \58\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP0 (\121\:vdd! \3\:Y3 \4\:I27\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP0 (I4\|I4\|net8 \5\:I4\|I4\|Ai \346\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP0 (I9\|I4\|net8 \5\:I9\|I4\|Ai \122\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP1 (\4\:I4\|net3 \12\:net19 I4\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP1 (\4\:I9\|net3 \7\:net16 I9\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP2 (\5\:net13 \7\:I27\|net013 \120\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN0 (I25\|net9 \18\:Y3 \21\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN0 (I22\|net9 \18\:Y2 \317\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN2 (\11\:net0127 \5\:I14\|net013 \287\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN2 (\23\:net0115 \7\:I17\|net013 \319\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN1 (\5\:I25\|net013 \15\:X0 I25\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN1 (\5\:I22\|net013 \19\:X0 I22\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN4 (\293\:gnd! \21\:net075 \6\:I8\|I1\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN4 (\1\:gnd! \21\:net47 \6\:I7\|I1\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN1 (I14\|net9 \19\:X1 \3\:I14\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN0 (I17\|net9 \24\:Y1 \3\:I17\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN2 (\23\:gnd! \4\:I25\|net013 \10\:net075 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN2 (\315\:gnd! \4\:I22\|net013 \10\:net47 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN2 (I8\|I1\|net17 \13\:net075 \6\:Z3 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN2 (I7\|I1\|net17 \13\:net47 \6\:Z2 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN0 (\280\:gnd! \14\:Y0 I14\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN1 (\318\:gnd! \9\:X0 I17\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN3 (\290\:gnd! \12\:net44 I8\|I1\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN3 (\22\:gnd! \12\:net32 I7\|I1\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN1 (I8\|I3\|net9 \19\:net44 \24\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN1 (I8\|I1\|net32 \7\:I8\|I1\|Bi \282\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN1 (I7\|I3\|net9 \19\:net32 \309\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN1 (I7\|I1\|net32 \7\:I7\|I1\|Bi \25\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN2 (\10\:net35 I6\|I3\|net013 \270\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN5 (\312\:gnd! \7\:net0127 \7\:I6\|I1\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN0 (\5\:I8\|I3\|net013 \9\:net075 I8\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN0 (\5\:Z3 \3\:I8\|I1\|Ai I8\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN0 (\5\:I7\|I3\|net013 \9\:net47 I7\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN0 (\5\:Z2 \3\:I7\|I1\|Ai I7\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN1 (\262\:gnd! \10\:net0127 I6\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN1 (\310\:gnd! \3\:I6\|I1\|Bi I6\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN0 (\5\:I24\|net013 \14\:Y3 I24\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN3 (I6\|I1\|net17 \6\:net0127 \304\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN0 (\5\:I23\|net013 \14\:Y2 I23\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN2 (\7\:Z1 \19\:net0115 I6\|I1\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN2 (\11\:net095 \5\:I16\|net013 \253\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN0 (I6\|I3\|net9 \12\:net0115 \5\:I6\|I3\|net013 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN0 (I6\|I1\|net32 \5\:I6\|I1\|Ai \1\:Z1 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN5 (\3\:I8\|I1\|Bi \16\:net44 \274\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN2 (\26\:gnd! \4\:I8\|I3\|net013 \14\:net5 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN5 (\3\:I7\|I1\|Bi \16\:net32 \27\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN2 (\307\:gnd! \4\:I7\|I3\|net013 \14\:net45 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN4 (\3\:I6\|I1\|Ai \4\:net0115 \300\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN1 (I16\|net9 \4\:X1 \3\:I16\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN3 (\29\:gnd! \12\:net29 I2\|I4\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN1 (I24\|net9 \10\:X1 \28\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN0 (\246\:gnd! \17\:Y1 I16\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN1 (I23\|net9 \15\:X1 \302\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN2 (\17\:net34 \5\:I13\|net013 \240\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN2 (I11\|I4\|net17 \17\:net078 \18\:I11\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN2 (\30\:gnd! \4\:I24\|net013 \14\:net078 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN2 (\299\:gnd! \4\:I23\|net013 \15\:net28 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN2 (I2\|I4\|net17 \17\:net28 \18\:I2\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN3 (\264\:gnd! \12\:net0100 I11\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN1 (\19\:I1\|net3 \4\:I1\|I4\|Bi I1\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MN1 (I2\|I0\|net9 \19\:net29 \292\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MN0 (\5\:I2\|net1 \11\:net28 I2\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN1 (I13\|net9 \22\:X2 \3\:I13\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN0 (\232\:gnd! \17\:Y0 I13\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN3 (I1\|I4\|net17 \14\:net34 \18\:I1\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN4 (\296\:gnd! \5\:net28 I2\|I4\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN2 (\297\:gnd! \3\:net095 I1\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN5 (\3\:I11\|I4\|Bi \18\:net0100 \247\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MN0 (\5\:I11\|net1 \11\:net078 I11\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN5 (\3\:I2\|I4\|Bi \18\:net29 \33\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN1 (I11\|I4\|net32 \7\:I11\|I4\|Bi \249\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN4 (\31\:gnd! \5\:net078 I11\|I4\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN1 (I2\|I4\|net32 \7\:I2\|I4\|Bi \32\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN0 (\19\:I11\|net3 \4\:I11\|I4\|Ai I11\|I4\|net32 0) nmos1 \ + w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN0 (\19\:I2\|net3 \4\:I2\|I4\|Ai I2\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MN0 (I1\|I0\|net9 \10\:net095 \218\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN4 (\3\:I1\|I4\|Ai \9\:net095 \283\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MN1 (I2\|I1\|net9 \5\:I2\|net6 \277\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MN1 (\5\:I1\|net1 \11\:net34 I1\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MN0 (\10\:net26 \4\:I2\|net1 I2\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN0 (I1\|I4\|net32 \7\:I1\|I4\|Ai \286\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN5 (\227\:gnd! \5\:net34 I1\|I4\|Bi 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN2 (I2\|I3\|net17 I2\|net3 net44 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN3 (\220\:gnd! \4\:net5 I11\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MN1 (I11\|I1\|net9 \5\:I11\|net6 \37\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN3 (\36\:gnd! \3\:net45 I2\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MN0 (\10\:net1 \4\:I11\|net1 I11\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN4 (\234\:gnd! \10\:I11\|net3 \5\:I11\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN4 (\35\:gnd! \11\:I2\|net3 \5\:I2\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MN1 (I11\|I0\|net9 \19\:net0100 \34\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MN1 (\203\:gnd! \7\:net35 I1\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN2 (I1\|I3\|net17 I1\|net3 net32 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN5 (\259\:gnd! \8\:net45 \4\:I2\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN3 (\265\:gnd! \3\:net35 I1\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MN1 (I1\|I1\|net9 \5\:I1\|net6 \210\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MN0 (I2\|I2\|net9 \6\:I2\|net3 \3\:I2\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MN0 (\10\:net31 \4\:I1\|net1 I1\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN4 (\275\:gnd! \10\:I1\|net3 \5\:I1\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MN1 (\268\:gnd! \7\:net45 I2\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN5 (\39\:gnd! \9\:net5 \4\:I11\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN1 (I11\|I3\|net32 \6\:I11\|I3\|Bi \206\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN1 (I2\|I3\|net32 \6\:I2\|I3\|Bi \40\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN0 (\4\:Z4 \3\:I11\|I3\|Ai I11\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN0 (\4\:net44 \3\:I2\|I3\|Ai I2\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MN0 (I11\|I2\|net9 \6\:I11\|net3 \3\:I11\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MN1 (\38\:gnd! \8\:net5 I11\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN2 (I11\|I3\|net17 I11\|net3 \2\:Z4 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN1 (\198\:gnd! \3\:I10\|I3\|Bi I10\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN5 (\6\:I10\|I3\|Bi \3\:net1 \44\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN1 (\45\:gnd! \3\:I3\|I3\|Bi I3\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN5 (\6\:I3\|I3\|Bi \3\:net26 \243\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN5 (\196\:gnd! \8\:net35 \4\:I1\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN1 (I1\|I3\|net32 \6\:I1\|I3\|Bi \251\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN0 (\4\:net32 \3\:I1\|I3\|Ai I1\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MN0 (I1\|I2\|net9 \6\:I1\|net3 \3\:I1\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MN1 (I0\|I2\|net9 \4\:net31 \185\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MN1 (\224\:gnd! \4\:I3\|net6 I3\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MN0 (\7\:I0\|net6 \16\:I0\|net3 I0\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN0 (I0\|I3\|net32 \5\:I0\|I3\|Ai net29 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MN1 (I3\|I2\|net9 \4\:net26 \230\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN1 (\237\:gnd! \6\:I0\|I3\|Bi I0\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN5 (\4\:I0\|I3\|Bi \3\:net31 \190\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MN0 (\7\:I3\|net6 \16\:I3\|net3 I3\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MN0 (I3\|I0\|net9 \13\:net087 I3\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN4 (\3\:I0\|I3\|Ai \12\:I0\|net3 \208\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MN0 (I0\|I1\|net9 \5\:I0\|net1 \22\:net55 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MN1 (\215\:gnd! \16\:net54 I3\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MN1 (\179\:gnd! \4\:I0\|net6 I0\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN3 (I0\|I3\|net17 \8\:net31 \221\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MN0 (I3\|I1\|net9 \5\:I3\|net1 \11\:net21 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN2 (\4\:net29 \20\:I0\|net3 I0\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN0 (I0\|I4\|net32 \4\:I0\|I4\|Ai \5\:I0\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN2 (net087 \5\:I21\|net013 \183\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN4 (\2\:I0\|I4\|Ai \19\:net38 \165\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN1 (\188\:gnd! \3\:I0\|I4\|Bi I0\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MN0 (I0\|I0\|net9 \13\:net38 I0\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN4 (\2\:I3\|I4\|Ai \19\:net087 \194\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN5 (\201\:gnd! \12\:net39 \5\:I0\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MN1 (\172\:gnd! \10\:net39 I0\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN1 (\151\:gnd! \4\:X2 I18\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN3 (I0\|I4\|net17 \9\:net39 \169\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN0 (I21\|net9 \8\:Y2 \3\:I21\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN2 (\7\:I0\|net3 \8\:net38 I0\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN1 (\176\:gnd! \18\:X2 I21\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN2 (\3\:net38 \5\:I18\|net013 \159\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN3 (I10\|I3\|net17 \8\:net1 \191\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN3 (I3\|I3\|net17 \8\:net26 \55\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN2 (\4\:Z5 \20\:I10\|net3 I10\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MN1 (I10\|I2\|net9 \4\:net1 \48\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN2 (\4\:net0100 \20\:I3\|net3 I3\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MN0 (\7\:I10\|net6 \16\:I10\|net3 I10\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN0 (I10\|I3\|net32 \5\:I10\|I3\|Ai \1\:Z5 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN0 (I3\|I3\|net32 \5\:I3\|I3\|Ai net0100 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN5 (\167\:gnd! \18\:net17 \5\:I10\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN5 (\61\:gnd! \18\:net54 \5\:I3\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MN1 (\54\:gnd! \16\:net17 I10\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN4 (\3\:I10\|I3\|Ai \12\:I10\|net3 \181\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN4 (\3\:I3\|I3\|Ai \12\:I3\|net3 \56\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MN0 (I10\|I1\|net9 \5\:I10\|net1 \13\:net15 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MN1 (\50\:gnd! \4\:I10\|net6 I10\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN0 (I10\|I4\|net32 I10\|I4\|Ai \5\:I10\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN0 (I3\|I4\|net32 \4\:I3\|I4\|Ai \5\:I3\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN4 (\5\:I10\|I4\|Ai \19\:net8 \60\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN1 (\161\:gnd! \3\:I10\|I4\|Bi I10\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN1 (\62\:gnd! \3\:I3\|I4\|Bi I3\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MN0 (I10\|I0\|net9 \13\:net8 I10\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN0 (I26\|net9 \8\:Y3 \3\:I26\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN1 (\67\:gnd! \10\:X2 I26\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN3 (I10\|I4\|net17 \15\:net17 \146\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN3 (I3\|I4\|net17 \15\:net54 \72\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN2 (\7\:I10\|net3 \8\:net8 I10\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN2 (\7\:I3\|net3 \8\:net087 I3\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN2 (net8 \5\:I26\|net013 \65\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MN1 (I4\|I2\|net9 \5\:net21 \148\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MN0 (\7\:I4\|net6 \16\:I4\|net3 I4\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN4 (\156\:gnd! \18\:net55 \6\:I5\|I1\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN2 (net39 \5\:I12\|net013 \144\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN5 (\6\:I4\|I3\|Bi \4\:net21 \163\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN0 (I18\|net9 \11\:Y1 \3\:I18\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN0 (\5\:I5\|I3\|net013 \9\:net55 I5\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN0 (\5\:net54 \3\:I5\|I1\|Ai I5\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MN0 (I4\|I1\|net9 \5\:I4\|net1 \14\:net16 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN2 (I5\|I1\|net17 \10\:net55 \6\:net54 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MN1 (\142\:gnd! \4\:I4\|net6 I4\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN1 (I12\|net9 \21\:X3 \3\:I12\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN3 (\154\:gnd! \6\:net093 I5\|I1\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN0 (\139\:gnd! \20\:Y0 I12\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN4 (\2\:I4\|I4\|Ai \17\:net090 \119\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN5 (\3\:I5\|I1\|Bi \10\:net093 \125\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN2 (\122\:gnd! \4\:I5\|I3\|net013 \3\:net19 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MN0 (I4\|I0\|net9 \9\:net090 I4\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN1 (I5\|I3\|net9 \13\:net093 \130\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN1 (I5\|I1\|net32 \7\:I5\|I1\|Bi \128\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MN1 (\136\:gnd! \14\:net19 I4\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN1 (I20\|net9 \10\:X3 \3\:I20\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN0 (I15\|net9 \23\:Y0 \3\:I15\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN1 (I19\|net9 \13\:X3 \3\:I19\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN0 (\104\:gnd! \4\:Y2 I20\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN1 (\110\:gnd! \3\:X0 I15\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN0 (\107\:gnd! \4\:Y1 I19\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN2 (\3\:net090 \5\:I20\|net013 \112\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN2 (\3\:Z0 \7\:I15\|net013 \117\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN2 (net093 \5\:I19\|net013 \114\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN2 (\6\:net17 \20\:I4\|net3 I4\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN2 (\4\:Z6 \20\:I9\|net3 I9\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MN1 (I9\|I2\|net9 \5\:net15 \75\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MN0 (\7\:I9\|net6 \16\:I9\|net3 I9\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN0 (I4\|I3\|net32 \5\:I4\|I3\|Ai \3\:net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN0 (I9\|I3\|net32 \5\:I9\|I3\|Ai \2\:Z6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN1 (\73\:gnd! \3\:I4\|I3\|Bi I4\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN1 (\134\:gnd! \3\:I9\|I3\|Bi I9\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN5 (\6\:I9\|I3\|Bi \4\:net15 \71\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MN1 (\79\:gnd! \9\:net16 I9\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN4 (\3\:I4\|I3\|Ai \12\:I4\|net3 \83\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN4 (\3\:I9\|I3\|Ai \12\:I9\|net3 \116\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MN0 (I9\|I1\|net9 \5\:I9\|net1 \2\:Z7 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MN1 (\77\:gnd! \4\:I9\|net6 I9\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN3 (I4\|I3\|net17 \9\:net21 \80\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN3 (I9\|I3\|net17 \9\:net15 \124\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN0 (I4\|I4\|net32 \4\:I4\|I4\|Ai \5\:I4\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN0 (I9\|I4\|net32 \4\:I9\|I4\|Ai \5\:I9\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN4 (\2\:I9\|I4\|Ai \17\:net13 \86\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN1 (\87\:gnd! \3\:I4\|I4\|Bi I4\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN1 (\101\:gnd! \3\:I9\|I4\|Bi I9\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MN0 (I9\|I0\|net9 \9\:net13 I9\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN5 (\84\:gnd! \16\:net19 \5\:I4\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN5 (\109\:gnd! \11\:net16 \5\:I9\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN1 (I27\|net9 \7\:X3 \3\:I27\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN0 (\92\:gnd! \4\:Y3 I27\|net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN3 (I4\|I4\|net17 \13\:net19 \96\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN3 (I9\|I4\|net17 \8\:net16 \95\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN2 (\7\:I4\|net3 \8\:net090 I4\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN2 (\7\:I9\|net3 \8\:net13 I9\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN2 (\3\:net13 \5\:I27\|net013 \90\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..182cbb664154d7f1a868cf96107e5bf24cd91cc9 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/4X4_multiplier/av_extracted multiplier_low_4X4_multiplier_av_extracted +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..56a2b0b16ee0d2f5ea934dd3046c90546609d920 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 2:13:06 AM, Thur May 27, 2021 (process id: 98043). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre1_6429_1" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x66235e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..7e6e01765ba5d5836c86945177eaeaa81a015711 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,2942 @@ +// Generated for: spectre +// Generated on: May 27 02:13:04 2021 +// Design library name: multiplier_low +// Design cell name: 4X4_multiplier +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/4x4_mul_11100001.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: 4X4_multiplier +// View name: av_extracted +rd1 (\8\:net19 \5\:net19) resistor r=8.0091 c=0 +rd2 (\12\:net16 \3\:net16) resistor r=5.8364 c=0 +rd3 (\24\:X3 \25\:X3) resistor r=3.1579 c=0 +rd4 (\25\:X3 \26\:X3) resistor r=0.5024 c=0 +rd5 (\26\:X3 \17\:X3) resistor r=5.0228 c=0 +rd6 (\17\:X3 \16\:X3) resistor r=4.8777 c=0 +rd7 (\25\:X3 \18\:X3) resistor r=0.04452 c=0 +rd8 (\26\:X3 X3) resistor r=1.8728 c=0 +rd9 (\20\:net17 net17) resistor r=7.2124 c=0 +rd10 (\20\:net54 \8\:net54) resistor r=8.6175 c=0 +rd11 (\12\:net15 net15) resistor r=7.3099 c=0 +rd12 (\14\:net21 net21) resistor r=5.4346 c=0 +rd13 (\8\:net0100 \11\:net0100) resistor r=4.2422 c=0 +rd14 (\8\:net29 \11\:net29) resistor r=4.6625 c=0 +rd15 (X2 \25\:X2) resistor r=2.0091 c=0 +rd16 (\25\:X2 \6\:X2) resistor r=4.3508 c=0 +rd17 (\25\:X2 \26\:X2) resistor r=4.9199 c=0 +rd18 (\26\:X2 \14\:X2) resistor r=9.0609 c=0 +rd19 (\25\:X2 \21\:X2) resistor r=4.2095 c=0 +rd20 (\26\:X2 \15\:X2) resistor r=3.9144 c=0 +rd21 (\11\:net45 \10\:net45) resistor r=3.8783 c=0 +rd22 (\11\:net5 \3\:net5) resistor r=4.1 c=0 +rd23 (\11\:net44 \8\:net44) resistor r=2.3746 c=0 +rd24 (\11\:net32 \8\:net32) resistor r=2.3184 c=0 +rd25 (\24\:X1 \3\:X1) resistor r=3.2855 c=0 +rd26 (\3\:X1 \25\:X1) resistor r=0.05722 c=0 +rd27 (\25\:X1 X1) resistor r=2.0116 c=0 +rd28 (\25\:X1 \26\:X1) resistor r=4.9159 c=0 +rd29 (\26\:X1 \9\:X1) resistor r=5.0544 c=0 +rd30 (\26\:X1 \18\:X1) resistor r=0.03024 c=0 +rd31 (X0 \25\:X0) resistor r=4.3738 c=0 +rd32 (\25\:X0 \11\:X0) resistor r=1.0865 c=0 +rd33 (\25\:X0 \24\:X0) resistor r=0.8508 c=0 +rd34 (\24\:X0 \22\:X0) resistor r=1.5696 c=0 +rd35 (\22\:X0 \23\:X0) resistor r=4.8116 c=0 +re1 (\16\:X3 \1\:X3) resistor r=4.4678 c=0 +re2 (\17\:X3 \3\:X3) resistor r=4.4712 c=0 +re3 (\5\:X3 \18\:X3) resistor r=4 c=0 +re4 (\4\:net19 \5\:net19) resistor r=0.005495 c=0 +re5 (net19 \4\:net19) resistor r=2 c=0 +re6 (\18\:net090 \2\:net090) resistor r=3.1152 c=0 +re7 (\18\:net13 \2\:net13) resistor r=3.1152 c=0 +re8 (\19\:net090 \4\:net090) resistor r=4.9649 c=0 +re9 (\4\:net13 \19\:net13) resistor r=4.9666 c=0 +re10 (\5\:net093 \2\:net093) resistor r=3.1619 c=0 +re11 (\6\:net19 \8\:net19) resistor r=2 c=0 +re12 (\3\:net16 net16) resistor r=2 c=0 +re13 (Z7 \1\:Z7) resistor r=6.021 c=0 +re14 (\8\:net54 \9\:net54) resistor r=0.004082 c=0 +re15 (\3\:net54 \9\:net54) resistor r=2 c=0 +re16 (\12\:net16 \13\:net16) resistor r=4.0411 c=0 +re17 (\6\:net55 \4\:net55) resistor r=5.3786 c=0 +re18 (\19\:X3 \24\:X3) resistor r=4 c=0 +re19 (\13\:I4\|net3 \14\:I4\|net3) resistor r=2.6847 c=0 +re20 (\14\:I4\|net3 \6\:I4\|net3) resistor r=0.9844 c=0 +re21 (\8\:I4\|net3 \14\:I4\|net3) resistor r=2 c=0 +re22 (\13\:I9\|net3 \14\:I9\|net3) resistor r=2.6847 c=0 +re23 (\14\:I9\|net3 \6\:I9\|net3) resistor r=0.9844 c=0 +re24 (\8\:I9\|net3 \14\:I9\|net3) resistor r=2 c=0 +re25 (net21 \2\:net21) resistor r=4 c=0 +re26 (net15 \2\:net15) resistor r=0.001087 c=0 +re27 (net17 \2\:net17) resistor r=0.004082 c=0 +re28 (Z6 \1\:Z6) resistor r=3.0317 c=0 +re29 (\15\:net55 \20\:net55) resistor r=4.7641 c=0 +re30 (\5\:X2 \6\:X2) resistor r=2 c=0 +re31 (\11\:X2 \14\:X2) resistor r=2 c=0 +re32 (\15\:X2 \12\:X2) resistor r=2 c=0 +re33 (\10\:net38 \2\:net38) resistor r=3.1152 c=0 +re34 (\4\:net38 \11\:net38) resistor r=5.0824 c=0 +re35 (\9\:net8 \5\:net8) resistor r=5.1152 c=0 +re36 (\11\:net8 \2\:net8) resistor r=5.0534 c=0 +re37 (\13\:net39 \2\:net39) resistor r=5.7166 c=0 +re38 (\10\:net087 \5\:net087) resistor r=3.1152 c=0 +re39 (\11\:net087 \2\:net087) resistor r=5.0993 c=0 +re40 (\21\:net55 net55) resistor r=8.1859 c=0 +re41 (\20\:net17 \19\:net17) resistor r=3.0466 c=0 +re42 (\20\:net54 \19\:net54) resistor r=3.0379 c=0 +re43 (\11\:net15 \12\:net15) resistor r=4 c=0 +re44 (\14\:net21 \12\:net21) resistor r=4.0011 c=0 +re45 (\14\:I0\|net3 \15\:I0\|net3) resistor r=0.6847 c=0 +re46 (\15\:I0\|net3 \6\:I0\|net3) resistor r=0.9844 c=0 +re47 (\8\:I0\|net3 \15\:I0\|net3) resistor r=2 c=0 +re48 (\13\:I10\|net3 \14\:I10\|net3) resistor r=2.6847 c=0 +re49 (\14\:I10\|net3 \6\:I10\|net3) resistor r=0.9844 c=0 +re50 (\8\:I10\|net3 \14\:I10\|net3) resistor r=2 c=0 +re51 (\14\:I3\|net3 \15\:I3\|net3) resistor r=0.6847 c=0 +re52 (\15\:I3\|net3 \6\:I3\|net3) resistor r=0.9844 c=0 +re53 (\8\:I3\|net3 \15\:I3\|net3) resistor r=2 c=0 +re54 (Z5 \2\:Z5) resistor r=3.1416 c=0 +re55 (\8\:net0100 \2\:net0100) resistor r=5.4502 c=0 +re56 (\8\:net29 \2\:net29) resistor r=5.86 c=0 +re57 (Z4 \1\:Z4) resistor r=3.0829 c=0 +re58 (\11\:net31 \2\:net31) resistor r=5.438 c=0 +re59 (\3\:net5 \2\:net5) resistor r=2.422 c=0 +re60 (\10\:net45 \2\:net45) resistor r=2.4508 c=0 +re61 (\11\:net1 \2\:net1) resistor r=6.1255 c=0 +re62 (\11\:net26 \2\:net26) resistor r=6.1929 c=0 +re63 (\10\:net0100 \11\:net0100) resistor r=2 c=0 +re64 (\13\:I1\|net3 \14\:I1\|net3) resistor r=2.9844 c=0 +re65 (\14\:I1\|net3 \7\:I1\|net3) resistor r=0.6847 c=0 +re66 (\12\:I1\|net3 \14\:I1\|net3) resistor r=2 c=0 +re67 (\10\:net29 \11\:net29) resistor r=2 c=0 +re68 (\19\:X2 \21\:X2) resistor r=4.0089 c=0 +re69 (\3\:net34 \13\:net34) resistor r=3.1152 c=0 +re70 (\13\:I11\|net3 \14\:I11\|net3) resistor r=2.9844 c=0 +re71 (\14\:I11\|net3 \7\:I11\|net3) resistor r=0.6847 c=0 +re72 (\12\:I11\|net3 \14\:I11\|net3) resistor r=2 c=0 +re73 (\13\:I2\|net3 \14\:I2\|net3) resistor r=2.9844 c=0 +re74 (\14\:I2\|net3 \7\:I2\|net3) resistor r=0.6847 c=0 +re75 (\9\:I2\|net3 \14\:I2\|net3) resistor r=2 c=0 +re76 (\3\:net078 \13\:net078) resistor r=3.1152 c=0 +re77 (\3\:net28 \13\:net28) resistor r=3.1152 c=0 +re78 (\18\:net34 \2\:net34) resistor r=6.3777 c=0 +re79 (\15\:net078 \2\:net078) resistor r=5.3259 c=0 +re80 (\14\:net28 \2\:net28) resistor r=5.1758 c=0 +re81 (\1\:X1 \3\:X1) resistor r=4.0933 c=0 +re82 (\8\:net44 \3\:net44) resistor r=8.0252 c=0 +re83 (\8\:X1 \9\:X1) resistor r=2.3735 c=0 +re84 (\14\:X1 \18\:X1) resistor r=2.5129 c=0 +re85 (\6\:net0115 \5\:net0115) resistor r=4.7641 c=0 +re86 (\8\:net32 \3\:net32) resistor r=9.1881 c=0 +re87 (\2\:net095 \12\:net095) resistor r=7.462 c=0 +re88 (\9\:net0115 \10\:net0115) resistor r=5.3786 c=0 +re89 (\12\:net5 \11\:net5) resistor r=4.4477 c=0 +re90 (\12\:net45 \11\:net45) resistor r=4.4706 c=0 +re91 (\11\:net44 \10\:net44) resistor r=2.7182 c=0 +re92 (\10\:net32 \11\:net32) resistor r=2.553 c=0 +re93 (\2\:net35 \11\:net35) resistor r=11.1009 c=0 +re94 (\6\:net075 \4\:net075) resistor r=5.3786 c=0 +re95 (\6\:net47 \4\:net47) resistor r=5.3786 c=0 +re96 (net075 \11\:net075) resistor r=2.6252 c=0 +re97 (\11\:net47 net47) resistor r=2.6218 c=0 +re98 (\23\:X1 \24\:X1) resistor r=4 c=0 +re99 (\11\:X0 \6\:X0) resistor r=2.0078 c=0 +re100 (\12\:net0127 net0127) resistor r=5.6983 c=0 +re101 (\22\:net0115 \20\:net0115) resistor r=7.1937 c=0 +re102 (\18\:net075 \23\:net075) resistor r=4.7641 c=0 +re103 (\18\:net47 \23\:net47) resistor r=4.7641 c=0 +re104 (\22\:X0 \21\:X0) resistor r=4.2267 c=0 +re105 (\23\:X0 \20\:X0) resistor r=4.2289 c=0 +re106 (\24\:X0 \5\:X0) resistor r=21.5123 c=0 +re107 (Z3 \3\:Z3) resistor r=3.8779 c=0 +re108 (Z2 \3\:Z2) resistor r=4.033 c=0 +re109 (Z1 \3\:Z1) resistor r=5.9155 c=0 +re110 (Y2 \21\:Y2) resistor r=1.1311 c=0 +re111 (\21\:Y2 \22\:Y2) resistor r=2.7111 c=0 +re112 (\22\:Y2 \23\:Y2) resistor r=10.4714 c=0 +re113 (\23\:Y2 \5\:Y2) resistor r=5.6954 c=0 +re114 (\21\:Y2 \17\:Y2) resistor r=1.078 c=0 +re115 (\22\:Y2 \15\:Y2) resistor r=3.023 c=0 +re116 (\23\:Y2 \6\:Y2) resistor r=3.1738 c=0 +re117 (Y3 \21\:Y3) resistor r=1.1311 c=0 +re118 (\21\:Y3 \22\:Y3) resistor r=2.8324 c=0 +re119 (\22\:Y3 \23\:Y3) resistor r=10.4206 c=0 +re120 (\23\:Y3 \5\:Y3) resistor r=5.6155 c=0 +re121 (\21\:Y3 \17\:Y3) resistor r=1.0707 c=0 +re122 (\22\:Y3 \15\:Y3) resistor r=3.0112 c=0 +re123 (\23\:Y3 \6\:Y3) resistor r=3.1534 c=0 +re124 (Z0 \2\:Z0) resistor r=20.9575 c=0 +rf1 (\1\:X3 \2\:X3) resistor r=0.01 c=0 +rf2 (\3\:X3 \4\:X3) resistor r=0.01 c=0 +rf4 (\5\:X3 \6\:X3) resistor r=0.01 c=0 +rf5 (\5\:Y3 \1\:Y3) resistor r=2.01 c=0 +rf6 (\5\:Y2 \1\:Y2) resistor r=2.01 c=0 +rf7 (\5\:X0 \1\:X0) resistor r=2.01 c=0 +rf9 (I27\|net013 \2\:I27\|net013) resistor r=0.2434 c=0 +rf10 (\2\:I27\|net013 \3\:I27\|net013) resistor r=0.3205 c=0 +rf11 (\2\:I27\|net013 \4\:I27\|net013) resistor r=0.5422 c=0 +rf12 (I20\|net013 \2\:I20\|net013) resistor r=0.2434 c=0 +rf13 (\2\:I20\|net013 \3\:I20\|net013) resistor r=0.3205 c=0 +rf14 (\2\:I20\|net013 \4\:I20\|net013) resistor r=0.5422 c=0 +rf15 (I15\|net013 \2\:I15\|net013) resistor r=0.2434 c=0 +rf16 (\2\:I15\|net013 \3\:I15\|net013) resistor r=0.3205 c=0 +rf17 (\2\:I15\|net013 \4\:I15\|net013) resistor r=0.5422 c=0 +rf18 (I19\|net013 \2\:I19\|net013) resistor r=0.2434 c=0 +rf19 (\2\:I19\|net013 \3\:I19\|net013) resistor r=0.3205 c=0 +rf20 (\2\:I19\|net013 \4\:I19\|net013) resistor r=0.5422 c=0 +rf21 (net090 \2\:net090) resistor r=2.0022 c=0 +rf22 (net13 \2\:net13) resistor r=2.0022 c=0 +rf23 (\3\:net13 \4\:net13) resistor r=0.2066 c=0 +rf24 (\4\:net13 \5\:net13) resistor r=0.6132 c=0 +rf25 (\3\:net090 \4\:net090) resistor r=0.2066 c=0 +rf26 (\4\:net090 \5\:net090) resistor r=0.6132 c=0 +rf27 (\1\:Z0 \2\:Z0) resistor r=0.6132 c=0 +rf28 (\2\:Z0 \3\:Z0) resistor r=0.2066 c=0 +rf29 (net093 \2\:net093) resistor r=0.2066 c=0 +rf30 (\2\:net093 \3\:net093) resistor r=0.6132 c=0 +rf31 (net19 \2\:net19) resistor r=0.285 c=0 +rf32 (net19 \3\:net19) resistor r=0.8307 c=0 +rf33 (I4\|net3 \2\:I4\|net3) resistor r=0.7396 c=0 +rf34 (\2\:I4\|net3 \3\:I4\|net3) resistor r=0.4087 c=0 +rf35 (\3\:I4\|net3 \4\:I4\|net3) resistor r=0.7213 c=0 +rf36 (\2\:I4\|net3 \5\:I4\|net3) resistor r=0.2896 c=0 +rf37 (\2\:I4\|net3 \6\:I4\|net3) resistor r=2.2056 c=0 +rf38 (\3\:I4\|net3 \7\:I4\|net3) resistor r=0.2841 c=0 +rf39 (I9\|net3 \2\:I9\|net3) resistor r=0.7396 c=0 +rf40 (\2\:I9\|net3 \3\:I9\|net3) resistor r=0.4087 c=0 +rf41 (\3\:I9\|net3 \4\:I9\|net3) resistor r=0.7213 c=0 +rf42 (\2\:I9\|net3 \5\:I9\|net3) resistor r=0.2896 c=0 +rf43 (\2\:I9\|net3 \6\:I9\|net3) resistor r=2.2056 c=0 +rf44 (\3\:I9\|net3 \7\:I9\|net3) resistor r=0.2841 c=0 +rf45 (I4\|I4\|Ai \2\:I4\|I4\|Ai) resistor r=0.84 c=0 +rf46 (I4\|I4\|Ai \3\:I4\|I4\|Ai) resistor r=0.2475 c=0 +rf47 (I9\|I4\|Ai \2\:I9\|I4\|Ai) resistor r=0.84 c=0 +rf48 (I9\|I4\|Ai \3\:I9\|I4\|Ai) resistor r=0.2475 c=0 +rf49 (\12\:net090 \18\:net090) resistor r=2.0267 c=0 +rf50 (\19\:net090 \15\:net090) resistor r=0.02222 c=0 +rf51 (\12\:net13 \18\:net13) resistor r=2.0267 c=0 +rf52 (\19\:net13 \15\:net13) resistor r=0.02222 c=0 +rf53 (\4\:net093 \5\:net093) resistor r=2.0111 c=0 +rf54 (I5\|I1\|Bi \2\:I5\|I1\|Bi) resistor r=0.3619 c=0 +rf55 (\2\:I5\|I1\|Bi \3\:I5\|I1\|Bi) resistor r=0.6109 c=0 +rf56 (\2\:I5\|I1\|Bi \4\:I5\|I1\|Bi) resistor r=0.2422 c=0 +rf57 (\5\:I4\|I4\|Bi \6\:I4\|I4\|Bi) resistor r=0.3789 c=0 +rf58 (\6\:I4\|I4\|Bi I4\|I4\|Bi) resistor r=0.2425 c=0 +rf59 (\6\:I4\|I4\|Bi \7\:I4\|I4\|Bi) resistor r=0.3634 c=0 +rf60 (\5\:I9\|I4\|Bi \6\:I9\|I4\|Bi) resistor r=0.3789 c=0 +rf61 (\6\:I9\|I4\|Bi I9\|I4\|Bi) resistor r=0.2425 c=0 +rf62 (\6\:I9\|I4\|Bi \7\:I9\|I4\|Bi) resistor r=0.3634 c=0 +rf63 (\6\:net19 \7\:net19) resistor r=2.0233 c=0 +rf64 (net16 \2\:net16) resistor r=2.0233 c=0 +rf65 (net55 \2\:net55) resistor r=2.01 c=0 +rf66 (\5\:I5\|I3\|net013 \6\:I5\|I3\|net013) resistor r=0.4307 c=0 +rf67 (\6\:I5\|I3\|net013 I5\|I3\|net013) resistor r=0.5507 c=0 +rf68 (\6\:I5\|I3\|net013 \7\:I5\|I3\|net013) resistor r=0.8338 c=0 +rf69 (\8\:I4\|net3 \9\:I4\|net3) resistor r=0.01 c=0 +rf70 (\8\:I9\|net3 \9\:I9\|net3) resistor r=0.01 c=0 +rf71 (\3\:net55 \4\:net55) resistor r=0.002222 c=0 +rf72 (I4\|net1 \2\:I4\|net1) resistor r=0.7023 c=0 +rf73 (\2\:I4\|net1 \3\:I4\|net1) resistor r=0.5764 c=0 +rf74 (\2\:I4\|net1 \4\:I4\|net1) resistor r=0.5108 c=0 +rf75 (I9\|net1 \2\:I9\|net1) resistor r=0.7023 c=0 +rf76 (\2\:I9\|net1 \3\:I9\|net1) resistor r=0.5764 c=0 +rf77 (\2\:I9\|net1 \4\:I9\|net1) resistor r=0.5108 c=0 +rf78 (\5\:net55 \6\:net55) resistor r=0.002222 c=0 +rf79 (net54 \2\:net54) resistor r=0.629 c=0 +rf80 (\2\:net54 \3\:net54) resistor r=0.1083 c=0 +rf81 (\3\:net54 \4\:net54) resistor r=0.1123 c=0 +rf82 (\4\:net54 \5\:net54) resistor r=0.4382 c=0 +rf83 (\2\:net54 \6\:net54) resistor r=0.4386 c=0 +rf84 (\4\:net54 \7\:net54) resistor r=0.6387 c=0 +rf85 (I4\|I3\|Ai \2\:I4\|I3\|Ai) resistor r=0.04192 c=0 +rf86 (\2\:I4\|I3\|Ai \3\:I4\|I3\|Ai) resistor r=0.6961 c=0 +rf87 (\2\:I4\|I3\|Ai \4\:I4\|I3\|Ai) resistor r=0.4006 c=0 +rf88 (I9\|I3\|Ai \2\:I9\|I3\|Ai) resistor r=0.04192 c=0 +rf89 (\2\:I9\|I3\|Ai \3\:I9\|I3\|Ai) resistor r=0.6961 c=0 +rf90 (\2\:I9\|I3\|Ai \4\:I9\|I3\|Ai) resistor r=0.4006 c=0 +rf91 (\14\:net16 \13\:net16) resistor r=0.1956 c=0 +rf92 (\13\:net16 \15\:net16) resistor r=1.0615 c=0 +rf93 (\2\:Z7 \1\:Z7) resistor r=0.1956 c=0 +rf94 (\1\:Z7 \3\:Z7) resistor r=1.0615 c=0 +rf95 (\19\:X3 \20\:X3) resistor r=0.01 c=0 +rf96 (\14\:net55 \15\:net55) resistor r=0.01 c=0 +rf97 (\15\:I4\|net3 \13\:I4\|net3) resistor r=0.08472 c=0 +rf98 (\15\:I9\|net3 \13\:I9\|net3) resistor r=0.08472 c=0 +rf99 (\3\:net21 \2\:net21) resistor r=0.1 c=0 +rf100 (\3\:net15 \2\:net15) resistor r=2.1 c=0 +rf102 (I12\|net013 \2\:I12\|net013) resistor r=0.2434 c=0 +rf103 (\2\:I12\|net013 \3\:I12\|net013) resistor r=0.3205 c=0 +rf104 (\2\:I12\|net013 \4\:I12\|net013) resistor r=0.5422 c=0 +rf105 (\4\:I5\|I1\|Ai \5\:I5\|I1\|Ai) resistor r=0.2765 c=0 +rf106 (\5\:I5\|I1\|Ai \2\:I5\|I1\|Ai) resistor r=0.04519 c=0 +rf107 (\5\:I5\|I1\|Ai \6\:I5\|I1\|Ai) resistor r=0.7634 c=0 +rf108 (\3\:net17 \4\:net17) resistor r=0.2905 c=0 +rf109 (\4\:net17 \5\:net17) resistor r=0.08276 c=0 +rf110 (\5\:net17 \6\:net17) resistor r=0.2973 c=0 +rf111 (\5\:net17 \7\:net17) resistor r=0.4127 c=0 +rf112 (\7\:net17 \8\:net17) resistor r=0.3748 c=0 +rf113 (\7\:net17 \9\:net17) resistor r=0.5859 c=0 +rf114 (\2\:net17 \4\:net17) resistor r=2 c=0 +rf115 (\2\:Z6 \1\:Z6) resistor r=0.2905 c=0 +rf116 (\1\:Z6 \3\:Z6) resistor r=0.08276 c=0 +rf117 (\3\:Z6 \4\:Z6) resistor r=0.2973 c=0 +rf118 (\3\:Z6 \5\:Z6) resistor r=0.4127 c=0 +rf119 (\5\:Z6 \6\:Z6) resistor r=0.3748 c=0 +rf120 (\5\:Z6 \7\:Z6) resistor r=0.5859 c=0 +rf121 (\16\:net55 \20\:net55) resistor r=0.01 c=0 +rf122 (\5\:I4\|net6 \6\:I4\|net6) resistor r=0.7681 c=0 +rf123 (\6\:I4\|net6 I4\|net6) resistor r=0.8057 c=0 +rf124 (\6\:I4\|net6 \7\:I4\|net6) resistor r=0.4319 c=0 +rf125 (\5\:I9\|net6 \6\:I9\|net6) resistor r=0.7681 c=0 +rf126 (\6\:I9\|net6 I9\|net6) resistor r=0.8057 c=0 +rf127 (\6\:I9\|net6 \7\:I9\|net6) resistor r=0.4319 c=0 +rf128 (net39 \2\:net39) resistor r=0.2066 c=0 +rf129 (\2\:net39 \3\:net39) resistor r=0.6132 c=0 +rf131 (I4\|I3\|Bi \4\:I4\|I3\|Bi) resistor r=0.07769 c=0 +rf132 (\4\:I4\|I3\|Bi \5\:I4\|I3\|Bi) resistor r=0.2684 c=0 +rf133 (\4\:I4\|I3\|Bi \6\:I4\|I3\|Bi) resistor r=0.5661 c=0 +rf134 (I9\|I3\|Bi \4\:I9\|I3\|Bi) resistor r=0.07769 c=0 +rf135 (\4\:I9\|I3\|Bi \5\:I9\|I3\|Bi) resistor r=0.2684 c=0 +rf136 (\4\:I9\|I3\|Bi \6\:I9\|I3\|Bi) resistor r=0.5661 c=0 +rf137 (\6\:Y3 \7\:Y3) resistor r=0.01 c=0 +rf138 (\5\:X2 \1\:X2) resistor r=2.01 c=0 +rf139 (\6\:Y2 \7\:Y2) resistor r=0.01 c=0 +rf140 (I18\|net013 \2\:I18\|net013) resistor r=0.2434 c=0 +rf141 (\2\:I18\|net013 \3\:I18\|net013) resistor r=0.3205 c=0 +rf142 (\2\:I18\|net013 \4\:I18\|net013) resistor r=0.5422 c=0 +rf143 (\11\:X2 \7\:X2) resistor r=2.01 c=0 +rf144 (\12\:X2 \13\:X2) resistor r=2.01 c=0 +rf145 (I26\|net013 \2\:I26\|net013) resistor r=0.2434 c=0 +rf146 (\2\:I26\|net013 \3\:I26\|net013) resistor r=0.3205 c=0 +rf147 (\2\:I26\|net013 \4\:I26\|net013) resistor r=0.5422 c=0 +rf148 (I21\|net013 \2\:I21\|net013) resistor r=0.2434 c=0 +rf149 (\2\:I21\|net013 \3\:I21\|net013) resistor r=0.3205 c=0 +rf150 (\2\:I21\|net013 \4\:I21\|net013) resistor r=0.5422 c=0 +rf151 (net38 \2\:net38) resistor r=2.0022 c=0 +rf152 (\3\:net38 \4\:net38) resistor r=0.2066 c=0 +rf153 (\4\:net38 \5\:net38) resistor r=0.6132 c=0 +rf154 (I0\|net3 \2\:I0\|net3) resistor r=0.7396 c=0 +rf155 (\2\:I0\|net3 \3\:I0\|net3) resistor r=0.4087 c=0 +rf156 (\3\:I0\|net3 \4\:I0\|net3) resistor r=0.7213 c=0 +rf157 (\2\:I0\|net3 \5\:I0\|net3) resistor r=0.2896 c=0 +rf158 (\2\:I0\|net3 \6\:I0\|net3) resistor r=2.2056 c=0 +rf159 (\3\:I0\|net3 \7\:I0\|net3) resistor r=0.2841 c=0 +rf160 (net8 \2\:net8) resistor r=0.2066 c=0 +rf161 (\2\:net8 \3\:net8) resistor r=0.6132 c=0 +rf162 (\4\:net8 \5\:net8) resistor r=2.0022 c=0 +rf163 (net087 \2\:net087) resistor r=0.2066 c=0 +rf164 (\2\:net087 \3\:net087) resistor r=0.6132 c=0 +rf165 (\4\:net087 \5\:net087) resistor r=2.0022 c=0 +rf166 (I0\|I4\|Ai \2\:I0\|I4\|Ai) resistor r=0.84 c=0 +rf167 (I0\|I4\|Ai \3\:I0\|I4\|Ai) resistor r=0.2475 c=0 +rf168 (\9\:net38 \10\:net38) resistor r=2.0267 c=0 +rf169 (\11\:net38 \12\:net38) resistor r=0.02222 c=0 +rf170 (I10\|net3 \2\:I10\|net3) resistor r=0.7396 c=0 +rf171 (\2\:I10\|net3 \3\:I10\|net3) resistor r=0.4087 c=0 +rf172 (\3\:I10\|net3 \4\:I10\|net3) resistor r=0.7213 c=0 +rf173 (\2\:I10\|net3 \5\:I10\|net3) resistor r=0.2896 c=0 +rf174 (\2\:I10\|net3 \6\:I10\|net3) resistor r=2.2056 c=0 +rf175 (\3\:I10\|net3 \7\:I10\|net3) resistor r=0.2841 c=0 +rf176 (\5\:I0\|I4\|Bi \6\:I0\|I4\|Bi) resistor r=0.3789 c=0 +rf177 (\6\:I0\|I4\|Bi I0\|I4\|Bi) resistor r=0.2425 c=0 +rf178 (\6\:I0\|I4\|Bi \7\:I0\|I4\|Bi) resistor r=0.3634 c=0 +rf179 (I3\|net3 \2\:I3\|net3) resistor r=0.7396 c=0 +rf180 (\2\:I3\|net3 \3\:I3\|net3) resistor r=0.4087 c=0 +rf181 (\3\:I3\|net3 \4\:I3\|net3) resistor r=0.7213 c=0 +rf182 (\2\:I3\|net3 \5\:I3\|net3) resistor r=0.2896 c=0 +rf183 (\2\:I3\|net3 \6\:I3\|net3) resistor r=2.2056 c=0 +rf184 (\3\:I3\|net3 \7\:I3\|net3) resistor r=0.2841 c=0 +rf185 (\4\:I10\|I4\|Ai \5\:I10\|I4\|Ai) resistor r=0.84 c=0 +rf186 (\4\:I10\|I4\|Ai \3\:I10\|I4\|Ai) resistor r=0.2475 c=0 +rf187 (I3\|I4\|Ai \2\:I3\|I4\|Ai) resistor r=0.84 c=0 +rf188 (I3\|I4\|Ai \3\:I3\|I4\|Ai) resistor r=0.2475 c=0 +rf189 (\10\:net8 \9\:net8) resistor r=0.02667 c=0 +rf190 (\11\:net8 \12\:net8) resistor r=0.02222 c=0 +rf191 (\13\:net39 \4\:net39) resistor r=2.0233 c=0 +rf192 (\5\:I10\|I4\|Bi \6\:I10\|I4\|Bi) resistor r=0.3789 c=0 +rf193 (\6\:I10\|I4\|Bi I10\|I4\|Bi) resistor r=0.2425 c=0 +rf194 (\6\:I10\|I4\|Bi \7\:I10\|I4\|Bi) resistor r=0.3634 c=0 +rf195 (\9\:net087 \10\:net087) resistor r=2.0267 c=0 +rf196 (\11\:net087 \12\:net087) resistor r=0.02222 c=0 +rf197 (\8\:I0\|net3 \9\:I0\|net3) resistor r=0.01 c=0 +rf198 (\5\:I3\|I4\|Bi \6\:I3\|I4\|Bi) resistor r=0.3789 c=0 +rf199 (\6\:I3\|I4\|Bi I3\|I4\|Bi) resistor r=0.2425 c=0 +rf200 (\6\:I3\|I4\|Bi \7\:I3\|I4\|Bi) resistor r=0.3634 c=0 +rf201 (I0\|net1 \2\:I0\|net1) resistor r=0.7023 c=0 +rf202 (\2\:I0\|net1 \3\:I0\|net1) resistor r=0.5764 c=0 +rf203 (\2\:I0\|net1 \4\:I0\|net1) resistor r=0.5108 c=0 +rf204 (\19\:net17 \10\:net17) resistor r=2.0233 c=0 +rf205 (I0\|I3\|Ai \2\:I0\|I3\|Ai) resistor r=0.04192 c=0 +rf206 (\2\:I0\|I3\|Ai \3\:I0\|I3\|Ai) resistor r=0.6961 c=0 +rf207 (\2\:I0\|I3\|Ai \4\:I0\|I3\|Ai) resistor r=0.4006 c=0 +rf208 (\22\:net55 \21\:net55) resistor r=0.1956 c=0 +rf209 (\21\:net55 \23\:net55) resistor r=1.0615 c=0 +rf210 (\19\:net54 \10\:net54) resistor r=2.0233 c=0 +rf211 (\8\:I10\|net3 \9\:I10\|net3) resistor r=0.01 c=0 +rf212 (\8\:I3\|net3 \9\:I3\|net3) resistor r=0.01 c=0 +rf213 (I10\|net1 \2\:I10\|net1) resistor r=0.7023 c=0 +rf214 (\2\:I10\|net1 \3\:I10\|net1) resistor r=0.5764 c=0 +rf215 (\2\:I10\|net1 \4\:I10\|net1) resistor r=0.5108 c=0 +rf216 (I3\|net1 \2\:I3\|net1) resistor r=0.7023 c=0 +rf217 (\2\:I3\|net1 \3\:I3\|net1) resistor r=0.5764 c=0 +rf218 (\2\:I3\|net1 \4\:I3\|net1) resistor r=0.5108 c=0 +rf219 (I10\|I3\|Ai \2\:I10\|I3\|Ai) resistor r=0.04192 c=0 +rf220 (\2\:I10\|I3\|Ai \3\:I10\|I3\|Ai) resistor r=0.6961 c=0 +rf221 (\2\:I10\|I3\|Ai \4\:I10\|I3\|Ai) resistor r=0.4006 c=0 +rf222 (\13\:I0\|net3 \14\:I0\|net3) resistor r=2.0847 c=0 +rf223 (\13\:net15 \11\:net15) resistor r=0.1956 c=0 +rf224 (\11\:net15 \14\:net15) resistor r=1.0615 c=0 +rf225 (net31 \2\:net31) resistor r=2.1 c=0 +rf226 (I3\|I3\|Ai \2\:I3\|I3\|Ai) resistor r=0.04192 c=0 +rf227 (\2\:I3\|I3\|Ai \3\:I3\|I3\|Ai) resistor r=0.6961 c=0 +rf228 (\2\:I3\|I3\|Ai \4\:I3\|I3\|Ai) resistor r=0.4006 c=0 +rf229 (\11\:net21 \12\:net21) resistor r=0.1956 c=0 +rf230 (\12\:net21 \13\:net21) resistor r=1.0615 c=0 +rf231 (\15\:I10\|net3 \13\:I10\|net3) resistor r=0.08472 c=0 +rf232 (net29 \2\:net29) resistor r=0.2905 c=0 +rf233 (\2\:net29 \3\:net29) resistor r=0.08276 c=0 +rf234 (\3\:net29 \4\:net29) resistor r=0.2973 c=0 +rf235 (\3\:net29 \5\:net29) resistor r=0.4127 c=0 +rf236 (\5\:net29 \6\:net29) resistor r=0.3748 c=0 +rf237 (\5\:net29 \7\:net29) resistor r=0.5859 c=0 +rf238 (net1 \2\:net1) resistor r=2.1 c=0 +rf239 (\5\:I0\|net6 \6\:I0\|net6) resistor r=0.7681 c=0 +rf240 (\6\:I0\|net6 I0\|net6) resistor r=0.8057 c=0 +rf241 (\6\:I0\|net6 \7\:I0\|net6) resistor r=0.4319 c=0 +rf242 (\13\:I3\|net3 \14\:I3\|net3) resistor r=2.0847 c=0 +rf243 (net26 \2\:net26) resistor r=2.1 c=0 +rf244 (\1\:Z5 \2\:Z5) resistor r=0.2905 c=0 +rf245 (\2\:Z5 \3\:Z5) resistor r=0.08276 c=0 +rf246 (\3\:Z5 \4\:Z5) resistor r=0.2973 c=0 +rf247 (\3\:Z5 \5\:Z5) resistor r=0.4127 c=0 +rf248 (\5\:Z5 \6\:Z5) resistor r=0.3748 c=0 +rf249 (\5\:Z5 \7\:Z5) resistor r=0.5859 c=0 +rf250 (\5\:I10\|net6 \6\:I10\|net6) resistor r=0.7681 c=0 +rf251 (\6\:I10\|net6 I10\|net6) resistor r=0.8057 c=0 +rf252 (\6\:I10\|net6 \7\:I10\|net6) resistor r=0.4319 c=0 +rf253 (net0100 \2\:net0100) resistor r=0.2905 c=0 +rf254 (\2\:net0100 \3\:net0100) resistor r=0.08276 c=0 +rf255 (\3\:net0100 \4\:net0100) resistor r=0.2973 c=0 +rf256 (\3\:net0100 \5\:net0100) resistor r=0.4127 c=0 +rf257 (\5\:net0100 \6\:net0100) resistor r=0.3748 c=0 +rf258 (\5\:net0100 \7\:net0100) resistor r=0.5859 c=0 +rf259 (\5\:I3\|net6 \6\:I3\|net6) resistor r=0.7681 c=0 +rf260 (\6\:I3\|net6 I3\|net6) resistor r=0.8057 c=0 +rf261 (\6\:I3\|net6 \7\:I3\|net6) resistor r=0.4319 c=0 +rf262 (I0\|I3\|Bi \2\:I0\|I3\|Bi) resistor r=0.07769 c=0 +rf263 (\2\:I0\|I3\|Bi \3\:I0\|I3\|Bi) resistor r=0.2684 c=0 +rf264 (\2\:I0\|I3\|Bi \4\:I0\|I3\|Bi) resistor r=0.5661 c=0 +rf265 (I1\|I3\|Bi \2\:I1\|I3\|Bi) resistor r=0.2684 c=0 +rf266 (\2\:I1\|I3\|Bi \3\:I1\|I3\|Bi) resistor r=0.07769 c=0 +rf267 (\2\:I1\|I3\|Bi \4\:I1\|I3\|Bi) resistor r=0.5661 c=0 +rf268 (I10\|I3\|Bi \4\:I10\|I3\|Bi) resistor r=0.07769 c=0 +rf269 (\4\:I10\|I3\|Bi \5\:I10\|I3\|Bi) resistor r=0.2684 c=0 +rf270 (\4\:I10\|I3\|Bi \6\:I10\|I3\|Bi) resistor r=0.5661 c=0 +rf271 (I3\|I3\|Bi \4\:I3\|I3\|Bi) resistor r=0.07769 c=0 +rf272 (\4\:I3\|I3\|Bi \5\:I3\|I3\|Bi) resistor r=0.2684 c=0 +rf273 (\4\:I3\|I3\|Bi \6\:I3\|I3\|Bi) resistor r=0.5661 c=0 +rf274 (I11\|I3\|Bi \2\:I11\|I3\|Bi) resistor r=0.2684 c=0 +rf275 (\2\:I11\|I3\|Bi \3\:I11\|I3\|Bi) resistor r=0.07769 c=0 +rf276 (\2\:I11\|I3\|Bi \4\:I11\|I3\|Bi) resistor r=0.5661 c=0 +rf277 (net32 \2\:net32) resistor r=0.2973 c=0 +rf278 (\2\:net32 \3\:net32) resistor r=0.08276 c=0 +rf279 (\3\:net32 \4\:net32) resistor r=0.2905 c=0 +rf280 (\2\:net32 \5\:net32) resistor r=0.4127 c=0 +rf281 (\5\:net32 \6\:net32) resistor r=0.5859 c=0 +rf282 (\5\:net32 \7\:net32) resistor r=0.3748 c=0 +rf283 (I2\|I3\|Bi \2\:I2\|I3\|Bi) resistor r=0.2684 c=0 +rf284 (\2\:I2\|I3\|Bi \3\:I2\|I3\|Bi) resistor r=0.07769 c=0 +rf285 (\2\:I2\|I3\|Bi \4\:I2\|I3\|Bi) resistor r=0.5661 c=0 +rf286 (net35 \2\:net35) resistor r=2.1 c=0 +rf287 (\4\:I1\|net3 \7\:I1\|net3) resistor r=2.0847 c=0 +rf288 (I1\|net6 \2\:I1\|net6) resistor r=0.7681 c=0 +rf289 (\2\:I1\|net6 \3\:I1\|net6) resistor r=0.4319 c=0 +rf290 (\2\:I1\|net6 \4\:I1\|net6) resistor r=0.8057 c=0 +rf291 (\2\:Z4 \3\:Z4) resistor r=0.2973 c=0 +rf292 (\3\:Z4 \1\:Z4) resistor r=0.08276 c=0 +rf293 (\1\:Z4 \4\:Z4) resistor r=0.2905 c=0 +rf294 (\3\:Z4 \5\:Z4) resistor r=0.4127 c=0 +rf295 (\5\:Z4 \6\:Z4) resistor r=0.5859 c=0 +rf296 (\5\:Z4 \7\:Z4) resistor r=0.3748 c=0 +rf297 (\2\:I1\|I3\|Ai \4\:I1\|I3\|Ai) resistor r=0.04192 c=0 +rf298 (\4\:I1\|I3\|Ai \5\:I1\|I3\|Ai) resistor r=0.6961 c=0 +rf299 (\4\:I1\|I3\|Ai \6\:I1\|I3\|Ai) resistor r=0.4006 c=0 +rf300 (\10\:net31 \11\:net31) resistor r=0.1956 c=0 +rf301 (\11\:net31 \12\:net31) resistor r=1.0615 c=0 +rf302 (net44 \2\:net44) resistor r=0.2973 c=0 +rf303 (\2\:net44 \3\:net44) resistor r=0.08276 c=0 +rf304 (\3\:net44 \4\:net44) resistor r=0.2905 c=0 +rf305 (\2\:net44 \5\:net44) resistor r=0.4127 c=0 +rf306 (\5\:net44 \6\:net44) resistor r=0.5859 c=0 +rf307 (\5\:net44 \7\:net44) resistor r=0.3748 c=0 +rf308 (net5 \2\:net5) resistor r=2.1 c=0 +rf309 (\8\:I1\|net3 \12\:I1\|net3) resistor r=0.01 c=0 +rf310 (\4\:I11\|net3 \7\:I11\|net3) resistor r=2.0847 c=0 +rf311 (I11\|net6 \2\:I11\|net6) resistor r=0.7681 c=0 +rf312 (\2\:I11\|net6 \3\:I11\|net6) resistor r=0.4319 c=0 +rf313 (\2\:I11\|net6 \4\:I11\|net6) resistor r=0.8057 c=0 +rf314 (net095 \2\:net095) resistor r=2.0233 c=0 +rf315 (net45 \2\:net45) resistor r=2.1 c=0 +rf316 (\4\:I2\|net3 \7\:I2\|net3) resistor r=2.0847 c=0 +rf317 (I2\|net6 \2\:I2\|net6) resistor r=0.7681 c=0 +rf318 (\2\:I2\|net6 \3\:I2\|net6) resistor r=0.4319 c=0 +rf319 (\2\:I2\|net6 \4\:I2\|net6) resistor r=0.8057 c=0 +rf320 (\2\:I11\|I3\|Ai \4\:I11\|I3\|Ai) resistor r=0.04192 c=0 +rf321 (\4\:I11\|I3\|Ai \5\:I11\|I3\|Ai) resistor r=0.6961 c=0 +rf322 (\4\:I11\|I3\|Ai \6\:I11\|I3\|Ai) resistor r=0.4006 c=0 +rf323 (\10\:net1 \11\:net1) resistor r=0.1956 c=0 +rf324 (\11\:net1 \12\:net1) resistor r=1.0615 c=0 +rf325 (net34 \2\:net34) resistor r=0.02222 c=0 +rf326 (\3\:net34 \4\:net34) resistor r=2.0267 c=0 +rf327 (\5\:I1\|net1 \6\:I1\|net1) resistor r=0.7023 c=0 +rf328 (\6\:I1\|net1 I1\|net1) resistor r=0.5108 c=0 +rf329 (\6\:I1\|net1 \7\:I1\|net1) resistor r=0.5764 c=0 +rf330 (\8\:I11\|net3 \12\:I11\|net3) resistor r=0.01 c=0 +rf331 (\2\:I2\|I3\|Ai \4\:I2\|I3\|Ai) resistor r=0.04192 c=0 +rf332 (\4\:I2\|I3\|Ai \5\:I2\|I3\|Ai) resistor r=0.6961 c=0 +rf333 (\4\:I2\|I3\|Ai \6\:I2\|I3\|Ai) resistor r=0.4006 c=0 +rf334 (I1\|I4\|Ai \2\:I1\|I4\|Ai) resistor r=0.3634 c=0 +rf335 (\2\:I1\|I4\|Ai \3\:I1\|I4\|Ai) resistor r=0.3789 c=0 +rf336 (\2\:I1\|I4\|Ai \4\:I1\|I4\|Ai) resistor r=0.2425 c=0 +rf337 (\10\:net26 \11\:net26) resistor r=0.1956 c=0 +rf338 (\11\:net26 \12\:net26) resistor r=1.0615 c=0 +rf339 (I1\|I4\|Bi \2\:I1\|I4\|Bi) resistor r=0.84 c=0 +rf340 (\2\:I1\|I4\|Bi \3\:I1\|I4\|Bi) resistor r=0.2475 c=0 +rf341 (\9\:net0100 \10\:net0100) resistor r=2.0233 c=0 +rf342 (\8\:I2\|net3 \9\:I2\|net3) resistor r=0.01 c=0 +rf343 (\9\:net29 \10\:net29) resistor r=2.0233 c=0 +rf344 (net078 \2\:net078) resistor r=0.02222 c=0 +rf345 (\3\:net078 \4\:net078) resistor r=2.0267 c=0 +rf346 (\5\:I11\|net1 \6\:I11\|net1) resistor r=0.7023 c=0 +rf347 (\6\:I11\|net1 I11\|net1) resistor r=0.5108 c=0 +rf348 (\6\:I11\|net1 \7\:I11\|net1) resistor r=0.5764 c=0 +rf349 (\19\:X2 \20\:X2) resistor r=0.01 c=0 +rf350 (\12\:net34 \13\:net34) resistor r=2.0022 c=0 +rf351 (I11\|I4\|Bi \2\:I11\|I4\|Bi) resistor r=0.3634 c=0 +rf352 (\2\:I11\|I4\|Bi \3\:I11\|I4\|Bi) resistor r=0.3789 c=0 +rf353 (\2\:I11\|I4\|Bi \4\:I11\|I4\|Bi) resistor r=0.2425 c=0 +rf354 (net28 \2\:net28) resistor r=0.02222 c=0 +rf355 (\3\:net28 \4\:net28) resistor r=2.0267 c=0 +rf356 (\5\:I2\|net1 \6\:I2\|net1) resistor r=0.7023 c=0 +rf357 (\6\:I2\|net1 I2\|net1) resistor r=0.5108 c=0 +rf358 (\6\:I2\|net1 \7\:I2\|net1) resistor r=0.5764 c=0 +rf359 (I11\|I4\|Ai \2\:I11\|I4\|Ai) resistor r=0.84 c=0 +rf360 (\2\:I11\|I4\|Ai \3\:I11\|I4\|Ai) resistor r=0.2475 c=0 +rf361 (\15\:I1\|net3 \16\:I1\|net3) resistor r=0.7213 c=0 +rf362 (\16\:I1\|net3 \17\:I1\|net3) resistor r=0.4087 c=0 +rf363 (\17\:I1\|net3 \13\:I1\|net3) resistor r=0.2056 c=0 +rf364 (\16\:I1\|net3 \18\:I1\|net3) resistor r=0.2841 c=0 +rf365 (\17\:I1\|net3 \19\:I1\|net3) resistor r=0.2896 c=0 +rf366 (\17\:I1\|net3 \20\:I1\|net3) resistor r=0.7396 c=0 +rf367 (I2\|I4\|Bi \2\:I2\|I4\|Bi) resistor r=0.3634 c=0 +rf368 (\2\:I2\|I4\|Bi \3\:I2\|I4\|Bi) resistor r=0.3789 c=0 +rf369 (\2\:I2\|I4\|Bi \4\:I2\|I4\|Bi) resistor r=0.2425 c=0 +rf370 (I2\|I4\|Ai \2\:I2\|I4\|Ai) resistor r=0.84 c=0 +rf371 (\2\:I2\|I4\|Ai \3\:I2\|I4\|Ai) resistor r=0.2475 c=0 +rf373 (I13\|net013 \2\:I13\|net013) resistor r=0.2434 c=0 +rf374 (\2\:I13\|net013 \3\:I13\|net013) resistor r=0.3205 c=0 +rf375 (\2\:I13\|net013 \4\:I13\|net013) resistor r=0.5422 c=0 +rf376 (\12\:net078 \13\:net078) resistor r=2.0022 c=0 +rf377 (\15\:I11\|net3 \16\:I11\|net3) resistor r=0.7213 c=0 +rf378 (\16\:I11\|net3 \17\:I11\|net3) resistor r=0.4087 c=0 +rf379 (\17\:I11\|net3 \13\:I11\|net3) resistor r=0.2056 c=0 +rf380 (\16\:I11\|net3 \18\:I11\|net3) resistor r=0.2841 c=0 +rf381 (\17\:I11\|net3 \19\:I11\|net3) resistor r=0.2896 c=0 +rf382 (\17\:I11\|net3 \20\:I11\|net3) resistor r=0.7396 c=0 +rf383 (\12\:net28 \13\:net28) resistor r=2.0022 c=0 +rf384 (\17\:net34 \18\:net34) resistor r=0.2066 c=0 +rf385 (\18\:net34 \19\:net34) resistor r=0.6132 c=0 +rf386 (\14\:net078 \15\:net078) resistor r=0.2066 c=0 +rf387 (\15\:net078 \16\:net078) resistor r=0.6132 c=0 +rf388 (\15\:net28 \14\:net28) resistor r=0.2066 c=0 +rf389 (\14\:net28 \16\:net28) resistor r=0.6132 c=0 +rf390 (\15\:I2\|net3 \16\:I2\|net3) resistor r=0.7213 c=0 +rf391 (\16\:I2\|net3 \17\:I2\|net3) resistor r=0.4087 c=0 +rf392 (\17\:I2\|net3 \13\:I2\|net3) resistor r=0.2056 c=0 +rf393 (\16\:I2\|net3 \18\:I2\|net3) resistor r=0.2841 c=0 +rf394 (\17\:I2\|net3 \19\:I2\|net3) resistor r=0.2896 c=0 +rf395 (\17\:I2\|net3 \20\:I2\|net3) resistor r=0.7396 c=0 +rf396 (\5\:net0115 \3\:net0115) resistor r=0.01 c=0 +rf397 (\1\:X1 \2\:X1) resistor r=0.01 c=0 +rf398 (\7\:X1 \8\:X1) resistor r=2.01 c=0 +rf399 (I6\|I1\|Ai \2\:I6\|I1\|Ai) resistor r=0.04519 c=0 +rf400 (\2\:I6\|I1\|Ai \3\:I6\|I1\|Ai) resistor r=0.7634 c=0 +rf401 (\2\:I6\|I1\|Ai \4\:I6\|I1\|Ai) resistor r=0.2765 c=0 +rf402 (\13\:X1 \14\:X1) resistor r=2.01 c=0 +rf404 (I16\|net013 \2\:I16\|net013) resistor r=0.2434 c=0 +rf405 (\2\:I16\|net013 \3\:I16\|net013) resistor r=0.3205 c=0 +rf406 (\2\:I16\|net013 \4\:I16\|net013) resistor r=0.5422 c=0 +rf407 (\11\:Y3 \15\:Y3) resistor r=0.01 c=0 +rf408 (\5\:I24\|net013 \6\:I24\|net013) resistor r=0.236 c=0 +rf409 (\6\:I24\|net013 I24\|net013) resistor r=0.2322 c=0 +rf410 (\6\:I24\|net013 \7\:I24\|net013) resistor r=0.5701 c=0 +rf411 (\6\:net0115 \7\:net0115) resistor r=0.01 c=0 +rf412 (\11\:Y2 \15\:Y2) resistor r=0.01 c=0 +rf413 (\5\:I23\|net013 \6\:I23\|net013) resistor r=0.236 c=0 +rf414 (\6\:I23\|net013 I23\|net013) resistor r=0.2322 c=0 +rf415 (\6\:I23\|net013 \7\:I23\|net013) resistor r=0.5701 c=0 +rf416 (\11\:net095 \12\:net095) resistor r=0.2066 c=0 +rf417 (\12\:net095 \13\:net095) resistor r=0.6132 c=0 +rf418 (\8\:net0115 \9\:net0115) resistor r=0.002222 c=0 +rf419 (\10\:net0115 \11\:net0115) resistor r=0.002222 c=0 +rf420 (\1\:Z1 \2\:Z1) resistor r=0.4382 c=0 +rf421 (\2\:Z1 \3\:Z1) resistor r=0.1123 c=0 +rf422 (\3\:Z1 \4\:Z1) resistor r=0.1083 c=0 +rf423 (\4\:Z1 \5\:Z1) resistor r=0.629 c=0 +rf424 (\2\:Z1 \6\:Z1) resistor r=0.6387 c=0 +rf425 (\4\:Z1 \7\:Z1) resistor r=0.4386 c=0 +rf426 (\15\:net0115 \20\:net0115) resistor r=2.01 c=0 +rf427 (\12\:net5 \13\:net5) resistor r=0.285 c=0 +rf428 (\12\:net5 \14\:net5) resistor r=0.8307 c=0 +rf429 (\12\:net45 \13\:net45) resistor r=0.285 c=0 +rf430 (\12\:net45 \14\:net45) resistor r=0.8307 c=0 +rf431 (net0127 \2\:net0127) resistor r=2.0111 c=0 +rf432 (\9\:net44 \10\:net44) resistor r=2.0111 c=0 +rf433 (I8\|I1\|Bi \2\:I8\|I1\|Bi) resistor r=0.3619 c=0 +rf434 (\2\:I8\|I1\|Bi \3\:I8\|I1\|Bi) resistor r=0.6109 c=0 +rf435 (\2\:I8\|I1\|Bi \4\:I8\|I1\|Bi) resistor r=0.2422 c=0 +rf436 (\9\:net32 \10\:net32) resistor r=2.0111 c=0 +rf437 (I7\|I1\|Bi \2\:I7\|I1\|Bi) resistor r=0.3619 c=0 +rf438 (\2\:I7\|I1\|Bi \3\:I7\|I1\|Bi) resistor r=0.6109 c=0 +rf439 (\2\:I7\|I1\|Bi \4\:I7\|I1\|Bi) resistor r=0.2422 c=0 +rf440 (\5\:I6\|I1\|Bi \6\:I6\|I1\|Bi) resistor r=0.3619 c=0 +rf441 (\6\:I6\|I1\|Bi I6\|I1\|Bi) resistor r=0.2422 c=0 +rf442 (\6\:I6\|I1\|Bi \7\:I6\|I1\|Bi) resistor r=0.6109 c=0 +rf443 (\5\:I6\|I3\|net013 \6\:I6\|I3\|net013) resistor r=0.4307 c=0 +rf444 (\6\:I6\|I3\|net013 \7\:I6\|I3\|net013) resistor r=0.8338 c=0 +rf445 (\6\:I6\|I3\|net013 \3\:I6\|I3\|net013) resistor r=0.5507 c=0 +rf446 (net075 \2\:net075) resistor r=2.01 c=0 +rf447 (net47 \2\:net47) resistor r=2.01 c=0 +rf448 (\10\:net35 \11\:net35) resistor r=0.8307 c=0 +rf449 (\11\:net35 \12\:net35) resistor r=0.285 c=0 +rf450 (\5\:I8\|I3\|net013 \6\:I8\|I3\|net013) resistor r=0.4307 c=0 +rf451 (\6\:I8\|I3\|net013 I8\|I3\|net013) resistor r=0.5507 c=0 +rf452 (\6\:I8\|I3\|net013 \7\:I8\|I3\|net013) resistor r=0.8338 c=0 +rf453 (\5\:I7\|I3\|net013 \6\:I7\|I3\|net013) resistor r=0.4307 c=0 +rf454 (\6\:I7\|I3\|net013 I7\|I3\|net013) resistor r=0.5507 c=0 +rf455 (\6\:I7\|I3\|net013 \7\:I7\|I3\|net013) resistor r=0.8338 c=0 +rf456 (\3\:net075 \4\:net075) resistor r=0.002222 c=0 +rf457 (\3\:net47 \4\:net47) resistor r=0.002222 c=0 +rf458 (\5\:net075 \6\:net075) resistor r=0.002222 c=0 +rf459 (\5\:net47 \6\:net47) resistor r=0.002222 c=0 +rf460 (\10\:net075 \11\:net075) resistor r=0.2066 c=0 +rf461 (\11\:net075 \12\:net075) resistor r=0.6132 c=0 +rf462 (\10\:net47 \11\:net47) resistor r=0.2066 c=0 +rf463 (\11\:net47 \12\:net47) resistor r=0.6132 c=0 +rf464 (\23\:X1 \21\:X1) resistor r=0.01 c=0 +rf466 (\1\:Z3 \2\:Z3) resistor r=0.629 c=0 +rf467 (\2\:Z3 \3\:Z3) resistor r=0.1083 c=0 +rf468 (\3\:Z3 \4\:Z3) resistor r=0.1123 c=0 +rf469 (\4\:Z3 \5\:Z3) resistor r=0.4382 c=0 +rf470 (\2\:Z3 \6\:Z3) resistor r=0.4386 c=0 +rf471 (\4\:Z3 \7\:Z3) resistor r=0.6387 c=0 +rf472 (\1\:Z2 \2\:Z2) resistor r=0.629 c=0 +rf473 (\2\:Z2 \3\:Z2) resistor r=0.1083 c=0 +rf474 (\3\:Z2 \4\:Z2) resistor r=0.1123 c=0 +rf475 (\4\:Z2 \5\:Z2) resistor r=0.4382 c=0 +rf476 (\2\:Z2 \6\:Z2) resistor r=0.4386 c=0 +rf477 (\4\:Z2 \7\:Z2) resistor r=0.6387 c=0 +rf478 (\17\:net075 \18\:net075) resistor r=0.01 c=0 +rf479 (\17\:net47 \18\:net47) resistor r=0.01 c=0 +rf481 (\6\:X0 \7\:X0) resistor r=2.01 c=0 +rf482 (I14\|net013 \2\:I14\|net013) resistor r=0.2434 c=0 +rf483 (\2\:I14\|net013 \3\:I14\|net013) resistor r=0.3205 c=0 +rf484 (\2\:I14\|net013 \4\:I14\|net013) resistor r=0.5422 c=0 +rf485 (I17\|net013 \2\:I17\|net013) resistor r=0.2434 c=0 +rf486 (\2\:I17\|net013 \3\:I17\|net013) resistor r=0.3205 c=0 +rf487 (\2\:I17\|net013 \4\:I17\|net013) resistor r=0.5422 c=0 +rf488 (\16\:Y3 \17\:Y3) resistor r=2.01 c=0 +rf489 (\16\:Y2 \17\:Y2) resistor r=2.01 c=0 +rf490 (\4\:I8\|I1\|Ai \5\:I8\|I1\|Ai) resistor r=0.2765 c=0 +rf491 (\5\:I8\|I1\|Ai \2\:I8\|I1\|Ai) resistor r=0.04519 c=0 +rf492 (\5\:I8\|I1\|Ai \6\:I8\|I1\|Ai) resistor r=0.7634 c=0 +rf493 (\4\:I7\|I1\|Ai \5\:I7\|I1\|Ai) resistor r=0.2765 c=0 +rf494 (\5\:I7\|I1\|Ai \2\:I7\|I1\|Ai) resistor r=0.04519 c=0 +rf495 (\5\:I7\|I1\|Ai \6\:I7\|I1\|Ai) resistor r=0.7634 c=0 +rf496 (\12\:X0 \20\:X0) resistor r=0.01 c=0 +rf497 (\16\:X0 \21\:X0) resistor r=0.01 c=0 +rf498 (\11\:net0127 \12\:net0127) resistor r=0.2066 c=0 +rf499 (\12\:net0127 \13\:net0127) resistor r=0.6132 c=0 +rf500 (\21\:net0115 \22\:net0115) resistor r=0.6132 c=0 +rf501 (\22\:net0115 \23\:net0115) resistor r=0.2066 c=0 +rf502 (\5\:I25\|net013 \6\:I25\|net013) resistor r=0.236 c=0 +rf503 (\6\:I25\|net013 I25\|net013) resistor r=0.2322 c=0 +rf504 (\6\:I25\|net013 \7\:I25\|net013) resistor r=0.5701 c=0 +rf505 (\5\:I22\|net013 \6\:I22\|net013) resistor r=0.236 c=0 +rf506 (\6\:I22\|net013 I22\|net013) resistor r=0.2322 c=0 +rf507 (\6\:I22\|net013 \7\:I22\|net013) resistor r=0.5701 c=0 +rf508 (\19\:net075 \23\:net075) resistor r=0.01 c=0 +rf509 (\19\:net47 \23\:net47) resistor r=0.01 c=0 +rf510 (\1\:gnd! \2\:gnd!) resistor r=0.5373 c=0 +rf511 (\2\:gnd! \3\:gnd!) resistor r=0.06105 c=0 +rf512 (\3\:gnd! \4\:gnd!) resistor r=0.089 c=0 +rf513 (\4\:gnd! \5\:gnd!) resistor r=0.1325 c=0 +rf514 (\5\:gnd! \6\:gnd!) resistor r=0.0567 c=0 +rf515 (\6\:gnd! \7\:gnd!) resistor r=0.05137 c=0 +rf516 (\7\:gnd! \8\:gnd!) resistor r=0.04013 c=0 +rf517 (\8\:gnd! \9\:gnd!) resistor r=0.1485 c=0 +rf518 (\9\:gnd! \10\:gnd!) resistor r=0.07027 c=0 +rf519 (\10\:gnd! \11\:gnd!) resistor r=0.07573 c=0 +rf520 (\11\:gnd! \12\:gnd!) resistor r=0.1984 c=0 +rf521 (\12\:gnd! \13\:gnd!) resistor r=0.1201 c=0 +rf522 (\13\:gnd! \14\:gnd!) resistor r=0.02927 c=0 +rf523 (\14\:gnd! \15\:gnd!) resistor r=0.03312 c=0 +rf524 (\15\:gnd! \16\:gnd!) resistor r=0.09389 c=0 +rf525 (\16\:gnd! \17\:gnd!) resistor r=0.07629 c=0 +rf526 (\17\:gnd! \18\:gnd!) resistor r=0.05008 c=0 +rf527 (\18\:gnd! \19\:gnd!) resistor r=0.02223 c=0 +rf528 (\19\:gnd! \20\:gnd!) resistor r=0.1485 c=0 +rf529 (\2\:gnd! \21\:gnd!) resistor r=0.4051 c=0 +rf530 (\2\:gnd! \22\:gnd!) resistor r=0.4778 c=0 +rf531 (\3\:gnd! \23\:gnd!) resistor r=0.3083 c=0 +rf532 (\5\:gnd! \24\:gnd!) resistor r=0.4782 c=0 +rf533 (\5\:gnd! \25\:gnd!) resistor r=0.4924 c=0 +rf534 (\6\:gnd! \26\:gnd!) resistor r=0.3585 c=0 +rf535 (\7\:gnd! \27\:gnd!) resistor r=0.3845 c=0 +rf536 (\10\:gnd! \28\:gnd!) resistor r=0.3925 c=0 +rf537 (\10\:gnd! \29\:gnd!) resistor r=0.4802 c=0 +rf538 (\11\:gnd! \30\:gnd!) resistor r=0.44 c=0 +rf539 (\12\:gnd! \31\:gnd!) resistor r=0.3843 c=0 +rf540 (\12\:gnd! \32\:gnd!) resistor r=0.4444 c=0 +rf541 (\13\:gnd! \33\:gnd!) resistor r=0.3833 c=0 +rf542 (\15\:gnd! \34\:gnd!) resistor r=0.3817 c=0 +rf543 (\15\:gnd! \35\:gnd!) resistor r=0.4721 c=0 +rf544 (\16\:gnd! \36\:gnd!) resistor r=0.4967 c=0 +rf545 (\17\:gnd! \37\:gnd!) resistor r=0.3196 c=0 +rf546 (\18\:gnd! \38\:gnd!) resistor r=0.3196 c=0 +rf547 (\20\:gnd! \39\:gnd!) resistor r=0.4346 c=0 +rf548 (\20\:gnd! \40\:gnd!) resistor r=0.486 c=0 +rf549 (\20\:gnd! \41\:gnd!) resistor r=0.1486 c=0 +rf550 (\41\:gnd! \42\:gnd!) resistor r=0.03801 c=0 +rf551 (\42\:gnd! \43\:gnd!) resistor r=0.07419 c=0 +rf552 (\43\:gnd! \44\:gnd!) resistor r=0.3142 c=0 +rf553 (\42\:gnd! \45\:gnd!) resistor r=0.3864 c=0 +rf554 (\43\:gnd! \46\:gnd!) resistor r=0.0911 c=0 +rf555 (\46\:gnd! \47\:gnd!) resistor r=0.06504 c=0 +rf556 (\47\:gnd! \48\:gnd!) resistor r=0.3175 c=0 +rf557 (\47\:gnd! \49\:gnd!) resistor r=0.04775 c=0 +rf558 (\49\:gnd! \50\:gnd!) resistor r=0.4116 c=0 +rf559 (\49\:gnd! \51\:gnd!) resistor r=0.03353 c=0 +rf560 (\51\:gnd! \52\:gnd!) resistor r=0.07914 c=0 +rf561 (\52\:gnd! \53\:gnd!) resistor r=0.05225 c=0 +rf562 (\53\:gnd! \54\:gnd!) resistor r=0.4218 c=0 +rf563 (\49\:gnd! \55\:gnd!) resistor r=0.4813 c=0 +rf564 (\52\:gnd! \56\:gnd!) resistor r=0.3864 c=0 +rf565 (\53\:gnd! \57\:gnd!) resistor r=0.1034 c=0 +rf566 (\57\:gnd! \58\:gnd!) resistor r=0.04537 c=0 +rf567 (\58\:gnd! \59\:gnd!) resistor r=0.05274 c=0 +rf568 (\59\:gnd! \60\:gnd!) resistor r=0.3142 c=0 +rf569 (\53\:gnd! \61\:gnd!) resistor r=0.4674 c=0 +rf570 (\57\:gnd! \62\:gnd!) resistor r=0.3864 c=0 +rf571 (\59\:gnd! \63\:gnd!) resistor r=0.09297 c=0 +rf572 (\63\:gnd! \64\:gnd!) resistor r=0.03064 c=0 +rf573 (\64\:gnd! \65\:gnd!) resistor r=0.3023 c=0 +rf574 (\64\:gnd! \66\:gnd!) resistor r=0.06745 c=0 +rf575 (\66\:gnd! \67\:gnd!) resistor r=0.3835 c=0 +rf576 (\66\:gnd! \68\:gnd!) resistor r=0.04394 c=0 +rf577 (\68\:gnd! \69\:gnd!) resistor r=0.1358 c=0 +rf578 (\69\:gnd! \70\:gnd!) resistor r=0.04148 c=0 +rf579 (\70\:gnd! \71\:gnd!) resistor r=0.4407 c=0 +rf580 (\66\:gnd! \72\:gnd!) resistor r=0.4754 c=0 +rf581 (\69\:gnd! \73\:gnd!) resistor r=0.3833 c=0 +rf582 (\70\:gnd! \74\:gnd!) resistor r=0.1489 c=0 +rf583 (\74\:gnd! \75\:gnd!) resistor r=0.4043 c=0 +rf584 (\74\:gnd! \76\:gnd!) resistor r=0.07477 c=0 +rf585 (\76\:gnd! \77\:gnd!) resistor r=0.3848 c=0 +rf586 (\76\:gnd! \78\:gnd!) resistor r=0.1353 c=0 +rf587 (\78\:gnd! \79\:gnd!) resistor r=0.3869 c=0 +rf588 (\76\:gnd! \80\:gnd!) resistor r=0.47 c=0 +rf589 (\78\:gnd! \81\:gnd!) resistor r=0.0387 c=0 +rf590 (\81\:gnd! \82\:gnd!) resistor r=0.1067 c=0 +rf591 (\78\:gnd! \83\:gnd!) resistor r=0.4452 c=0 +rf592 (\81\:gnd! \84\:gnd!) resistor r=0.3793 c=0 +rf593 (\82\:gnd! \85\:gnd!) resistor r=0.0706 c=0 +rf594 (\85\:gnd! \86\:gnd!) resistor r=0.3122 c=0 +rf595 (\82\:gnd! \87\:gnd!) resistor r=0.4967 c=0 +rf596 (\85\:gnd! \88\:gnd!) resistor r=0.06608 c=0 +rf597 (\88\:gnd! \89\:gnd!) resistor r=0.04684 c=0 +rf598 (\89\:gnd! \90\:gnd!) resistor r=0.306 c=0 +rf599 (\89\:gnd! \91\:gnd!) resistor r=0.09403 c=0 +rf600 (\91\:gnd! \92\:gnd!) resistor r=0.3596 c=0 +rf601 (\91\:gnd! \93\:gnd!) resistor r=0.3451 c=0 +rf602 (\93\:gnd! \94\:gnd!) resistor r=4.7066 c=0 +rf603 (\94\:gnd! \95\:gnd!) resistor r=0.476 c=0 +rf604 (\91\:gnd! \96\:gnd!) resistor r=0.442 c=0 +rf605 (\93\:gnd! \97\:gnd!) resistor r=4.2632 c=0 +rf606 (\97\:gnd! \98\:gnd!) resistor r=4.2744 c=0 +rf607 (\98\:gnd! 0) resistor r=0.4005 c=0 +rf608 (\94\:gnd! \99\:gnd!) resistor r=0.1317 c=0 +rf609 (\99\:gnd! \100\:gnd!) resistor r=0.1396 c=0 +rf610 (\100\:gnd! \101\:gnd!) resistor r=0.52 c=0 +rf611 (\97\:gnd! \102\:gnd!) resistor r=0.3328 c=0 +rf612 (\102\:gnd! \103\:gnd!) resistor r=0.05392 c=0 +rf613 (\103\:gnd! \104\:gnd!) resistor r=0.3949 c=0 +rf614 (\98\:gnd! \105\:gnd!) resistor r=0.359 c=0 +rf615 (\105\:gnd! \106\:gnd!) resistor r=0.09621 c=0 +rf616 (\106\:gnd! \107\:gnd!) resistor r=0.2996 c=0 +rf617 (\100\:gnd! \108\:gnd!) resistor r=0.1085 c=0 +rf618 (\108\:gnd! \109\:gnd!) resistor r=0.3877 c=0 +rf619 (\103\:gnd! \110\:gnd!) resistor r=0.3965 c=0 +rf620 (\103\:gnd! \111\:gnd!) resistor r=0.09221 c=0 +rf621 (\111\:gnd! \112\:gnd!) resistor r=0.3649 c=0 +rf622 (\106\:gnd! \113\:gnd!) resistor r=0.07337 c=0 +rf623 (\113\:gnd! \114\:gnd!) resistor r=0.3083 c=0 +rf624 (\108\:gnd! \115\:gnd!) resistor r=0.03889 c=0 +rf625 (\115\:gnd! \116\:gnd!) resistor r=0.4877 c=0 +rf626 (\111\:gnd! \117\:gnd!) resistor r=0.3954 c=0 +rf627 (\111\:gnd! \118\:gnd!) resistor r=0.09227 c=0 +rf628 (\118\:gnd! \119\:gnd!) resistor r=0.3971 c=0 +rf629 (\113\:gnd! \120\:gnd!) resistor r=0.03456 c=0 +rf630 (\120\:gnd! \121\:gnd!) resistor r=0.1383 c=0 +rf631 (\121\:gnd! \122\:gnd!) resistor r=0.4467 c=0 +rf632 (\115\:gnd! \123\:gnd!) resistor r=0.1292 c=0 +rf633 (\123\:gnd! \124\:gnd!) resistor r=0.3918 c=0 +rf634 (\118\:gnd! \125\:gnd!) resistor r=0.473 c=0 +rf635 (\118\:gnd! \126\:gnd!) resistor r=0.06553 c=0 +rf636 (\126\:gnd! \127\:gnd!) resistor r=0.046 c=0 +rf637 (\127\:gnd! \128\:gnd!) resistor r=0.3896 c=0 +rf638 (\121\:gnd! \129\:gnd!) resistor r=0.04511 c=0 +rf639 (\129\:gnd! \130\:gnd!) resistor r=0.358 c=0 +rf640 (\123\:gnd! \131\:gnd!) resistor r=0.08824 c=0 +rf641 (\131\:gnd! \132\:gnd!) resistor r=0.1508 c=0 +rf642 (\132\:gnd! \133\:gnd!) resistor r=0.04236 c=0 +rf643 (\133\:gnd! \134\:gnd!) resistor r=0.3918 c=0 +rf644 (\127\:gnd! \135\:gnd!) resistor r=0.1014 c=0 +rf645 (\135\:gnd! \136\:gnd!) resistor r=0.3965 c=0 +rf646 (\129\:gnd! \137\:gnd!) resistor r=0.09948 c=0 +rf647 (\137\:gnd! \138\:gnd!) resistor r=0.2186 c=0 +rf648 (\138\:gnd! \139\:gnd!) resistor r=0.3811 c=0 +rf649 (\133\:gnd! \140\:gnd!) resistor r=0.1372 c=0 +rf650 (\135\:gnd! \141\:gnd!) resistor r=0.15 c=0 +rf651 (\141\:gnd! \142\:gnd!) resistor r=0.3196 c=0 +rf652 (\138\:gnd! \143\:gnd!) resistor r=0.07421 c=0 +rf653 (\143\:gnd! \144\:gnd!) resistor r=0.3105 c=0 +rf654 (\140\:gnd! \145\:gnd!) resistor r=0.0255 c=0 +rf655 (\145\:gnd! \146\:gnd!) resistor r=0.3873 c=0 +rf656 (\141\:gnd! \147\:gnd!) resistor r=0.06745 c=0 +rf657 (\147\:gnd! \148\:gnd!) resistor r=0.3617 c=0 +rf658 (\143\:gnd! \149\:gnd!) resistor r=0.07653 c=0 +rf659 (\149\:gnd! \150\:gnd!) resistor r=0.1347 c=0 +rf660 (\150\:gnd! \151\:gnd!) resistor r=0.3038 c=0 +rf661 (\145\:gnd! \152\:gnd!) resistor r=0.1216 c=0 +rf662 (\152\:gnd! \153\:gnd!) resistor r=0.148 c=0 +rf663 (\147\:gnd! \154\:gnd!) resistor r=0.4707 c=0 +rf664 (\147\:gnd! \155\:gnd!) resistor r=0.09352 c=0 +rf665 (\155\:gnd! \156\:gnd!) resistor r=0.3896 c=0 +rf666 (\150\:gnd! \157\:gnd!) resistor r=0.0463 c=0 +rf667 (\157\:gnd! \158\:gnd!) resistor r=0.02722 c=0 +rf668 (\158\:gnd! \159\:gnd!) resistor r=0.3 c=0 +rf669 (\153\:gnd! \160\:gnd!) resistor r=0.02188 c=0 +rf670 (\160\:gnd! \161\:gnd!) resistor r=0.3873 c=0 +rf671 (\155\:gnd! \162\:gnd!) resistor r=0.05615 c=0 +rf672 (\162\:gnd! \163\:gnd!) resistor r=0.3941 c=0 +rf673 (\158\:gnd! \164\:gnd!) resistor r=0.1173 c=0 +rf674 (\164\:gnd! \165\:gnd!) resistor r=0.4044 c=0 +rf675 (\160\:gnd! \166\:gnd!) resistor r=0.1038 c=0 +rf676 (\166\:gnd! \167\:gnd!) resistor r=0.3833 c=0 +rf677 (\162\:gnd! \168\:gnd!) resistor r=0.1077 c=0 +rf678 (\168\:gnd! \169\:gnd!) resistor r=0.3874 c=0 +rf679 (\164\:gnd! \170\:gnd!) resistor r=0.1447 c=0 +rf680 (\170\:gnd! \171\:gnd!) resistor r=0.05704 c=0 +rf681 (\171\:gnd! \172\:gnd!) resistor r=0.3215 c=0 +rf682 (\166\:gnd! \173\:gnd!) resistor r=0.02269 c=0 +rf683 (\168\:gnd! \174\:gnd!) resistor r=0.0715 c=0 +rf684 (\174\:gnd! \175\:gnd!) resistor r=0.05637 c=0 +rf685 (\175\:gnd! \176\:gnd!) resistor r=0.3019 c=0 +rf686 (\171\:gnd! \177\:gnd!) resistor r=0.08887 c=0 +rf687 (\177\:gnd! \178\:gnd!) resistor r=0.06637 c=0 +rf688 (\178\:gnd! \179\:gnd!) resistor r=0.3215 c=0 +rf689 (\173\:gnd! \180\:gnd!) resistor r=0.02879 c=0 +rf690 (\180\:gnd! \181\:gnd!) resistor r=0.3873 c=0 +rf691 (\175\:gnd! \182\:gnd!) resistor r=0.09058 c=0 +rf692 (\182\:gnd! \183\:gnd!) resistor r=0.3708 c=0 +rf693 (\178\:gnd! \184\:gnd!) resistor r=0.06251 c=0 +rf694 (\184\:gnd! \185\:gnd!) resistor r=0.3843 c=0 +rf695 (\180\:gnd! \186\:gnd!) resistor r=0.1034 c=0 +rf696 (\182\:gnd! \187\:gnd!) resistor r=0.07183 c=0 +rf697 (\187\:gnd! \188\:gnd!) resistor r=0.3874 c=0 +rf698 (\184\:gnd! \189\:gnd!) resistor r=0.1469 c=0 +rf699 (\189\:gnd! \190\:gnd!) resistor r=0.4044 c=0 +rf700 (\186\:gnd! \191\:gnd!) resistor r=0.4477 c=0 +rf701 (\186\:gnd! \192\:gnd!) resistor r=0.1503 c=0 +rf702 (\187\:gnd! \193\:gnd!) resistor r=0.04481 c=0 +rf703 (\193\:gnd! \194\:gnd!) resistor r=0.3163 c=0 +rf704 (\189\:gnd! \195\:gnd!) resistor r=0.2039 c=0 +rf705 (\195\:gnd! \196\:gnd!) resistor r=0.4022 c=0 +rf706 (\192\:gnd! \197\:gnd!) resistor r=0.1433 c=0 +rf707 (\197\:gnd! \198\:gnd!) resistor r=0.3873 c=0 +rf708 (\193\:gnd! \199\:gnd!) resistor r=0.02922 c=0 +rf709 (\199\:gnd! \200\:gnd!) resistor r=0.02857 c=0 +rf710 (\200\:gnd! \201\:gnd!) resistor r=0.3834 c=0 +rf711 (\195\:gnd! \202\:gnd!) resistor r=0.1456 c=0 +rf712 (\202\:gnd! \203\:gnd!) resistor r=0.3767 c=0 +rf713 (\197\:gnd! \204\:gnd!) resistor r=0.06184 c=0 +rf714 (\204\:gnd! \205\:gnd!) resistor r=0.109 c=0 +rf715 (\205\:gnd! \206\:gnd!) resistor r=0.3873 c=0 +rf716 (\200\:gnd! \207\:gnd!) resistor r=0.05138 c=0 +rf717 (\207\:gnd! \208\:gnd!) resistor r=0.3874 c=0 +rf718 (\202\:gnd! \209\:gnd!) resistor r=0.06647 c=0 +rf719 (\209\:gnd! \210\:gnd!) resistor r=0.3213 c=0 +rf720 (\205\:gnd! \211\:gnd!) resistor r=0.03833 c=0 +rf721 (\211\:gnd! \212\:gnd!) resistor r=0.148 c=0 +rf722 (\207\:gnd! \213\:gnd!) resistor r=0.06821 c=0 +rf723 (\213\:gnd! \214\:gnd!) resistor r=0.03653 c=0 +rf724 (\214\:gnd! \215\:gnd!) resistor r=0.3929 c=0 +rf725 (\209\:gnd! \216\:gnd!) resistor r=0.07812 c=0 +rf726 (\216\:gnd! \217\:gnd!) resistor r=0.07812 c=0 +rf727 (\217\:gnd! \218\:gnd!) resistor r=0.3213 c=0 +rf728 (\212\:gnd! \219\:gnd!) resistor r=0.09425 c=0 +rf729 (\219\:gnd! \220\:gnd!) resistor r=0.3873 c=0 +rf730 (\214\:gnd! \221\:gnd!) resistor r=0.4741 c=0 +rf731 (\214\:gnd! \222\:gnd!) resistor r=0.09179 c=0 +rf732 (\222\:gnd! \223\:gnd!) resistor r=0.0567 c=0 +rf733 (\223\:gnd! \224\:gnd!) resistor r=0.3197 c=0 +rf734 (\217\:gnd! \225\:gnd!) resistor r=0.06873 c=0 +rf735 (\225\:gnd! \226\:gnd!) resistor r=0.1307 c=0 +rf736 (\226\:gnd! \227\:gnd!) resistor r=0.4022 c=0 +rf737 (\219\:gnd! \228\:gnd!) resistor r=0.0551 c=0 +rf738 (\223\:gnd! \229\:gnd!) resistor r=0.04991 c=0 +rf739 (\229\:gnd! \230\:gnd!) resistor r=0.3197 c=0 +rf740 (\226\:gnd! \231\:gnd!) resistor r=0.1662 c=0 +rf741 (\231\:gnd! \232\:gnd!) resistor r=0.3027 c=0 +rf742 (\228\:gnd! \233\:gnd!) resistor r=0.06004 c=0 +rf743 (\233\:gnd! \234\:gnd!) resistor r=0.3873 c=0 +rf744 (\229\:gnd! \235\:gnd!) resistor r=0.04157 c=0 +rf745 (\235\:gnd! \236\:gnd!) resistor r=0.04519 c=0 +rf746 (\236\:gnd! \237\:gnd!) resistor r=0.3874 c=0 +rf747 (\231\:gnd! \238\:gnd!) resistor r=0.05028 c=0 +rf748 (\238\:gnd! \239\:gnd!) resistor r=0.02337 c=0 +rf749 (\239\:gnd! \240\:gnd!) resistor r=0.3093 c=0 +rf750 (\233\:gnd! \241\:gnd!) resistor r=0.07188 c=0 +rf751 (\236\:gnd! \242\:gnd!) resistor r=0.06896 c=0 +rf752 (\242\:gnd! \243\:gnd!) resistor r=0.3173 c=0 +rf753 (\239\:gnd! \244\:gnd!) resistor r=0.1061 c=0 +rf754 (\244\:gnd! \245\:gnd!) resistor r=0.148 c=0 +rf755 (\245\:gnd! \246\:gnd!) resistor r=0.3515 c=0 +rf756 (\241\:gnd! \247\:gnd!) resistor r=0.442 c=0 +rf757 (\241\:gnd! \248\:gnd!) resistor r=0.08461 c=0 +rf758 (\248\:gnd! \249\:gnd!) resistor r=0.3873 c=0 +rf759 (\242\:gnd! \250\:gnd!) resistor r=0.04495 c=0 +rf760 (\250\:gnd! \251\:gnd!) resistor r=0.3896 c=0 +rf761 (\245\:gnd! \252\:gnd!) resistor r=0.0544 c=0 +rf762 (\252\:gnd! \253\:gnd!) resistor r=0.3085 c=0 +rf763 (\248\:gnd! \254\:gnd!) resistor r=0.06497 c=0 +rf764 (\254\:gnd! \255\:gnd!) resistor r=0.1977 c=0 +rf765 (\250\:gnd! \256\:gnd!) resistor r=0.04402 c=0 +rf766 (\256\:gnd! \257\:gnd!) resistor r=0.1485 c=0 +rf767 (\257\:gnd! \258\:gnd!) resistor r=0.07299 c=0 +rf768 (\258\:gnd! \259\:gnd!) resistor r=0.3788 c=0 +rf769 (\252\:gnd! \260\:gnd!) resistor r=0.09236 c=0 +rf770 (\260\:gnd! \261\:gnd!) resistor r=0.1489 c=0 +rf771 (\261\:gnd! \262\:gnd!) resistor r=0.4122 c=0 +rf772 (\255\:gnd! \263\:gnd!) resistor r=0.02879 c=0 +rf773 (\263\:gnd! \264\:gnd!) resistor r=0.3873 c=0 +rf774 (\258\:gnd! \265\:gnd!) resistor r=0.4741 c=0 +rf775 (\258\:gnd! \266\:gnd!) resistor r=0.06936 c=0 +rf776 (\266\:gnd! \267\:gnd!) resistor r=0.06287 c=0 +rf777 (\267\:gnd! \268\:gnd!) resistor r=0.3949 c=0 +rf778 (\261\:gnd! \269\:gnd!) resistor r=0.03693 c=0 +rf779 (\269\:gnd! \270\:gnd!) resistor r=0.3611 c=0 +rf780 (\263\:gnd! \271\:gnd!) resistor r=0.1186 c=0 +rf781 (\271\:gnd! \272\:gnd!) resistor r=0.1485 c=0 +rf782 (\272\:gnd! \273\:gnd!) resistor r=0.03889 c=0 +rf783 (\273\:gnd! \274\:gnd!) resistor r=0.3844 c=0 +rf784 (\267\:gnd! \275\:gnd!) resistor r=0.4764 c=0 +rf785 (\267\:gnd! \276\:gnd!) resistor r=0.04763 c=0 +rf786 (\276\:gnd! \277\:gnd!) resistor r=0.3962 c=0 +rf787 (\269\:gnd! \278\:gnd!) resistor r=0.09408 c=0 +rf788 (\278\:gnd! \279\:gnd!) resistor r=0.1513 c=0 +rf789 (\279\:gnd! \280\:gnd!) resistor r=0.3627 c=0 +rf790 (\273\:gnd! \281\:gnd!) resistor r=0.1108 c=0 +rf791 (\281\:gnd! \282\:gnd!) resistor r=0.5167 c=0 +rf792 (\276\:gnd! \283\:gnd!) resistor r=0.4722 c=0 +rf793 (\276\:gnd! \284\:gnd!) resistor r=0.03195 c=0 +rf794 (\284\:gnd! \285\:gnd!) resistor r=0.06382 c=0 +rf795 (\285\:gnd! \286\:gnd!) resistor r=0.3896 c=0 +rf796 (\279\:gnd! \287\:gnd!) resistor r=0.3647 c=0 +rf797 (\281\:gnd! \288\:gnd!) resistor r=0.1333 c=0 +rf798 (\288\:gnd! \289\:gnd!) resistor r=0.1508 c=0 +rf799 (\289\:gnd! \290\:gnd!) resistor r=0.5167 c=0 +rf800 (\285\:gnd! \291\:gnd!) resistor r=0.06844 c=0 +rf801 (\291\:gnd! \292\:gnd!) resistor r=0.4133 c=0 +rf802 (\289\:gnd! \293\:gnd!) resistor r=0.521 c=0 +rf803 (\291\:gnd! \294\:gnd!) resistor r=0.1508 c=0 +rf804 (\294\:gnd! \295\:gnd!) resistor r=0.06482 c=0 +rf805 (\295\:gnd! \296\:gnd!) resistor r=0.3936 c=0 +rf806 (\295\:gnd! \297\:gnd!) resistor r=0.4764 c=0 +rf807 (\295\:gnd! \298\:gnd!) resistor r=0.1289 c=0 +rf808 (\298\:gnd! \299\:gnd!) resistor r=0.364 c=0 +rf809 (\298\:gnd! \300\:gnd!) resistor r=0.4713 c=0 +rf810 (\298\:gnd! \301\:gnd!) resistor r=0.09652 c=0 +rf811 (\301\:gnd! \302\:gnd!) resistor r=0.302 c=0 +rf812 (\301\:gnd! \303\:gnd!) resistor r=0.04996 c=0 +rf813 (\303\:gnd! \304\:gnd!) resistor r=0.5113 c=0 +rf814 (\303\:gnd! \305\:gnd!) resistor r=0.1477 c=0 +rf815 (\305\:gnd! \306\:gnd!) resistor r=0.0937 c=0 +rf816 (\306\:gnd! \307\:gnd!) resistor r=0.3575 c=0 +rf817 (\306\:gnd! \308\:gnd!) resistor r=0.0552 c=0 +rf818 (\308\:gnd! \309\:gnd!) resistor r=0.4108 c=0 +rf819 (\308\:gnd! \310\:gnd!) resistor r=0.4821 c=0 +rf820 (\308\:gnd! \311\:gnd!) resistor r=0.09077 c=0 +rf821 (\311\:gnd! \312\:gnd!) resistor r=0.3857 c=0 +rf822 (\311\:gnd! \313\:gnd!) resistor r=0.07145 c=0 +rf823 (\313\:gnd! \314\:gnd!) resistor r=0.05835 c=0 +rf824 (\314\:gnd! \315\:gnd!) resistor r=0.3063 c=0 +rf825 (\314\:gnd! \316\:gnd!) resistor r=0.09091 c=0 +rf826 (\316\:gnd! \317\:gnd!) resistor r=0.3306 c=0 +rf827 (\316\:gnd! \318\:gnd!) resistor r=0.3711 c=0 +rf828 (\316\:gnd! \319\:gnd!) resistor r=0.3343 c=0 +rf829 (Y1 \21\:Y1) resistor r=0.2212 c=0 +rf830 (\21\:Y1 \18\:Y1) resistor r=3.8017 c=0 +rf831 (\18\:Y1 \12\:Y1) resistor r=10.0519 c=0 +rf832 (\12\:Y1 \5\:Y1) resistor r=4.0448 c=0 +rf833 (vdd! \1\:vdd!) resistor r=1.9259 c=0 +rf834 (\1\:vdd! \2\:vdd!) resistor r=4.4079 c=0 +rf835 (\2\:vdd! \3\:vdd!) resistor r=4.3331 c=0 +rf836 (\3\:vdd! \4\:vdd!) resistor r=0.1142 c=0 +rf837 (\4\:vdd! \5\:vdd!) resistor r=0.07026 c=0 +rf838 (\5\:vdd! \6\:vdd!) resistor r=0.1185 c=0 +rf839 (\6\:vdd! \7\:vdd!) resistor r=0.1058 c=0 +rf840 (\7\:vdd! \8\:vdd!) resistor r=0.05382 c=0 +rf841 (\8\:vdd! \9\:vdd!) resistor r=0.05336 c=0 +rf842 (\9\:vdd! \10\:vdd!) resistor r=0.1554 c=0 +rf843 (\10\:vdd! \11\:vdd!) resistor r=0.1068 c=0 +rf844 (\11\:vdd! \12\:vdd!) resistor r=0.0441 c=0 +rf845 (\12\:vdd! \13\:vdd!) resistor r=0.02879 c=0 +rf846 (\13\:vdd! \14\:vdd!) resistor r=0.1886 c=0 +rf847 (\14\:vdd! \15\:vdd!) resistor r=0.07569 c=0 +rf848 (\15\:vdd! \16\:vdd!) resistor r=0.03265 c=0 +rf849 (\16\:vdd! \17\:vdd!) resistor r=0.07166 c=0 +rf850 (\17\:vdd! \18\:vdd!) resistor r=0.02575 c=0 +rf851 (\18\:vdd! \19\:vdd!) resistor r=0.02916 c=0 +rf852 (\19\:vdd! \20\:vdd!) resistor r=0.0265 c=0 +rf853 (\20\:vdd! \21\:vdd!) resistor r=0.1023 c=0 +rf854 (\21\:vdd! \22\:vdd!) resistor r=0.05449 c=0 +rf855 (\22\:vdd! \23\:vdd!) resistor r=0.1069 c=0 +rf856 (\23\:vdd! \24\:vdd!) resistor r=0.05069 c=0 +rf857 (\24\:vdd! \25\:vdd!) resistor r=0.05136 c=0 +rf858 (\25\:vdd! \26\:vdd!) resistor r=0.1725 c=0 +rf859 (\26\:vdd! \27\:vdd!) resistor r=0.05118 c=0 +rf860 (\27\:vdd! \28\:vdd!) resistor r=0.0506 c=0 +rf861 (\28\:vdd! \29\:vdd!) resistor r=0.1064 c=0 +rf862 (\29\:vdd! \30\:vdd!) resistor r=0.05445 c=0 +rf863 (\30\:vdd! \31\:vdd!) resistor r=0.1029 c=0 +rf864 (\31\:vdd! \32\:vdd!) resistor r=0.03453 c=0 +rf865 (\32\:vdd! \33\:vdd!) resistor r=0.03083 c=0 +rf866 (\33\:vdd! \34\:vdd!) resistor r=0.0257 c=0 +rf867 (\34\:vdd! \35\:vdd!) resistor r=0.07181 c=0 +rf868 (\35\:vdd! \36\:vdd!) resistor r=0.03262 c=0 +rf869 (\36\:vdd! \37\:vdd!) resistor r=0.07526 c=0 +rf870 (\37\:vdd! \38\:vdd!) resistor r=0.1245 c=0 +rf871 (\38\:vdd! \39\:vdd!) resistor r=0.06644 c=0 +rf872 (\39\:vdd! \40\:vdd!) resistor r=0.02911 c=0 +rf873 (\40\:vdd! \41\:vdd!) resistor r=0.08239 c=0 +rf874 (\41\:vdd! \42\:vdd!) resistor r=0.07195 c=0 +rf875 (\42\:vdd! \43\:vdd!) resistor r=0.05037 c=0 +rf876 (\43\:vdd! \44\:vdd!) resistor r=0.04978 c=0 +rf877 (\44\:vdd! \45\:vdd!) resistor r=0.1047 c=0 +rf878 (\45\:vdd! \46\:vdd!) resistor r=0.05363 c=0 +rf879 (\46\:vdd! \47\:vdd!) resistor r=0.1009 c=0 +rf880 (\47\:vdd! \48\:vdd!) resistor r=0.02613 c=0 +rf881 (\48\:vdd! \49\:vdd!) resistor r=0.02876 c=0 +rf882 (\49\:vdd! \50\:vdd!) resistor r=0.02535 c=0 +rf883 (\50\:vdd! \51\:vdd!) resistor r=0.07067 c=0 +rf884 (\51\:vdd! \52\:vdd!) resistor r=0.03216 c=0 +rf885 (\52\:vdd! \53\:vdd!) resistor r=0.07448 c=0 +rf886 (\53\:vdd! \54\:vdd!) resistor r=0.1082 c=0 +rf887 (\54\:vdd! \55\:vdd!) resistor r=0.07267 c=0 +rf888 (\55\:vdd! \56\:vdd!) resistor r=0.0317 c=0 +rf889 (\56\:vdd! \57\:vdd!) resistor r=0.06006 c=0 +rf890 (\57\:vdd! \58\:vdd!) resistor r=0.429 c=0 +rf891 (\1\:vdd! \59\:vdd!) resistor r=0.2893 c=0 +rf892 (\59\:vdd! \60\:vdd!) resistor r=0.3835 c=0 +rf893 (\2\:vdd! \61\:vdd!) resistor r=0.08985 c=0 +rf894 (\61\:vdd! \62\:vdd!) resistor r=0.5222 c=0 +rf895 (\3\:vdd! \63\:vdd!) resistor r=0.7491 c=0 +rf896 (\3\:vdd! \64\:vdd!) resistor r=0.7418 c=0 +rf897 (\4\:vdd! \65\:vdd!) resistor r=0.5159 c=0 +rf898 (\4\:vdd! \66\:vdd!) resistor r=0.5159 c=0 +rf899 (\5\:vdd! \67\:vdd!) resistor r=0.4015 c=0 +rf900 (\6\:vdd! \68\:vdd!) resistor r=0.3716 c=0 +rf901 (\7\:vdd! \69\:vdd!) resistor r=0.4979 c=0 +rf902 (\7\:vdd! \70\:vdd!) resistor r=0.468 c=0 +rf903 (\8\:vdd! \71\:vdd!) resistor r=0.3726 c=0 +rf904 (\9\:vdd! \72\:vdd!) resistor r=0.3984 c=0 +rf905 (\10\:vdd! \73\:vdd!) resistor r=0.4004 c=0 +rf906 (\11\:vdd! \74\:vdd!) resistor r=0.3994 c=0 +rf907 (\12\:vdd! \75\:vdd!) resistor r=0.3996 c=0 +rf908 (\13\:vdd! \76\:vdd!) resistor r=0.3997 c=0 +rf909 (\14\:vdd! \77\:vdd!) resistor r=0.3775 c=0 +rf910 (\15\:vdd! \78\:vdd!) resistor r=0.4015 c=0 +rf911 (\16\:vdd! \79\:vdd!) resistor r=0.522 c=0 +rf912 (\17\:vdd! \80\:vdd!) resistor r=0.3972 c=0 +rf913 (\18\:vdd! \81\:vdd!) resistor r=0.3878 c=0 +rf914 (\19\:vdd! \82\:vdd!) resistor r=0.4068 c=0 +rf915 (\20\:vdd! \83\:vdd!) resistor r=0.3805 c=0 +rf916 (\21\:vdd! \84\:vdd!) resistor r=0.521 c=0 +rf917 (\21\:vdd! \85\:vdd!) resistor r=0.5021 c=0 +rf918 (\22\:vdd! \86\:vdd!) resistor r=0.3815 c=0 +rf919 (\23\:vdd! \87\:vdd!) resistor r=0.3815 c=0 +rf920 (\24\:vdd! \88\:vdd!) resistor r=0.3775 c=0 +rf921 (\25\:vdd! \89\:vdd!) resistor r=0.4015 c=0 +rf922 (\26\:vdd! \90\:vdd!) resistor r=0.3994 c=0 +rf923 (\27\:vdd! \91\:vdd!) resistor r=0.3774 c=0 +rf924 (\28\:vdd! \92\:vdd!) resistor r=0.3815 c=0 +rf925 (\29\:vdd! \93\:vdd!) resistor r=0.3815 c=0 +rf926 (\30\:vdd! \94\:vdd!) resistor r=0.521 c=0 +rf927 (\30\:vdd! \95\:vdd!) resistor r=0.5021 c=0 +rf928 (\31\:vdd! \96\:vdd!) resistor r=0.3805 c=0 +rf929 (\32\:vdd! \97\:vdd!) resistor r=0.3968 c=0 +rf930 (\33\:vdd! \98\:vdd!) resistor r=0.3878 c=0 +rf931 (\34\:vdd! \99\:vdd!) resistor r=0.3973 c=0 +rf932 (\35\:vdd! \100\:vdd!) resistor r=0.5236 c=0 +rf933 (\36\:vdd! \101\:vdd!) resistor r=0.3994 c=0 +rf934 (\37\:vdd! \102\:vdd!) resistor r=0.3733 c=0 +rf935 (\38\:vdd! \103\:vdd!) resistor r=0.4019 c=0 +rf936 (\39\:vdd! \104\:vdd!) resistor r=0.4246 c=0 +rf937 (\40\:vdd! \105\:vdd!) resistor r=0.4226 c=0 +rf938 (\41\:vdd! \106\:vdd!) resistor r=0.4019 c=0 +rf939 (\42\:vdd! \107\:vdd!) resistor r=0.3955 c=0 +rf940 (\43\:vdd! \108\:vdd!) resistor r=0.3769 c=0 +rf941 (\44\:vdd! \109\:vdd!) resistor r=0.3809 c=0 +rf942 (\45\:vdd! \110\:vdd!) resistor r=0.3809 c=0 +rf943 (\46\:vdd! \111\:vdd!) resistor r=0.5188 c=0 +rf944 (\46\:vdd! \112\:vdd!) resistor r=0.5043 c=0 +rf945 (\47\:vdd! \113\:vdd!) resistor r=0.3809 c=0 +rf946 (\48\:vdd! \114\:vdd!) resistor r=0.4028 c=0 +rf947 (\49\:vdd! \115\:vdd!) resistor r=0.3882 c=0 +rf948 (\50\:vdd! \116\:vdd!) resistor r=0.3934 c=0 +rf949 (\51\:vdd! \117\:vdd!) resistor r=0.5224 c=0 +rf950 (\52\:vdd! \118\:vdd!) resistor r=0.3975 c=0 +rf951 (\53\:vdd! \119\:vdd!) resistor r=0.3769 c=0 +rf952 (\54\:vdd! \120\:vdd!) resistor r=0.3965 c=0 +rf953 (\55\:vdd! \121\:vdd!) resistor r=0.3965 c=0 +rf954 (\56\:vdd! \122\:vdd!) resistor r=0.3975 c=0 +rf955 (\59\:vdd! \123\:vdd!) resistor r=0.09153 c=0 +rf956 (\123\:vdd! \124\:vdd!) resistor r=0.4738 c=0 +rf957 (\59\:vdd! \125\:vdd!) resistor r=0.4236 c=0 +rf958 (\61\:vdd! \126\:vdd!) resistor r=0.08918 c=0 +rf959 (\126\:vdd! \127\:vdd!) resistor r=0.02324 c=0 +rf960 (\127\:vdd! \128\:vdd!) resistor r=0.5125 c=0 +rf961 (\61\:vdd! \129\:vdd!) resistor r=0.5256 c=0 +rf962 (\123\:vdd! \130\:vdd!) resistor r=0.08497 c=0 +rf963 (\130\:vdd! \131\:vdd!) resistor r=0.4974 c=0 +rf964 (\123\:vdd! \132\:vdd!) resistor r=0.4853 c=0 +rf965 (\127\:vdd! \133\:vdd!) resistor r=0.08278 c=0 +rf966 (\133\:vdd! \134\:vdd!) resistor r=0.1069 c=0 +rf967 (\134\:vdd! \135\:vdd!) resistor r=0.1034 c=0 +rf968 (\135\:vdd! \136\:vdd!) resistor r=0.4972 c=0 +rf969 (\127\:vdd! \137\:vdd!) resistor r=0.5158 c=0 +rf970 (\130\:vdd! \138\:vdd!) resistor r=0.0271 c=0 +rf971 (\138\:vdd! \139\:vdd!) resistor r=0.04574 c=0 +rf972 (\139\:vdd! \140\:vdd!) resistor r=0.3976 c=0 +rf973 (\130\:vdd! \141\:vdd!) resistor r=0.5029 c=0 +rf974 (\133\:vdd! \142\:vdd!) resistor r=0.4829 c=0 +rf975 (\134\:vdd! \143\:vdd!) resistor r=0.4789 c=0 +rf976 (\135\:vdd! \144\:vdd!) resistor r=0.06491 c=0 +rf977 (\144\:vdd! \145\:vdd!) resistor r=0.04205 c=0 +rf978 (\145\:vdd! \146\:vdd!) resistor r=0.3944 c=0 +rf979 (\135\:vdd! \147\:vdd!) resistor r=0.4717 c=0 +rf980 (\139\:vdd! \148\:vdd!) resistor r=0.06326 c=0 +rf981 (\148\:vdd! \149\:vdd!) resistor r=0.04045 c=0 +rf982 (\149\:vdd! \150\:vdd!) resistor r=0.5014 c=0 +rf983 (\144\:vdd! \151\:vdd!) resistor r=0.4564 c=0 +rf984 (\145\:vdd! \152\:vdd!) resistor r=0.06014 c=0 +rf985 (\152\:vdd! \153\:vdd!) resistor r=0.0715 c=0 +rf986 (\153\:vdd! \154\:vdd!) resistor r=0.03861 c=0 +rf987 (\154\:vdd! \155\:vdd!) resistor r=0.06161 c=0 +rf988 (\155\:vdd! \156\:vdd!) resistor r=0.02915 c=0 +rf989 (\156\:vdd! \157\:vdd!) resistor r=0.4154 c=0 +rf990 (\148\:vdd! \158\:vdd!) resistor r=0.4621 c=0 +rf991 (\149\:vdd! \159\:vdd!) resistor r=0.1028 c=0 +rf992 (\159\:vdd! \160\:vdd!) resistor r=0.06303 c=0 +rf993 (\160\:vdd! \161\:vdd!) resistor r=0.05368 c=0 +rf994 (\161\:vdd! \162\:vdd!) resistor r=0.05529 c=0 +rf995 (\162\:vdd! \163\:vdd!) resistor r=0.52 c=0 +rf996 (\149\:vdd! \164\:vdd!) resistor r=0.467 c=0 +rf997 (\153\:vdd! \165\:vdd!) resistor r=0.3985 c=0 +rf998 (\155\:vdd! \166\:vdd!) resistor r=0.4154 c=0 +rf999 (\156\:vdd! \167\:vdd!) resistor r=0.04924 c=0 +rf1000 (\167\:vdd! \168\:vdd!) resistor r=0.1599 c=0 +rf1001 (\168\:vdd! \169\:vdd!) resistor r=0.07474 c=0 +rf1002 (\169\:vdd! \170\:vdd!) resistor r=0.3985 c=0 +rf1003 (\159\:vdd! \171\:vdd!) resistor r=0.3658 c=0 +rf1004 (\161\:vdd! \172\:vdd!) resistor r=0.4003 c=0 +rf1005 (\162\:vdd! \173\:vdd!) resistor r=0.1145 c=0 +rf1006 (\173\:vdd! \174\:vdd!) resistor r=0.4992 c=0 +rf1007 (\162\:vdd! \175\:vdd!) resistor r=0.5011 c=0 +rf1008 (\167\:vdd! \176\:vdd!) resistor r=0.3985 c=0 +rf1009 (\168\:vdd! \177\:vdd!) resistor r=0.3768 c=0 +rf1010 (\169\:vdd! \178\:vdd!) resistor r=0.03227 c=0 +rf1011 (\178\:vdd! \179\:vdd!) resistor r=0.07091 c=0 +rf1012 (\179\:vdd! \180\:vdd!) resistor r=0.3944 c=0 +rf1013 (\173\:vdd! \181\:vdd!) resistor r=0.11 c=0 +rf1014 (\181\:vdd! \182\:vdd!) resistor r=0.01688 c=0 +rf1015 (\182\:vdd! \183\:vdd!) resistor r=0.02859 c=0 +rf1016 (\183\:vdd! \184\:vdd!) resistor r=0.4171 c=0 +rf1017 (\173\:vdd! \185\:vdd!) resistor r=0.5267 c=0 +rf1018 (\178\:vdd! \186\:vdd!) resistor r=0.5222 c=0 +rf1019 (\179\:vdd! \187\:vdd!) resistor r=0.02544 c=0 +rf1020 (\187\:vdd! \188\:vdd!) resistor r=0.02894 c=0 +rf1021 (\188\:vdd! \189\:vdd!) resistor r=0.4059 c=0 +rf1022 (\182\:vdd! \190\:vdd!) resistor r=0.4193 c=0 +rf1023 (\183\:vdd! \191\:vdd!) resistor r=0.04829 c=0 +rf1024 (\191\:vdd! \192\:vdd!) resistor r=0.1035 c=0 +rf1025 (\192\:vdd! \193\:vdd!) resistor r=0.05234 c=0 +rf1026 (\193\:vdd! \194\:vdd!) resistor r=0.07331 c=0 +rf1027 (\194\:vdd! \195\:vdd!) resistor r=0.4003 c=0 +rf1028 (\187\:vdd! \196\:vdd!) resistor r=0.3881 c=0 +rf1029 (\188\:vdd! \197\:vdd!) resistor r=0.02627 c=0 +rf1030 (\197\:vdd! \198\:vdd!) resistor r=0.02216 c=0 +rf1031 (\198\:vdd! \199\:vdd!) resistor r=0.07917 c=0 +rf1032 (\199\:vdd! \200\:vdd!) resistor r=0.5204 c=0 +rf1033 (\191\:vdd! \201\:vdd!) resistor r=0.4025 c=0 +rf1034 (\192\:vdd! \202\:vdd!) resistor r=0.4025 c=0 +rf1035 (\193\:vdd! \203\:vdd!) resistor r=0.3697 c=0 +rf1036 (\194\:vdd! \204\:vdd!) resistor r=0.03166 c=0 +rf1037 (\204\:vdd! \205\:vdd!) resistor r=0.06955 c=0 +rf1038 (\205\:vdd! \206\:vdd!) resistor r=0.3961 c=0 +rf1039 (\197\:vdd! \207\:vdd!) resistor r=0.3808 c=0 +rf1040 (\199\:vdd! \208\:vdd!) resistor r=0.01667 c=0 +rf1041 (\208\:vdd! \209\:vdd!) resistor r=0.03729 c=0 +rf1042 (\209\:vdd! \210\:vdd!) resistor r=0.1055 c=0 +rf1043 (\210\:vdd! \211\:vdd!) resistor r=0.05007 c=0 +rf1044 (\211\:vdd! \212\:vdd!) resistor r=0.05073 c=0 +rf1045 (\212\:vdd! \213\:vdd!) resistor r=0.3985 c=0 +rf1046 (\199\:vdd! \214\:vdd!) resistor r=0.5026 c=0 +rf1047 (\204\:vdd! \215\:vdd!) resistor r=0.511 c=0 +rf1048 (\205\:vdd! \216\:vdd!) resistor r=0.02496 c=0 +rf1049 (\216\:vdd! \217\:vdd!) resistor r=0.02839 c=0 +rf1050 (\217\:vdd! \218\:vdd!) resistor r=0.4076 c=0 +rf1051 (\209\:vdd! \219\:vdd!) resistor r=0.3808 c=0 +rf1052 (\210\:vdd! \220\:vdd!) resistor r=0.3808 c=0 +rf1053 (\211\:vdd! \221\:vdd!) resistor r=0.3768 c=0 +rf1054 (\212\:vdd! \222\:vdd!) resistor r=0.1583 c=0 +rf1055 (\222\:vdd! \223\:vdd!) resistor r=0.03795 c=0 +rf1056 (\223\:vdd! \224\:vdd!) resistor r=0.3997 c=0 +rf1057 (\216\:vdd! \225\:vdd!) resistor r=0.3809 c=0 +rf1058 (\217\:vdd! \226\:vdd!) resistor r=0.02577 c=0 +rf1059 (\226\:vdd! \227\:vdd!) resistor r=0.08626 c=0 +rf1060 (\227\:vdd! \228\:vdd!) resistor r=0.444 c=0 +rf1061 (\223\:vdd! \229\:vdd!) resistor r=0.05073 c=0 +rf1062 (\229\:vdd! \230\:vdd!) resistor r=0.05007 c=0 +rf1063 (\230\:vdd! \231\:vdd!) resistor r=0.1055 c=0 +rf1064 (\231\:vdd! \232\:vdd!) resistor r=0.05397 c=0 +rf1065 (\232\:vdd! \233\:vdd!) resistor r=0.5215 c=0 +rf1066 (\226\:vdd! \234\:vdd!) resistor r=0.3736 c=0 +rf1067 (\227\:vdd! \235\:vdd!) resistor r=0.06722 c=0 +rf1068 (\235\:vdd! \236\:vdd!) resistor r=0.1035 c=0 +rf1069 (\236\:vdd! \237\:vdd!) resistor r=0.04912 c=0 +rf1070 (\237\:vdd! \238\:vdd!) resistor r=0.04976 c=0 +rf1071 (\238\:vdd! \239\:vdd!) resistor r=0.4003 c=0 +rf1072 (\227\:vdd! \240\:vdd!) resistor r=0.4204 c=0 +rf1073 (\229\:vdd! \241\:vdd!) resistor r=0.3757 c=0 +rf1074 (\230\:vdd! \242\:vdd!) resistor r=0.3797 c=0 +rf1075 (\231\:vdd! \243\:vdd!) resistor r=0.3797 c=0 +rf1076 (\232\:vdd! \244\:vdd!) resistor r=0.0772 c=0 +rf1077 (\244\:vdd! \245\:vdd!) resistor r=0.02413 c=0 +rf1078 (\245\:vdd! \246\:vdd!) resistor r=0.02627 c=0 +rf1079 (\246\:vdd! \247\:vdd!) resistor r=0.407 c=0 +rf1080 (\232\:vdd! \248\:vdd!) resistor r=0.5015 c=0 +rf1081 (\235\:vdd! \249\:vdd!) resistor r=0.3736 c=0 +rf1082 (\236\:vdd! \250\:vdd!) resistor r=0.3736 c=0 +rf1083 (\237\:vdd! \251\:vdd!) resistor r=0.3697 c=0 +rf1084 (\238\:vdd! \252\:vdd!) resistor r=0.08109 c=0 +rf1085 (\252\:vdd! \253\:vdd!) resistor r=0.03142 c=0 +rf1086 (\253\:vdd! \254\:vdd!) resistor r=0.4025 c=0 +rf1087 (\245\:vdd! \255\:vdd!) resistor r=0.3797 c=0 +rf1088 (\246\:vdd! \256\:vdd!) resistor r=0.02894 c=0 +rf1089 (\256\:vdd! \257\:vdd!) resistor r=0.02544 c=0 +rf1090 (\257\:vdd! \258\:vdd!) resistor r=0.3954 c=0 +rf1091 (\253\:vdd! \259\:vdd!) resistor r=0.04976 c=0 +rf1092 (\259\:vdd! \260\:vdd!) resistor r=0.04912 c=0 +rf1093 (\260\:vdd! \261\:vdd!) resistor r=0.1035 c=0 +rf1094 (\261\:vdd! \262\:vdd!) resistor r=0.039 c=0 +rf1095 (\262\:vdd! \263\:vdd!) resistor r=0.4719 c=0 +rf1096 (\256\:vdd! \264\:vdd!) resistor r=0.387 c=0 +rf1097 (\257\:vdd! \265\:vdd!) resistor r=0.0506 c=0 +rf1098 (\265\:vdd! \266\:vdd!) resistor r=0.02031 c=0 +rf1099 (\266\:vdd! \267\:vdd!) resistor r=0.03227 c=0 +rf1100 (\267\:vdd! \268\:vdd!) resistor r=0.3997 c=0 +rf1101 (\259\:vdd! \269\:vdd!) resistor r=0.3675 c=0 +rf1102 (\260\:vdd! \270\:vdd!) resistor r=0.3714 c=0 +rf1103 (\261\:vdd! \271\:vdd!) resistor r=0.3714 c=0 +rf1104 (\262\:vdd! \272\:vdd!) resistor r=0.03309 c=0 +rf1105 (\272\:vdd! \273\:vdd!) resistor r=0.07884 c=0 +rf1106 (\273\:vdd! \274\:vdd!) resistor r=0.0398 c=0 +rf1107 (\274\:vdd! \275\:vdd!) resistor r=0.457 c=0 +rf1108 (\262\:vdd! \276\:vdd!) resistor r=0.469 c=0 +rf1109 (\266\:vdd! \277\:vdd!) resistor r=0.5205 c=0 +rf1110 (\267\:vdd! \278\:vdd!) resistor r=0.07474 c=0 +rf1111 (\278\:vdd! \279\:vdd!) resistor r=0.1343 c=0 +rf1112 (\279\:vdd! \280\:vdd!) resistor r=0.07645 c=0 +rf1113 (\280\:vdd! \281\:vdd!) resistor r=0.5178 c=0 +rf1114 (\273\:vdd! \282\:vdd!) resistor r=0.3714 c=0 +rf1115 (\274\:vdd! \283\:vdd!) resistor r=0.0406 c=0 +rf1116 (\283\:vdd! \284\:vdd!) resistor r=0.3983 c=0 +rf1117 (\274\:vdd! \285\:vdd!) resistor r=0.4394 c=0 +rf1118 (\278\:vdd! \286\:vdd!) resistor r=0.3757 c=0 +rf1119 (\279\:vdd! \287\:vdd!) resistor r=0.3997 c=0 +rf1120 (\280\:vdd! \288\:vdd!) resistor r=0.1145 c=0 +rf1121 (\288\:vdd! \289\:vdd!) resistor r=0.07545 c=0 +rf1122 (\289\:vdd! \290\:vdd!) resistor r=0.3985 c=0 +rf1123 (\280\:vdd! \291\:vdd!) resistor r=0.5178 c=0 +rf1124 (\283\:vdd! \292\:vdd!) resistor r=0.06955 c=0 +rf1125 (\292\:vdd! \293\:vdd!) resistor r=0.03166 c=0 +rf1126 (\293\:vdd! \294\:vdd!) resistor r=0.4025 c=0 +rf1127 (\288\:vdd! \295\:vdd!) resistor r=0.4804 c=0 +rf1128 (\289\:vdd! \296\:vdd!) resistor r=0.05073 c=0 +rf1129 (\296\:vdd! \297\:vdd!) resistor r=0.05007 c=0 +rf1130 (\297\:vdd! \298\:vdd!) resistor r=0.1055 c=0 +rf1131 (\298\:vdd! \299\:vdd!) resistor r=0.05397 c=0 +rf1132 (\299\:vdd! \300\:vdd!) resistor r=0.5204 c=0 +rf1133 (\292\:vdd! \301\:vdd!) resistor r=0.5076 c=0 +rf1134 (\293\:vdd! \302\:vdd!) resistor r=0.07331 c=0 +rf1135 (\302\:vdd! \303\:vdd!) resistor r=0.1136 c=0 +rf1136 (\303\:vdd! \304\:vdd!) resistor r=0.06973 c=0 +rf1137 (\304\:vdd! \305\:vdd!) resistor r=0.02618 c=0 +rf1138 (\305\:vdd! \306\:vdd!) resistor r=0.4025 c=0 +rf1139 (\296\:vdd! \307\:vdd!) resistor r=0.3768 c=0 +rf1140 (\297\:vdd! \308\:vdd!) resistor r=0.3808 c=0 +rf1141 (\298\:vdd! \309\:vdd!) resistor r=0.3808 c=0 +rf1142 (\299\:vdd! \310\:vdd!) resistor r=0.06371 c=0 +rf1143 (\310\:vdd! \311\:vdd!) resistor r=0.03762 c=0 +rf1144 (\311\:vdd! \312\:vdd!) resistor r=0.02627 c=0 +rf1145 (\312\:vdd! \313\:vdd!) resistor r=0.4059 c=0 +rf1146 (\299\:vdd! \314\:vdd!) resistor r=0.5026 c=0 +rf1147 (\302\:vdd! \315\:vdd!) resistor r=0.3675 c=0 +rf1148 (\303\:vdd! \316\:vdd!) resistor r=0.4014 c=0 +rf1149 (\304\:vdd! \317\:vdd!) resistor r=0.4044 c=0 +rf1150 (\305\:vdd! \318\:vdd!) resistor r=0.09561 c=0 +rf1151 (\318\:vdd! \319\:vdd!) resistor r=0.0604 c=0 +rf1152 (\319\:vdd! \320\:vdd!) resistor r=0.4159 c=0 +rf1153 (\311\:vdd! \321\:vdd!) resistor r=0.3808 c=0 +rf1154 (\312\:vdd! \322\:vdd!) resistor r=0.02894 c=0 +rf1155 (\322\:vdd! \323\:vdd!) resistor r=0.02544 c=0 +rf1156 (\323\:vdd! \324\:vdd!) resistor r=0.3944 c=0 +rf1157 (\318\:vdd! \325\:vdd!) resistor r=0.4861 c=0 +rf1158 (\319\:vdd! \326\:vdd!) resistor r=0.02853 c=0 +rf1159 (\326\:vdd! \327\:vdd!) resistor r=0.03782 c=0 +rf1160 (\327\:vdd! \328\:vdd!) resistor r=0.0281 c=0 +rf1161 (\328\:vdd! \329\:vdd!) resistor r=0.02813 c=0 +rf1162 (\329\:vdd! \330\:vdd!) resistor r=0.4038 c=0 +rf1163 (\322\:vdd! \331\:vdd!) resistor r=0.3881 c=0 +rf1164 (\323\:vdd! \332\:vdd!) resistor r=0.05784 c=0 +rf1165 (\332\:vdd! \333\:vdd!) resistor r=0.04585 c=0 +rf1166 (\333\:vdd! \334\:vdd!) resistor r=0.3985 c=0 +rf1167 (\326\:vdd! \335\:vdd!) resistor r=0.4148 c=0 +rf1168 (\328\:vdd! \336\:vdd!) resistor r=0.4027 c=0 +rf1169 (\329\:vdd! \337\:vdd!) resistor r=0.06649 c=0 +rf1170 (\337\:vdd! \338\:vdd!) resistor r=0.1013 c=0 +rf1171 (\338\:vdd! \339\:vdd!) resistor r=0.1159 c=0 +rf1172 (\339\:vdd! \340\:vdd!) resistor r=0.5024 c=0 +rf1173 (\332\:vdd! \341\:vdd!) resistor r=0.617 c=0 +rf1174 (\333\:vdd! \342\:vdd!) resistor r=0.07474 c=0 +rf1175 (\342\:vdd! \343\:vdd!) resistor r=0.1076 c=0 +rf1176 (\343\:vdd! \344\:vdd!) resistor r=0.07294 c=0 +rf1177 (\344\:vdd! \345\:vdd!) resistor r=0.03281 c=0 +rf1178 (\345\:vdd! \346\:vdd!) resistor r=0.3985 c=0 +rf1179 (\337\:vdd! \347\:vdd!) resistor r=0.5065 c=0 +rf1180 (\338\:vdd! \348\:vdd!) resistor r=0.4589 c=0 +rf1181 (\339\:vdd! \349\:vdd!) resistor r=0.04944 c=0 +rf1182 (\349\:vdd! \350\:vdd!) resistor r=0.04887 c=0 +rf1183 (\350\:vdd! \351\:vdd!) resistor r=0.4238 c=0 +rf1184 (\339\:vdd! \352\:vdd!) resistor r=0.4635 c=0 +rf1185 (\342\:vdd! \353\:vdd!) resistor r=0.3768 c=0 +rf1186 (\343\:vdd! \354\:vdd!) resistor r=0.4019 c=0 +rf1187 (\344\:vdd! \355\:vdd!) resistor r=0.4019 c=0 +rf1188 (\345\:vdd! \356\:vdd!) resistor r=0.06262 c=0 +rf1189 (\349\:vdd! \357\:vdd!) resistor r=0.49 c=0 +rf1190 (\350\:vdd! \358\:vdd!) resistor r=0.1152 c=0 +rf1191 (\358\:vdd! \359\:vdd!) resistor r=0.4926 c=0 +rf1192 (\356\:vdd! \360\:vdd!) resistor r=0.4309 c=0 +rf1193 (\358\:vdd! \361\:vdd!) resistor r=0.02438 c=0 +rf1194 (\361\:vdd! \362\:vdd!) resistor r=0.04862 c=0 +rf1195 (\362\:vdd! \363\:vdd!) resistor r=0.5103 c=0 +rf1196 (\358\:vdd! \364\:vdd!) resistor r=0.5128 c=0 +rf1197 (\362\:vdd! \365\:vdd!) resistor r=0.07402 c=0 +rf1198 (\365\:vdd! \366\:vdd!) resistor r=0.0174 c=0 +rf1199 (\366\:vdd! \367\:vdd!) resistor r=0.4537 c=0 +rf1200 (\362\:vdd! \368\:vdd!) resistor r=0.5159 c=0 +rf1201 (\366\:vdd! \369\:vdd!) resistor r=0.5053 c=0 +rg1 (\7\:X3 \8\:X3) resistor r=91.5933 c=0 +rg2 (\8\:X3 \2\:X3) resistor r=3.7604 c=0 +rg3 (\8\:X3 \9\:X3) resistor r=62.0099 c=0 +rg4 (\10\:X3 \11\:X3) resistor r=91.5933 c=0 +rg5 (\11\:X3 \4\:X3) resistor r=3.7604 c=0 +rg6 (\11\:X3 \12\:X3) resistor r=62.0099 c=0 +rg7 (\13\:X3 \14\:X3) resistor r=91.5933 c=0 +rg8 (\14\:X3 \6\:X3) resistor r=3.7604 c=0 +rg9 (\14\:X3 \15\:X3) resistor r=62.0099 c=0 +rg10 (\1\:Y3 \2\:Y3) resistor r=3.7604 c=0 +rg11 (\2\:Y3 \3\:Y3) resistor r=62.0099 c=0 +rg12 (\2\:Y3 \4\:Y3) resistor r=91.5933 c=0 +rg13 (\1\:Y2 \2\:Y2) resistor r=3.7604 c=0 +rg14 (\2\:Y2 \3\:Y2) resistor r=62.0099 c=0 +rg15 (\2\:Y2 \4\:Y2) resistor r=91.5933 c=0 +rg16 (\1\:X0 \2\:X0) resistor r=3.7604 c=0 +rg17 (\2\:X0 \3\:X0) resistor r=91.5933 c=0 +rg18 (\2\:X0 \4\:X0) resistor r=62.0099 c=0 +rg20 (\2\:Y1 \3\:Y1) resistor r=62.0099 c=0 +rg21 (\2\:Y1 \4\:Y1) resistor r=91.5933 c=0 +rg22 (\4\:Y1 \5\:Y1) resistor r=134.735 c=0 +rg23 (\5\:I27\|net013 \6\:I27\|net013) resistor r=37.6755 c=0 +rg24 (\6\:I27\|net013 I27\|net013) resistor r=19.7812 c=0 +rg25 (\6\:I27\|net013 \7\:I27\|net013) resistor r=115.592 c=0 +rg26 (\5\:I20\|net013 \6\:I20\|net013) resistor r=37.6755 c=0 +rg27 (\6\:I20\|net013 I20\|net013) resistor r=19.7812 c=0 +rg28 (\6\:I20\|net013 \7\:I20\|net013) resistor r=115.592 c=0 +rg29 (\5\:I15\|net013 \6\:I15\|net013) resistor r=115.592 c=0 +rg30 (\6\:I15\|net013 I15\|net013) resistor r=19.7812 c=0 +rg31 (\6\:I15\|net013 \7\:I15\|net013) resistor r=37.6755 c=0 +rg32 (\5\:I19\|net013 \6\:I19\|net013) resistor r=37.6755 c=0 +rg33 (\6\:I19\|net013 I19\|net013) resistor r=19.7812 c=0 +rg34 (\6\:I19\|net013 \7\:I19\|net013) resistor r=115.592 c=0 +rg35 (\6\:net090 \7\:net090) resistor r=132.954 c=0 +rg36 (\7\:net090 \8\:net090) resistor r=83.7878 c=0 +rg37 (\7\:net090 net090) resistor r=15.5249 c=0 +rg38 (\6\:net13 \7\:net13) resistor r=132.954 c=0 +rg39 (\7\:net13 \8\:net13) resistor r=83.7878 c=0 +rg40 (\7\:net13 net13) resistor r=15.5249 c=0 +rg41 (I5\|I3\|net013 \2\:I5\|I3\|net013) resistor r=3.7604 c=0 +rg42 (\2\:I5\|I3\|net013 \3\:I5\|I3\|net013) resistor r=109.302 c=0 +rg43 (\2\:I5\|I3\|net013 \4\:I5\|I3\|net013) resistor r=43.2599 c=0 +rg44 (I4\|I4\|Bi \2\:I4\|I4\|Bi) resistor r=3.4479 c=0 +rg45 (\2\:I4\|I4\|Bi \3\:I4\|I4\|Bi) resistor r=70.5516 c=0 +rg46 (\2\:I4\|I4\|Bi \4\:I4\|I4\|Bi) resistor r=68.2599 c=0 +rg47 (\4\:I4\|I4\|Ai \5\:I4\|I4\|Ai) resistor r=426.762 c=0 +rg48 (\5\:I4\|I4\|Ai \3\:I4\|I4\|Ai) resistor r=295.399 c=0 +rg49 (I9\|I4\|Bi \2\:I9\|I4\|Bi) resistor r=3.4479 c=0 +rg50 (\2\:I9\|I4\|Bi \3\:I9\|I4\|Bi) resistor r=70.5516 c=0 +rg51 (\2\:I9\|I4\|Bi \4\:I9\|I4\|Bi) resistor r=68.2599 c=0 +rg52 (\4\:I9\|I4\|Ai \5\:I9\|I4\|Ai) resistor r=426.762 c=0 +rg53 (\5\:I9\|I4\|Ai \3\:I9\|I4\|Ai) resistor r=295.399 c=0 +rg54 (\9\:net090 \10\:net090) resistor r=68.6766 c=0 +rg55 (\10\:net090 \11\:net090) resistor r=39.0198 c=0 +rg56 (\11\:net090 \12\:net090) resistor r=3.7604 c=0 +rg57 (\12\:net090 \13\:net090) resistor r=42.4747 c=0 +rg58 (\13\:net090 \14\:net090) resistor r=51.4263 c=0 +rg59 (\10\:net090 \15\:net090) resistor r=3.6562 c=0 +rg60 (\11\:net090 \16\:net090) resistor r=47.6349 c=0 +rg61 (\13\:net090 \17\:net090) resistor r=106.01 c=0 +rg62 (\9\:net13 \10\:net13) resistor r=68.6766 c=0 +rg63 (\10\:net13 \11\:net13) resistor r=39.0198 c=0 +rg64 (\11\:net13 \12\:net13) resistor r=3.7604 c=0 +rg65 (\12\:net13 \13\:net13) resistor r=42.4747 c=0 +rg66 (\13\:net13 \14\:net13) resistor r=51.4263 c=0 +rg67 (\10\:net13 \15\:net13) resistor r=3.6562 c=0 +rg68 (\11\:net13 \16\:net13) resistor r=47.6349 c=0 +rg69 (\13\:net13 \17\:net13) resistor r=106.01 c=0 +rg70 (\5\:I5\|I1\|Bi \6\:I5\|I1\|Bi) resistor r=53.0516 c=0 +rg71 (\6\:I5\|I1\|Bi \4\:I5\|I1\|Bi) resistor r=3.6562 c=0 +rg72 (\6\:I5\|I1\|Bi \7\:I5\|I1\|Bi) resistor r=84.0933 c=0 +rg73 (\7\:net19 \9\:net19) resistor r=3.7604 c=0 +rg74 (\9\:net19 \10\:net19) resistor r=47.6349 c=0 +rg75 (\10\:net19 \11\:net19) resistor r=149.112 c=0 +rg76 (\11\:net19 \12\:net19) resistor r=237.862 c=0 +rg77 (\12\:net19 \13\:net19) resistor r=167.131 c=0 +rg78 (\9\:net19 \14\:net19) resistor r=109.093 c=0 +rg79 (\11\:net19 \15\:net19) resistor r=54.2235 c=0 +rg80 (\15\:net19 \16\:net19) resistor r=140.208 c=0 +rg81 (\2\:net16 \4\:net16) resistor r=3.7604 c=0 +rg82 (\4\:net16 \5\:net16) resistor r=47.6349 c=0 +rg83 (\5\:net16 \6\:net16) resistor r=149.112 c=0 +rg84 (\6\:net16 \7\:net16) resistor r=237.862 c=0 +rg85 (\7\:net16 \8\:net16) resistor r=167.131 c=0 +rg86 (\4\:net16 \9\:net16) resistor r=109.093 c=0 +rg87 (\6\:net16 \10\:net16) resistor r=54.2235 c=0 +rg88 (\10\:net16 \11\:net16) resistor r=140.208 c=0 +rg89 (\10\:I4\|net3 \11\:I4\|net3) resistor r=97.8433 c=0 +rg90 (\11\:I4\|net3 \9\:I4\|net3) resistor r=3.7604 c=0 +rg91 (\11\:I4\|net3 \12\:I4\|net3) resistor r=40.9683 c=0 +rg92 (\10\:I9\|net3 \11\:I9\|net3) resistor r=97.8433 c=0 +rg93 (\11\:I9\|net3 \9\:I9\|net3) resistor r=3.7604 c=0 +rg94 (\11\:I9\|net3 \12\:I9\|net3) resistor r=40.9683 c=0 +rg95 (\2\:net55 \7\:net55) resistor r=3.7604 c=0 +rg96 (\7\:net55 \8\:net55) resistor r=73.0516 c=0 +rg97 (\7\:net55 \9\:net55) resistor r=79.5099 c=0 +rg98 (\8\:net55 \5\:net55) resistor r=77.3221 c=0 +rg99 (\5\:I4\|net1 \6\:I4\|net1) resistor r=80.5516 c=0 +rg100 (\6\:I4\|net1 \4\:I4\|net1) resistor r=3.5521 c=0 +rg101 (\6\:I4\|net1 \7\:I4\|net1) resistor r=76.1766 c=0 +rg102 (\5\:I9\|net1 \6\:I9\|net1) resistor r=80.5516 c=0 +rg103 (\6\:I9\|net1 \4\:I9\|net1) resistor r=3.5521 c=0 +rg104 (\6\:I9\|net1 \7\:I9\|net1) resistor r=76.1766 c=0 +rg105 (\21\:X3 \22\:X3) resistor r=91.5933 c=0 +rg106 (\22\:X3 \20\:X3) resistor r=3.7604 c=0 +rg107 (\22\:X3 \23\:X3) resistor r=62.0099 c=0 +rg108 (\10\:net55 \11\:net55) resistor r=47.3355 c=0 +rg109 (\11\:net55 \12\:net55) resistor r=120.434 c=0 +rg110 (\12\:net55 \13\:net55) resistor r=41.6577 c=0 +rg111 (\11\:net55 \14\:net55) resistor r=7.4762 c=0 +rg112 (\12\:net55 \3\:net55) resistor r=32.1097 c=0 +rg113 (I4\|net6 \2\:I4\|net6) resistor r=3.5521 c=0 +rg114 (\2\:I4\|net6 \3\:I4\|net6) resistor r=77.0099 c=0 +rg115 (\2\:I4\|net6 \4\:I4\|net6) resistor r=79.7183 c=0 +rg116 (I9\|net6 \2\:I9\|net6) resistor r=3.5521 c=0 +rg117 (\2\:I9\|net6 \3\:I9\|net6) resistor r=77.0099 c=0 +rg118 (\2\:I9\|net6 \4\:I9\|net6) resistor r=79.7183 c=0 +rg119 (\6\:net093 \7\:net093) resistor r=174.262 c=0 +rg120 (\7\:net093 \8\:net093) resistor r=165.153 c=0 +rg121 (\8\:net093 \9\:net093) resistor r=116.403 c=0 +rg122 (\9\:net093 \10\:net093) resistor r=138.542 c=0 +rg123 (\8\:net093 \11\:net093) resistor r=135.474 c=0 +rg124 (\11\:net093 \12\:net093) resistor r=72.4266 c=0 +rg125 (\12\:net093 \4\:net093) resistor r=3.7604 c=0 +rg126 (\12\:net093 \13\:net093) resistor r=80.1349 c=0 +rg127 (I5\|I1\|Ai \2\:I5\|I1\|Ai) resistor r=77.852 c=0 +rg128 (\2\:I5\|I1\|Ai \3\:I5\|I1\|Ai) resistor r=333.882 c=0 +rg129 (\16\:net55 \17\:net55) resistor r=3.7604 c=0 +rg130 (\17\:net55 \18\:net55) resistor r=55.3433 c=0 +rg131 (\17\:net55 \19\:net55) resistor r=81.8016 c=0 +rg132 (\5\:I12\|net013 \6\:I12\|net013) resistor r=37.6755 c=0 +rg133 (\6\:I12\|net013 I12\|net013) resistor r=19.7812 c=0 +rg134 (\6\:I12\|net013 \7\:I12\|net013) resistor r=115.592 c=0 +rg135 (\16\:I4\|net3 \17\:I4\|net3) resistor r=158.125 c=0 +rg136 (\17\:I4\|net3 \18\:I4\|net3) resistor r=211.449 c=0 +rg137 (\18\:I4\|net3 \19\:I4\|net3) resistor r=168.536 c=0 +rg138 (\19\:I4\|net3 \15\:I4\|net3) resistor r=6.3083 c=0 +rg139 (\19\:I4\|net3 \20\:I4\|net3) resistor r=38.7601 c=0 +rg140 (\5\:I4\|I3\|Ai I4\|I3\|Ai) resistor r=317.339 c=0 +rg141 (I4\|I3\|Ai \6\:I4\|I3\|Ai) resistor r=91.8988 c=0 +rg142 (\16\:I9\|net3 \17\:I9\|net3) resistor r=158.125 c=0 +rg143 (\17\:I9\|net3 \18\:I9\|net3) resistor r=211.449 c=0 +rg144 (\18\:I9\|net3 \19\:I9\|net3) resistor r=168.536 c=0 +rg145 (\19\:I9\|net3 \15\:I9\|net3) resistor r=6.3083 c=0 +rg146 (\19\:I9\|net3 \20\:I9\|net3) resistor r=38.7601 c=0 +rg147 (\5\:I9\|I3\|Ai I9\|I3\|Ai) resistor r=317.339 c=0 +rg148 (I9\|I3\|Ai \6\:I9\|I3\|Ai) resistor r=91.8988 c=0 +rg149 (\4\:net21 \5\:net21) resistor r=181.923 c=0 +rg150 (\5\:net21 \6\:net21) resistor r=107.843 c=0 +rg151 (\6\:net21 \7\:net21) resistor r=48.8849 c=0 +rg152 (\7\:net21 \8\:net21) resistor r=189.671 c=0 +rg153 (\8\:net21 \9\:net21) resistor r=180.126 c=0 +rg154 (\4\:net21 \10\:net21) resistor r=158.125 c=0 +rg155 (\6\:net21 \3\:net21) resistor r=3.4479 c=0 +rg156 (\4\:net15 \5\:net15) resistor r=181.923 c=0 +rg157 (\5\:net15 \6\:net15) resistor r=107.843 c=0 +rg158 (\6\:net15 \7\:net15) resistor r=48.8849 c=0 +rg159 (\7\:net15 \8\:net15) resistor r=189.671 c=0 +rg160 (\8\:net15 \9\:net15) resistor r=180.126 c=0 +rg161 (\4\:net15 \10\:net15) resistor r=158.125 c=0 +rg162 (\6\:net15 \3\:net15) resistor r=3.4479 c=0 +rg163 (\9\:Y1 \10\:Y1) resistor r=62.0099 c=0 +rg165 (\10\:Y1 \11\:Y1) resistor r=91.5933 c=0 +rg166 (\11\:Y1 \12\:Y1) resistor r=135.03 c=0 +rg167 (I4\|I3\|Bi \2\:I4\|I3\|Bi) resistor r=271.714 c=0 +rg168 (\2\:I4\|I3\|Bi \3\:I4\|I3\|Bi) resistor r=140.208 c=0 +rg169 (I9\|I3\|Bi \2\:I9\|I3\|Bi) resistor r=271.714 c=0 +rg170 (\2\:I9\|I3\|Bi \3\:I9\|I3\|Bi) resistor r=140.208 c=0 +rg171 (\1\:X2 \2\:X2) resistor r=3.7604 c=0 +rg172 (\2\:X2 \3\:X2) resistor r=62.0099 c=0 +rg173 (\2\:X2 \4\:X2) resistor r=91.5933 c=0 +rg174 (\8\:Y3 \9\:Y3) resistor r=91.5933 c=0 +rg175 (\9\:Y3 \7\:Y3) resistor r=3.7604 c=0 +rg176 (\9\:Y3 \10\:Y3) resistor r=62.0099 c=0 +rg177 (\8\:Y2 \9\:Y2) resistor r=91.5933 c=0 +rg178 (\9\:Y2 \7\:Y2) resistor r=3.7604 c=0 +rg179 (\9\:Y2 \10\:Y2) resistor r=62.0099 c=0 +rg180 (\7\:X2 \8\:X2) resistor r=3.7604 c=0 +rg181 (\8\:X2 \9\:X2) resistor r=62.0099 c=0 +rg182 (\8\:X2 \10\:X2) resistor r=91.5933 c=0 +rg183 (\13\:X2 \16\:X2) resistor r=3.7604 c=0 +rg184 (\16\:X2 \17\:X2) resistor r=62.0099 c=0 +rg185 (\16\:X2 \18\:X2) resistor r=91.5933 c=0 +rg186 (\5\:I18\|net013 \6\:I18\|net013) resistor r=37.6755 c=0 +rg187 (\6\:I18\|net013 I18\|net013) resistor r=19.7812 c=0 +rg188 (\6\:I18\|net013 \7\:I18\|net013) resistor r=115.592 c=0 +rg189 (\6\:net38 \7\:net38) resistor r=132.954 c=0 +rg190 (\7\:net38 \8\:net38) resistor r=83.7878 c=0 +rg191 (\7\:net38 net38) resistor r=15.5249 c=0 +rg192 (\5\:I26\|net013 \6\:I26\|net013) resistor r=37.6755 c=0 +rg193 (\6\:I26\|net013 I26\|net013) resistor r=19.7812 c=0 +rg194 (\6\:I26\|net013 \7\:I26\|net013) resistor r=115.592 c=0 +rg195 (\5\:I21\|net013 \6\:I21\|net013) resistor r=37.6755 c=0 +rg196 (\6\:I21\|net013 I21\|net013) resistor r=19.7812 c=0 +rg197 (\6\:I21\|net013 \7\:I21\|net013) resistor r=115.592 c=0 +rg198 (I0\|I4\|Bi \2\:I0\|I4\|Bi) resistor r=3.4479 c=0 +rg199 (\2\:I0\|I4\|Bi \3\:I0\|I4\|Bi) resistor r=70.5516 c=0 +rg200 (\2\:I0\|I4\|Bi \4\:I0\|I4\|Bi) resistor r=68.2599 c=0 +rg201 (\4\:I0\|I4\|Ai \5\:I0\|I4\|Ai) resistor r=426.762 c=0 +rg202 (\5\:I0\|I4\|Ai \3\:I0\|I4\|Ai) resistor r=295.399 c=0 +rg203 (\6\:net8 \7\:net8) resistor r=132.954 c=0 +rg204 (\7\:net8 \8\:net8) resistor r=83.7878 c=0 +rg205 (\7\:net8 \4\:net8) resistor r=15.5249 c=0 +rg206 (\6\:net087 \7\:net087) resistor r=132.954 c=0 +rg207 (\7\:net087 \8\:net087) resistor r=83.7878 c=0 +rg208 (\7\:net087 \4\:net087) resistor r=15.5249 c=0 +rg209 (\13\:net38 \14\:net38) resistor r=68.6766 c=0 +rg210 (\14\:net38 \15\:net38) resistor r=39.0198 c=0 +rg211 (\15\:net38 \9\:net38) resistor r=3.7604 c=0 +rg212 (\9\:net38 \16\:net38) resistor r=42.4747 c=0 +rg213 (\16\:net38 \17\:net38) resistor r=51.4263 c=0 +rg214 (\14\:net38 \12\:net38) resistor r=3.6562 c=0 +rg215 (\15\:net38 \18\:net38) resistor r=47.6349 c=0 +rg216 (\16\:net38 \19\:net38) resistor r=106.01 c=0 +rg217 (I10\|I4\|Bi \2\:I10\|I4\|Bi) resistor r=3.4479 c=0 +rg218 (\2\:I10\|I4\|Bi \3\:I10\|I4\|Bi) resistor r=70.5516 c=0 +rg219 (\2\:I10\|I4\|Bi \4\:I10\|I4\|Bi) resistor r=68.2599 c=0 +rg220 (I10\|I4\|Ai \2\:I10\|I4\|Ai) resistor r=426.762 c=0 +rg221 (\2\:I10\|I4\|Ai \3\:I10\|I4\|Ai) resistor r=295.399 c=0 +rg222 (I3\|I4\|Bi \2\:I3\|I4\|Bi) resistor r=3.4479 c=0 +rg223 (\2\:I3\|I4\|Bi \3\:I3\|I4\|Bi) resistor r=70.5516 c=0 +rg224 (\2\:I3\|I4\|Bi \4\:I3\|I4\|Bi) resistor r=68.2599 c=0 +rg225 (\4\:I3\|I4\|Ai \5\:I3\|I4\|Ai) resistor r=426.762 c=0 +rg226 (\5\:I3\|I4\|Ai \3\:I3\|I4\|Ai) resistor r=295.399 c=0 +rg227 (\4\:net39 \5\:net39) resistor r=3.7604 c=0 +rg228 (\5\:net39 \6\:net39) resistor r=47.6349 c=0 +rg229 (\6\:net39 \7\:net39) resistor r=149.112 c=0 +rg230 (\7\:net39 \8\:net39) resistor r=237.862 c=0 +rg231 (\8\:net39 \9\:net39) resistor r=167.131 c=0 +rg232 (\5\:net39 \10\:net39) resistor r=109.093 c=0 +rg233 (\7\:net39 \11\:net39) resistor r=54.2235 c=0 +rg234 (\11\:net39 \12\:net39) resistor r=140.208 c=0 +rg235 (\13\:net8 \14\:net8) resistor r=68.6766 c=0 +rg236 (\14\:net8 \15\:net8) resistor r=39.0198 c=0 +rg237 (\15\:net8 \10\:net8) resistor r=3.7604 c=0 +rg238 (\10\:net8 \16\:net8) resistor r=42.4747 c=0 +rg239 (\16\:net8 \17\:net8) resistor r=51.4263 c=0 +rg240 (\14\:net8 \12\:net8) resistor r=3.6562 c=0 +rg241 (\15\:net8 \18\:net8) resistor r=47.6349 c=0 +rg242 (\16\:net8 \19\:net8) resistor r=106.01 c=0 +rg243 (\13\:net087 \14\:net087) resistor r=68.6766 c=0 +rg244 (\14\:net087 \15\:net087) resistor r=39.0198 c=0 +rg245 (\15\:net087 \9\:net087) resistor r=3.7604 c=0 +rg246 (\9\:net087 \16\:net087) resistor r=42.4747 c=0 +rg247 (\16\:net087 \17\:net087) resistor r=51.4263 c=0 +rg248 (\14\:net087 \12\:net087) resistor r=3.6562 c=0 +rg249 (\15\:net087 \18\:net087) resistor r=47.6349 c=0 +rg250 (\16\:net087 \19\:net087) resistor r=106.01 c=0 +rg251 (\10\:I0\|net3 \11\:I0\|net3) resistor r=97.8433 c=0 +rg252 (\11\:I0\|net3 \9\:I0\|net3) resistor r=3.7604 c=0 +rg253 (\11\:I0\|net3 \12\:I0\|net3) resistor r=40.9683 c=0 +rg254 (\5\:I0\|net1 \6\:I0\|net1) resistor r=80.5516 c=0 +rg255 (\6\:I0\|net1 \4\:I0\|net1) resistor r=3.5521 c=0 +rg256 (\6\:I0\|net1 \7\:I0\|net1) resistor r=76.1766 c=0 +rg257 (\10\:net17 \11\:net17) resistor r=3.7604 c=0 +rg258 (\11\:net17 \12\:net17) resistor r=47.6349 c=0 +rg259 (\12\:net17 \13\:net17) resistor r=149.112 c=0 +rg260 (\13\:net17 \14\:net17) resistor r=237.862 c=0 +rg261 (\14\:net17 \15\:net17) resistor r=167.131 c=0 +rg262 (\11\:net17 \16\:net17) resistor r=109.093 c=0 +rg263 (\13\:net17 \17\:net17) resistor r=54.2235 c=0 +rg264 (\17\:net17 \18\:net17) resistor r=140.208 c=0 +rg265 (\10\:net54 \11\:net54) resistor r=3.7604 c=0 +rg266 (\11\:net54 \12\:net54) resistor r=47.6349 c=0 +rg267 (\12\:net54 \13\:net54) resistor r=149.112 c=0 +rg268 (\13\:net54 \14\:net54) resistor r=237.862 c=0 +rg269 (\14\:net54 \15\:net54) resistor r=167.131 c=0 +rg270 (\11\:net54 \16\:net54) resistor r=109.093 c=0 +rg271 (\13\:net54 \17\:net54) resistor r=54.2235 c=0 +rg272 (\17\:net54 \18\:net54) resistor r=140.208 c=0 +rg273 (\10\:I10\|net3 \11\:I10\|net3) resistor r=97.8433 c=0 +rg274 (\11\:I10\|net3 \9\:I10\|net3) resistor r=3.7604 c=0 +rg275 (\11\:I10\|net3 \12\:I10\|net3) resistor r=40.9683 c=0 +rg276 (I0\|net6 \2\:I0\|net6) resistor r=3.5521 c=0 +rg277 (\2\:I0\|net6 \3\:I0\|net6) resistor r=77.0099 c=0 +rg278 (\2\:I0\|net6 \4\:I0\|net6) resistor r=79.7183 c=0 +rg279 (\10\:I3\|net3 \11\:I3\|net3) resistor r=97.8433 c=0 +rg280 (\11\:I3\|net3 \9\:I3\|net3) resistor r=3.7604 c=0 +rg281 (\11\:I3\|net3 \12\:I3\|net3) resistor r=40.9683 c=0 +rg282 (\5\:I10\|net1 \6\:I10\|net1) resistor r=80.5516 c=0 +rg283 (\6\:I10\|net1 \4\:I10\|net1) resistor r=3.5521 c=0 +rg284 (\6\:I10\|net1 \7\:I10\|net1) resistor r=76.1766 c=0 +rg285 (\5\:I3\|net1 \6\:I3\|net1) resistor r=80.5516 c=0 +rg286 (\6\:I3\|net1 \4\:I3\|net1) resistor r=3.5521 c=0 +rg287 (\6\:I3\|net1 \7\:I3\|net1) resistor r=76.1766 c=0 +rg288 (I10\|net6 \2\:I10\|net6) resistor r=3.5521 c=0 +rg289 (\2\:I10\|net6 \3\:I10\|net6) resistor r=77.0099 c=0 +rg290 (\2\:I10\|net6 \4\:I10\|net6) resistor r=79.7183 c=0 +rg291 (I3\|net6 \2\:I3\|net6) resistor r=3.5521 c=0 +rg292 (\2\:I3\|net6 \3\:I3\|net6) resistor r=77.0099 c=0 +rg293 (\2\:I3\|net6 \4\:I3\|net6) resistor r=79.7183 c=0 +rg294 (\16\:I0\|net3 \17\:I0\|net3) resistor r=158.125 c=0 +rg295 (\17\:I0\|net3 \18\:I0\|net3) resistor r=211.449 c=0 +rg296 (\18\:I0\|net3 \19\:I0\|net3) resistor r=168.536 c=0 +rg297 (\19\:I0\|net3 \13\:I0\|net3) resistor r=6.3083 c=0 +rg298 (\19\:I0\|net3 \20\:I0\|net3) resistor r=38.7601 c=0 +rg299 (\5\:I0\|I3\|Ai I0\|I3\|Ai) resistor r=317.339 c=0 +rg300 (I0\|I3\|Ai \6\:I0\|I3\|Ai) resistor r=91.8988 c=0 +rg301 (\3\:net31 \4\:net31) resistor r=181.923 c=0 +rg302 (\4\:net31 \5\:net31) resistor r=107.843 c=0 +rg303 (\5\:net31 \6\:net31) resistor r=48.8849 c=0 +rg304 (\6\:net31 \7\:net31) resistor r=189.671 c=0 +rg305 (\7\:net31 \8\:net31) resistor r=180.126 c=0 +rg306 (\3\:net31 \9\:net31) resistor r=158.125 c=0 +rg307 (\5\:net31 net31) resistor r=3.4479 c=0 +rg308 (\16\:I10\|net3 \17\:I10\|net3) resistor r=158.125 c=0 +rg309 (\17\:I10\|net3 \18\:I10\|net3) resistor r=211.449 c=0 +rg310 (\18\:I10\|net3 \19\:I10\|net3) resistor r=168.536 c=0 +rg311 (\19\:I10\|net3 \15\:I10\|net3) resistor r=6.3083 c=0 +rg312 (\19\:I10\|net3 \20\:I10\|net3) resistor r=38.7601 c=0 +rg313 (\5\:I10\|I3\|Ai I10\|I3\|Ai) resistor r=317.339 c=0 +rg314 (I10\|I3\|Ai \6\:I10\|I3\|Ai) resistor r=91.8988 c=0 +rg315 (I0\|I3\|Bi \5\:I0\|I3\|Bi) resistor r=271.714 c=0 +rg316 (\5\:I0\|I3\|Bi \6\:I0\|I3\|Bi) resistor r=140.208 c=0 +rg317 (\16\:I3\|net3 \17\:I3\|net3) resistor r=158.125 c=0 +rg318 (\17\:I3\|net3 \18\:I3\|net3) resistor r=211.449 c=0 +rg319 (\18\:I3\|net3 \19\:I3\|net3) resistor r=168.536 c=0 +rg320 (\19\:I3\|net3 \13\:I3\|net3) resistor r=6.3083 c=0 +rg321 (\19\:I3\|net3 \20\:I3\|net3) resistor r=38.7601 c=0 +rg322 (\5\:I3\|I3\|Ai I3\|I3\|Ai) resistor r=317.339 c=0 +rg323 (I3\|I3\|Ai \6\:I3\|I3\|Ai) resistor r=91.8988 c=0 +rg324 (\3\:net1 \4\:net1) resistor r=181.923 c=0 +rg325 (\4\:net1 \5\:net1) resistor r=107.843 c=0 +rg326 (\5\:net1 \6\:net1) resistor r=48.8849 c=0 +rg327 (\6\:net1 \7\:net1) resistor r=189.671 c=0 +rg328 (\7\:net1 \8\:net1) resistor r=180.126 c=0 +rg329 (\3\:net1 \9\:net1) resistor r=158.125 c=0 +rg330 (\5\:net1 net1) resistor r=3.4479 c=0 +rg331 (\3\:net26 \4\:net26) resistor r=181.923 c=0 +rg332 (\4\:net26 \5\:net26) resistor r=107.843 c=0 +rg333 (\5\:net26 \6\:net26) resistor r=48.8849 c=0 +rg334 (\6\:net26 \7\:net26) resistor r=189.671 c=0 +rg335 (\7\:net26 \8\:net26) resistor r=180.126 c=0 +rg336 (\3\:net26 \9\:net26) resistor r=158.125 c=0 +rg337 (\5\:net26 net26) resistor r=3.4479 c=0 +rg338 (I10\|I3\|Bi \2\:I10\|I3\|Bi) resistor r=271.714 c=0 +rg339 (\2\:I10\|I3\|Bi \3\:I10\|I3\|Bi) resistor r=140.208 c=0 +rg340 (\5\:I1\|I3\|Bi \3\:I1\|I3\|Bi) resistor r=271.714 c=0 +rg341 (\5\:I1\|I3\|Bi \6\:I1\|I3\|Bi) resistor r=140.208 c=0 +rg342 (I3\|I3\|Bi \2\:I3\|I3\|Bi) resistor r=271.714 c=0 +rg343 (\2\:I3\|I3\|Bi \3\:I3\|I3\|Bi) resistor r=140.208 c=0 +rg344 (\5\:I11\|I3\|Bi \3\:I11\|I3\|Bi) resistor r=271.714 c=0 +rg345 (\5\:I11\|I3\|Bi \6\:I11\|I3\|Bi) resistor r=140.208 c=0 +rg346 (I1\|net3 \2\:I1\|net3) resistor r=38.7601 c=0 +rg347 (\2\:I1\|net3 \3\:I1\|net3) resistor r=168.536 c=0 +rg348 (\2\:I1\|net3 \4\:I1\|net3) resistor r=6.3083 c=0 +rg349 (\3\:I1\|net3 \5\:I1\|net3) resistor r=211.449 c=0 +rg350 (\5\:I1\|net3 \6\:I1\|net3) resistor r=158.125 c=0 +rg351 (\5\:I2\|I3\|Bi \3\:I2\|I3\|Bi) resistor r=271.714 c=0 +rg352 (\5\:I2\|I3\|Bi \6\:I2\|I3\|Bi) resistor r=140.208 c=0 +rg353 (\3\:net35 \4\:net35) resistor r=180.126 c=0 +rg354 (\4\:net35 \5\:net35) resistor r=193.622 c=0 +rg355 (\5\:net35 \6\:net35) resistor r=48.8849 c=0 +rg356 (\6\:net35 \7\:net35) resistor r=107.843 c=0 +rg357 (\7\:net35 \8\:net35) resistor r=181.923 c=0 +rg358 (\8\:net35 \9\:net35) resistor r=158.125 c=0 +rg359 (\6\:net35 net35) resistor r=3.4479 c=0 +rg360 (\5\:I1\|net6 \6\:I1\|net6) resistor r=79.7183 c=0 +rg361 (\6\:I1\|net6 \4\:I1\|net6) resistor r=3.5521 c=0 +rg362 (\6\:I1\|net6 \7\:I1\|net6) resistor r=77.0099 c=0 +rg363 (I1\|I3\|Ai \2\:I1\|I3\|Ai) resistor r=91.8988 c=0 +rg364 (\2\:I1\|I3\|Ai \3\:I1\|I3\|Ai) resistor r=317.339 c=0 +rg365 (I1\|net1 \2\:I1\|net1) resistor r=3.5521 c=0 +rg366 (\2\:I1\|net1 \3\:I1\|net1) resistor r=76.1766 c=0 +rg367 (\2\:I1\|net1 \4\:I1\|net1) resistor r=80.5516 c=0 +rg368 (I11\|net3 \2\:I11\|net3) resistor r=38.7601 c=0 +rg369 (\2\:I11\|net3 \3\:I11\|net3) resistor r=168.536 c=0 +rg370 (\2\:I11\|net3 \4\:I11\|net3) resistor r=6.3083 c=0 +rg371 (\3\:I11\|net3 \5\:I11\|net3) resistor r=211.449 c=0 +rg372 (\5\:I11\|net3 \6\:I11\|net3) resistor r=158.125 c=0 +rg373 (\8\:I1\|net3 \9\:I1\|net3) resistor r=3.7604 c=0 +rg374 (\9\:I1\|net3 \10\:I1\|net3) resistor r=40.9683 c=0 +rg375 (\9\:I1\|net3 \11\:I1\|net3) resistor r=97.8433 c=0 +rg376 (\4\:net5 \5\:net5) resistor r=180.126 c=0 +rg377 (\5\:net5 \6\:net5) resistor r=193.622 c=0 +rg378 (\6\:net5 \7\:net5) resistor r=48.8849 c=0 +rg379 (\7\:net5 \8\:net5) resistor r=107.843 c=0 +rg380 (\8\:net5 \9\:net5) resistor r=181.923 c=0 +rg381 (\9\:net5 \10\:net5) resistor r=158.125 c=0 +rg382 (\7\:net5 net5) resistor r=3.4479 c=0 +rg383 (I2\|net3 \2\:I2\|net3) resistor r=38.7601 c=0 +rg384 (\2\:I2\|net3 \3\:I2\|net3) resistor r=168.536 c=0 +rg385 (\2\:I2\|net3 \4\:I2\|net3) resistor r=6.3083 c=0 +rg386 (\3\:I2\|net3 \5\:I2\|net3) resistor r=211.449 c=0 +rg387 (\5\:I2\|net3 \6\:I2\|net3) resistor r=158.125 c=0 +rg388 (\5\:I11\|net6 \6\:I11\|net6) resistor r=79.7183 c=0 +rg389 (\6\:I11\|net6 \4\:I11\|net6) resistor r=3.5521 c=0 +rg390 (\6\:I11\|net6 \7\:I11\|net6) resistor r=77.0099 c=0 +rg391 (\3\:net45 \4\:net45) resistor r=180.126 c=0 +rg392 (\4\:net45 \5\:net45) resistor r=193.622 c=0 +rg393 (\5\:net45 \6\:net45) resistor r=48.8849 c=0 +rg394 (\6\:net45 \7\:net45) resistor r=107.843 c=0 +rg395 (\7\:net45 \8\:net45) resistor r=181.923 c=0 +rg396 (\8\:net45 \9\:net45) resistor r=158.125 c=0 +rg397 (\6\:net45 net45) resistor r=3.4479 c=0 +rg398 (I11\|I3\|Ai \2\:I11\|I3\|Ai) resistor r=91.8988 c=0 +rg399 (\2\:I11\|I3\|Ai \3\:I11\|I3\|Ai) resistor r=317.339 c=0 +rg400 (\5\:I2\|net6 \6\:I2\|net6) resistor r=79.7183 c=0 +rg401 (\6\:I2\|net6 \4\:I2\|net6) resistor r=3.5521 c=0 +rg402 (\6\:I2\|net6 \7\:I2\|net6) resistor r=77.0099 c=0 +rg403 (I11\|net1 \2\:I11\|net1) resistor r=3.5521 c=0 +rg404 (\2\:I11\|net1 \3\:I11\|net1) resistor r=76.1766 c=0 +rg405 (\2\:I11\|net1 \4\:I11\|net1) resistor r=80.5516 c=0 +rg406 (I2\|I3\|Ai \2\:I2\|I3\|Ai) resistor r=91.8988 c=0 +rg407 (\2\:I2\|I3\|Ai \3\:I2\|I3\|Ai) resistor r=317.339 c=0 +rg408 (\8\:I11\|net3 \9\:I11\|net3) resistor r=3.7604 c=0 +rg409 (\9\:I11\|net3 \10\:I11\|net3) resistor r=40.9683 c=0 +rg410 (\9\:I11\|net3 \11\:I11\|net3) resistor r=97.8433 c=0 +rg411 (I2\|net1 \2\:I2\|net1) resistor r=3.5521 c=0 +rg412 (\2\:I2\|net1 \3\:I2\|net1) resistor r=76.1766 c=0 +rg413 (\2\:I2\|net1 \4\:I2\|net1) resistor r=80.5516 c=0 +rg414 (\5\:I1\|I4\|Ai \6\:I1\|I4\|Ai) resistor r=68.2599 c=0 +rg415 (\6\:I1\|I4\|Ai \4\:I1\|I4\|Ai) resistor r=3.4479 c=0 +rg416 (\6\:I1\|I4\|Ai \7\:I1\|I4\|Ai) resistor r=70.5516 c=0 +rg417 (\8\:I2\|net3 \10\:I2\|net3) resistor r=3.7604 c=0 +rg418 (\10\:I2\|net3 \11\:I2\|net3) resistor r=40.9683 c=0 +rg419 (\10\:I2\|net3 \12\:I2\|net3) resistor r=97.8433 c=0 +rg420 (\5\:net34 \6\:net34) resistor r=106.125 c=0 +rg421 (\6\:net34 \4\:net34) resistor r=42.5281 c=0 +rg422 (\4\:net34 \7\:net34) resistor r=3.7604 c=0 +rg423 (\7\:net34 \8\:net34) resistor r=47.6349 c=0 +rg424 (\6\:net34 \9\:net34) resistor r=51.3337 c=0 +rg425 (\7\:net34 \10\:net34) resistor r=39.0198 c=0 +rg426 (\10\:net34 \11\:net34) resistor r=68.6766 c=0 +rg427 (\10\:net34 net34) resistor r=3.6562 c=0 +rg428 (\22\:X2 \23\:X2) resistor r=91.5933 c=0 +rg429 (\23\:X2 \20\:X2) resistor r=3.7604 c=0 +rg430 (\23\:X2 \24\:X2) resistor r=62.0099 c=0 +rg431 (\5\:I11\|I4\|Bi \6\:I11\|I4\|Bi) resistor r=68.2599 c=0 +rg432 (\6\:I11\|I4\|Bi \4\:I11\|I4\|Bi) resistor r=3.4479 c=0 +rg433 (\6\:I11\|I4\|Bi \7\:I11\|I4\|Bi) resistor r=70.5516 c=0 +rg434 (\5\:net078 \6\:net078) resistor r=106.125 c=0 +rg435 (\6\:net078 \4\:net078) resistor r=42.5281 c=0 +rg436 (\4\:net078 \7\:net078) resistor r=3.7604 c=0 +rg437 (\7\:net078 \8\:net078) resistor r=47.6349 c=0 +rg438 (\6\:net078 \9\:net078) resistor r=51.3337 c=0 +rg439 (\7\:net078 \10\:net078) resistor r=39.0198 c=0 +rg440 (\10\:net078 \11\:net078) resistor r=68.6766 c=0 +rg441 (\10\:net078 net078) resistor r=3.6562 c=0 +rg442 (\14\:net34 \15\:net34) resistor r=83.7878 c=0 +rg443 (\15\:net34 \16\:net34) resistor r=132.954 c=0 +rg444 (\15\:net34 \12\:net34) resistor r=15.5249 c=0 +rg445 (\5\:I2\|I4\|Bi \6\:I2\|I4\|Bi) resistor r=68.2599 c=0 +rg446 (\6\:I2\|I4\|Bi \4\:I2\|I4\|Bi) resistor r=3.4479 c=0 +rg447 (\6\:I2\|I4\|Bi \7\:I2\|I4\|Bi) resistor r=70.5516 c=0 +rg448 (\5\:net28 \6\:net28) resistor r=106.125 c=0 +rg449 (\6\:net28 \4\:net28) resistor r=42.5281 c=0 +rg450 (\4\:net28 \7\:net28) resistor r=3.7604 c=0 +rg451 (\7\:net28 \8\:net28) resistor r=47.6349 c=0 +rg452 (\6\:net28 \9\:net28) resistor r=51.3337 c=0 +rg453 (\7\:net28 \10\:net28) resistor r=39.0198 c=0 +rg454 (\10\:net28 \11\:net28) resistor r=68.6766 c=0 +rg455 (\10\:net28 net28) resistor r=3.6562 c=0 +rg456 (\3\:net095 \4\:net095) resistor r=167.131 c=0 +rg457 (\4\:net095 \5\:net095) resistor r=237.862 c=0 +rg458 (\5\:net095 \6\:net095) resistor r=149.112 c=0 +rg459 (\6\:net095 \7\:net095) resistor r=47.6349 c=0 +rg460 (\7\:net095 net095) resistor r=3.7604 c=0 +rg461 (\5\:net095 \8\:net095) resistor r=54.2235 c=0 +rg462 (\8\:net095 \9\:net095) resistor r=140.208 c=0 +rg463 (\7\:net095 \10\:net095) resistor r=109.093 c=0 +rg464 (\4\:I1\|I4\|Bi \5\:I1\|I4\|Bi) resistor r=426.762 c=0 +rg465 (\5\:I1\|I4\|Bi \3\:I1\|I4\|Bi) resistor r=295.399 c=0 +rg466 (\5\:I13\|net013 \6\:I13\|net013) resistor r=37.6755 c=0 +rg467 (\6\:I13\|net013 I13\|net013) resistor r=19.7812 c=0 +rg468 (\6\:I13\|net013 \7\:I13\|net013) resistor r=115.592 c=0 +rg469 (\17\:net078 \18\:net078) resistor r=83.7878 c=0 +rg470 (\18\:net078 \19\:net078) resistor r=132.954 c=0 +rg471 (\18\:net078 \12\:net078) resistor r=15.5249 c=0 +rg472 (\17\:net28 \18\:net28) resistor r=83.7878 c=0 +rg473 (\18\:net28 \19\:net28) resistor r=132.954 c=0 +rg474 (\18\:net28 \12\:net28) resistor r=15.5249 c=0 +rg475 (\12\:net0100 \13\:net0100) resistor r=167.131 c=0 +rg476 (\13\:net0100 \14\:net0100) resistor r=237.862 c=0 +rg477 (\14\:net0100 \15\:net0100) resistor r=149.112 c=0 +rg478 (\15\:net0100 \16\:net0100) resistor r=47.6349 c=0 +rg479 (\16\:net0100 \9\:net0100) resistor r=3.7604 c=0 +rg480 (\14\:net0100 \17\:net0100) resistor r=54.2235 c=0 +rg481 (\17\:net0100 \18\:net0100) resistor r=140.208 c=0 +rg482 (\16\:net0100 \19\:net0100) resistor r=109.093 c=0 +rg483 (net0115 \2\:net0115) resistor r=81.8016 c=0 +rg484 (\2\:net0115 \3\:net0115) resistor r=3.7604 c=0 +rg485 (\2\:net0115 \4\:net0115) resistor r=55.3433 c=0 +rg486 (\4\:X1 \5\:X1) resistor r=91.5933 c=0 +rg487 (\5\:X1 \2\:X1) resistor r=3.7604 c=0 +rg488 (\5\:X1 \6\:X1) resistor r=62.0099 c=0 +rg489 (\12\:net29 \13\:net29) resistor r=167.131 c=0 +rg490 (\13\:net29 \14\:net29) resistor r=237.862 c=0 +rg491 (\14\:net29 \15\:net29) resistor r=149.112 c=0 +rg492 (\15\:net29 \16\:net29) resistor r=47.6349 c=0 +rg493 (\16\:net29 \9\:net29) resistor r=3.7604 c=0 +rg494 (\14\:net29 \17\:net29) resistor r=54.2235 c=0 +rg495 (\17\:net29 \18\:net29) resistor r=140.208 c=0 +rg496 (\16\:net29 \19\:net29) resistor r=109.093 c=0 +rg497 (\4\:I11\|I4\|Ai \5\:I11\|I4\|Ai) resistor r=426.762 c=0 +rg498 (\5\:I11\|I4\|Ai \3\:I11\|I4\|Ai) resistor r=295.399 c=0 +rg499 (I24\|net013 \2\:I24\|net013) resistor r=19.7812 c=0 +rg500 (\2\:I24\|net013 \3\:I24\|net013) resistor r=115.592 c=0 +rg501 (\2\:I24\|net013 \4\:I24\|net013) resistor r=37.6755 c=0 +rg502 (I23\|net013 \2\:I23\|net013) resistor r=19.7812 c=0 +rg503 (\2\:I23\|net013 \3\:I23\|net013) resistor r=115.592 c=0 +rg504 (\2\:I23\|net013 \4\:I23\|net013) resistor r=37.6755 c=0 +rg505 (\10\:X1 \11\:X1) resistor r=91.5933 c=0 +rg506 (\11\:X1 \7\:X1) resistor r=3.7604 c=0 +rg507 (\11\:X1 \12\:X1) resistor r=62.0099 c=0 +rg508 (\4\:I2\|I4\|Ai \5\:I2\|I4\|Ai) resistor r=426.762 c=0 +rg509 (\5\:I2\|I4\|Ai \3\:I2\|I4\|Ai) resistor r=295.399 c=0 +rg510 (\15\:X1 \16\:X1) resistor r=91.5933 c=0 +rg511 (\16\:X1 \13\:X1) resistor r=3.7604 c=0 +rg512 (\16\:X1 \17\:X1) resistor r=62.0099 c=0 +rg514 (\15\:Y1 \16\:Y1) resistor r=62.0099 c=0 +rg515 (\15\:Y1 \17\:Y1) resistor r=91.5933 c=0 +rg516 (\17\:Y1 \18\:Y1) resistor r=135.482 c=0 +rg517 (\11\:Y3 \12\:Y3) resistor r=3.7604 c=0 +rg518 (\12\:Y3 \13\:Y3) resistor r=62.0099 c=0 +rg519 (\12\:Y3 \14\:Y3) resistor r=91.5933 c=0 +rg520 (\11\:Y2 \12\:Y2) resistor r=3.7604 c=0 +rg521 (\12\:Y2 \13\:Y2) resistor r=62.0099 c=0 +rg522 (\12\:Y2 \14\:Y2) resistor r=91.5933 c=0 +rg523 (\5\:I16\|net013 \6\:I16\|net013) resistor r=37.6755 c=0 +rg524 (\6\:I16\|net013 I16\|net013) resistor r=19.7812 c=0 +rg525 (\6\:I16\|net013 \7\:I16\|net013) resistor r=115.592 c=0 +rg526 (\12\:net0115 \13\:net0115) resistor r=79.5099 c=0 +rg527 (\13\:net0115 \14\:net0115) resistor r=73.0516 c=0 +rg528 (\14\:net0115 \8\:net0115) resistor r=77.3221 c=0 +rg529 (\13\:net0115 \15\:net0115) resistor r=3.7604 c=0 +rg530 (\16\:net0115 \17\:net0115) resistor r=41.6577 c=0 +rg531 (\17\:net0115 \18\:net0115) resistor r=120.434 c=0 +rg532 (\18\:net0115 \7\:net0115) resistor r=7.4762 c=0 +rg533 (\17\:net0115 \11\:net0115) resistor r=32.1097 c=0 +rg534 (\18\:net0115 \19\:net0115) resistor r=47.3355 c=0 +rg535 (\5\:I6\|I1\|Ai I6\|I1\|Ai) resistor r=333.423 c=0 +rg536 (I6\|I1\|Ai \6\:I6\|I1\|Ai) resistor r=76.0655 c=0 +rg537 (I8\|I3\|net013 \2\:I8\|I3\|net013) resistor r=3.7604 c=0 +rg538 (\2\:I8\|I3\|net013 \3\:I8\|I3\|net013) resistor r=109.302 c=0 +rg539 (\2\:I8\|I3\|net013 \4\:I8\|I3\|net013) resistor r=43.2599 c=0 +rg540 (I7\|I3\|net013 \2\:I7\|I3\|net013) resistor r=3.7604 c=0 +rg541 (\2\:I7\|I3\|net013 \3\:I7\|I3\|net013) resistor r=109.302 c=0 +rg542 (\2\:I7\|I3\|net013 \4\:I7\|I3\|net013) resistor r=43.2599 c=0 +rg543 (I6\|I1\|Bi \2\:I6\|I1\|Bi) resistor r=3.6562 c=0 +rg544 (\2\:I6\|I1\|Bi \3\:I6\|I1\|Bi) resistor r=84.0933 c=0 +rg545 (\2\:I6\|I1\|Bi \4\:I6\|I1\|Bi) resistor r=53.0516 c=0 +rg546 (\5\:I8\|I1\|Bi \6\:I8\|I1\|Bi) resistor r=53.0516 c=0 +rg547 (\6\:I8\|I1\|Bi \4\:I8\|I1\|Bi) resistor r=3.6562 c=0 +rg548 (\6\:I8\|I1\|Bi \7\:I8\|I1\|Bi) resistor r=84.0933 c=0 +rg549 (\5\:I7\|I1\|Bi \6\:I7\|I1\|Bi) resistor r=53.0516 c=0 +rg550 (\6\:I7\|I1\|Bi \4\:I7\|I1\|Bi) resistor r=3.6562 c=0 +rg551 (\6\:I7\|I1\|Bi \7\:I7\|I1\|Bi) resistor r=84.0933 c=0 +rg552 (I6\|I3\|net013 \2\:I6\|I3\|net013) resistor r=43.2599 c=0 +rg553 (\2\:I6\|I3\|net013 \3\:I6\|I3\|net013) resistor r=3.7604 c=0 +rg554 (\2\:I6\|I3\|net013 \4\:I6\|I3\|net013) resistor r=109.302 c=0 +rg555 (\3\:net0127 \4\:net0127) resistor r=116.403 c=0 +rg556 (\4\:net0127 \5\:net0127) resistor r=165.153 c=0 +rg557 (\5\:net0127 \6\:net0127) resistor r=174.262 c=0 +rg558 (\3\:net0127 \7\:net0127) resistor r=138.542 c=0 +rg559 (\4\:net0127 \8\:net0127) resistor r=135.474 c=0 +rg560 (\8\:net0127 \9\:net0127) resistor r=72.4266 c=0 +rg561 (\9\:net0127 \10\:net0127) resistor r=80.1349 c=0 +rg562 (\9\:net0127 \2\:net0127) resistor r=3.7604 c=0 +rg563 (\2\:net075 \7\:net075) resistor r=3.7604 c=0 +rg564 (\7\:net075 \8\:net075) resistor r=73.0516 c=0 +rg565 (\7\:net075 \9\:net075) resistor r=79.5099 c=0 +rg566 (\8\:net075 \5\:net075) resistor r=77.3221 c=0 +rg567 (\2\:net47 \7\:net47) resistor r=3.7604 c=0 +rg568 (\7\:net47 \8\:net47) resistor r=73.0516 c=0 +rg569 (\7\:net47 \9\:net47) resistor r=79.5099 c=0 +rg570 (\8\:net47 \5\:net47) resistor r=77.3221 c=0 +rg571 (\19\:X1 \20\:X1) resistor r=91.5933 c=0 +rg572 (\20\:X1 \21\:X1) resistor r=3.7604 c=0 +rg573 (\20\:X1 \22\:X1) resistor r=62.0099 c=0 +rg574 (\13\:net075 \14\:net075) resistor r=47.3355 c=0 +rg575 (\14\:net075 \15\:net075) resistor r=120.434 c=0 +rg576 (\15\:net075 \16\:net075) resistor r=41.6577 c=0 +rg577 (\14\:net075 \17\:net075) resistor r=7.4762 c=0 +rg578 (\15\:net075 \3\:net075) resistor r=32.1097 c=0 +rg579 (\13\:net47 \14\:net47) resistor r=47.3355 c=0 +rg580 (\14\:net47 \15\:net47) resistor r=120.434 c=0 +rg581 (\15\:net47 \16\:net47) resistor r=41.6577 c=0 +rg582 (\14\:net47 \17\:net47) resistor r=7.4762 c=0 +rg583 (\15\:net47 \3\:net47) resistor r=32.1097 c=0 +rg584 (\7\:X0 \8\:X0) resistor r=3.7604 c=0 +rg585 (\8\:X0 \9\:X0) resistor r=91.5933 c=0 +rg586 (\8\:X0 \10\:X0) resistor r=62.0099 c=0 +rg587 (\12\:net44 \13\:net44) resistor r=174.262 c=0 +rg588 (\13\:net44 \14\:net44) resistor r=165.153 c=0 +rg589 (\14\:net44 \15\:net44) resistor r=116.403 c=0 +rg590 (\15\:net44 \16\:net44) resistor r=138.542 c=0 +rg591 (\14\:net44 \17\:net44) resistor r=135.474 c=0 +rg592 (\17\:net44 \18\:net44) resistor r=72.4266 c=0 +rg593 (\18\:net44 \9\:net44) resistor r=3.7604 c=0 +rg594 (\18\:net44 \19\:net44) resistor r=80.1349 c=0 +rg595 (\12\:net32 \13\:net32) resistor r=174.262 c=0 +rg596 (\13\:net32 \14\:net32) resistor r=165.153 c=0 +rg597 (\14\:net32 \15\:net32) resistor r=116.403 c=0 +rg598 (\15\:net32 \16\:net32) resistor r=138.542 c=0 +rg599 (\14\:net32 \17\:net32) resistor r=135.474 c=0 +rg600 (\17\:net32 \18\:net32) resistor r=72.4266 c=0 +rg601 (\18\:net32 \9\:net32) resistor r=3.7604 c=0 +rg602 (\18\:net32 \19\:net32) resistor r=80.1349 c=0 +rg603 (I25\|net013 \2\:I25\|net013) resistor r=19.7812 c=0 +rg604 (\2\:I25\|net013 \3\:I25\|net013) resistor r=115.592 c=0 +rg605 (\2\:I25\|net013 \4\:I25\|net013) resistor r=37.6755 c=0 +rg606 (I22\|net013 \2\:I22\|net013) resistor r=19.7812 c=0 +rg607 (\2\:I22\|net013 \3\:I22\|net013) resistor r=115.592 c=0 +rg608 (\2\:I22\|net013 \4\:I22\|net013) resistor r=37.6755 c=0 +rg609 (\18\:Y3 \19\:Y3) resistor r=91.5933 c=0 +rg610 (\19\:Y3 \16\:Y3) resistor r=3.7604 c=0 +rg611 (\19\:Y3 \20\:Y3) resistor r=62.0099 c=0 +rg612 (\18\:Y2 \19\:Y2) resistor r=91.5933 c=0 +rg613 (\19\:Y2 \16\:Y2) resistor r=3.7604 c=0 +rg614 (\19\:Y2 \20\:Y2) resistor r=62.0099 c=0 +rg615 (I8\|I1\|Ai \2\:I8\|I1\|Ai) resistor r=77.852 c=0 +rg616 (\2\:I8\|I1\|Ai \3\:I8\|I1\|Ai) resistor r=333.882 c=0 +rg617 (I7\|I1\|Ai \2\:I7\|I1\|Ai) resistor r=77.852 c=0 +rg618 (\2\:I7\|I1\|Ai \3\:I7\|I1\|Ai) resistor r=333.882 c=0 +rg619 (\5\:I14\|net013 \6\:I14\|net013) resistor r=37.6755 c=0 +rg620 (\6\:I14\|net013 I14\|net013) resistor r=19.7812 c=0 +rg621 (\6\:I14\|net013 \7\:I14\|net013) resistor r=115.592 c=0 +rg622 (\5\:I17\|net013 \6\:I17\|net013) resistor r=115.592 c=0 +rg623 (\6\:I17\|net013 I17\|net013) resistor r=19.7812 c=0 +rg624 (\6\:I17\|net013 \7\:I17\|net013) resistor r=37.6755 c=0 +rg625 (\12\:X0 \13\:X0) resistor r=3.7604 c=0 +rg626 (\13\:X0 \14\:X0) resistor r=62.0099 c=0 +rg627 (\13\:X0 \15\:X0) resistor r=91.5933 c=0 +rg628 (\16\:X0 \17\:X0) resistor r=3.7604 c=0 +rg629 (\17\:X0 \18\:X0) resistor r=62.0099 c=0 +rg630 (\17\:X0 \19\:X0) resistor r=91.5933 c=0 +rg631 (\19\:net075 \20\:net075) resistor r=3.7604 c=0 +rg632 (\20\:net075 \21\:net075) resistor r=55.3433 c=0 +rg633 (\20\:net075 \22\:net075) resistor r=81.8016 c=0 +rg634 (\19\:net47 \20\:net47) resistor r=3.7604 c=0 +rg635 (\20\:net47 \21\:net47) resistor r=55.3433 c=0 +rg636 (\20\:net47 \22\:net47) resistor r=81.8016 c=0 +rg637 (\21\:Y1 \22\:Y1) resistor r=627.236 c=0 +rg638 (\22\:Y1 \23\:Y1) resistor r=62.0099 c=0 +rg640 (\23\:Y1 \24\:Y1) resistor r=91.5933 c=0 +rg641 (Y0 \9\:Y0) resistor r=129.31 c=0 +rg642 (\9\:Y0 \10\:Y0) resistor r=455.086 c=0 +rg643 (\10\:Y0 \11\:Y0) resistor r=1019.75 c=0 +rg644 (\11\:Y0 \12\:Y0) resistor r=948.15 c=0 +rg645 (\12\:Y0 \13\:Y0) resistor r=62.0099 c=0 +rg647 (\9\:Y0 \14\:Y0) resistor r=165.202 c=0 +rg648 (\14\:Y0 \15\:Y0) resistor r=91.5933 c=0 +rg649 (\15\:Y0 \16\:Y0) resistor r=62.0099 c=0 +rg650 (\10\:Y0 \17\:Y0) resistor r=165.41 c=0 +rg651 (\17\:Y0 \18\:Y0) resistor r=91.5933 c=0 +rg652 (\18\:Y0 \19\:Y0) resistor r=62.0099 c=0 +rg653 (\11\:Y0 \20\:Y0) resistor r=165.618 c=0 +rg654 (\20\:Y0 \21\:Y0) resistor r=91.5933 c=0 +rg655 (\21\:Y0 \22\:Y0) resistor r=62.0099 c=0 +rg656 (\13\:Y0 \23\:Y0) resistor r=91.5933 c=0 +I25\|MP0 (\7\:I25\|net013 \20\:Y3 \66\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP0 (\7\:I22\|net013 \20\:Y2 \137\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP2 (\13\:net0127 \7\:I14\|net013 \125\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP2 (\21\:net0115 \5\:I17\|net013 \60\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MP1 (\64\:vdd! \14\:X0 \7\:I25\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP1 (\129\:vdd! \18\:X0 \7\:I22\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP4 (\63\:vdd! \22\:net075 \4\:I8\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP4 (\62\:vdd! \22\:net47 \4\:I7\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP1 (\4\:I14\|net013 \22\:X1 \141\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP0 (\4\:I17\|net013 \22\:Y1 \131\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MP2 (\67\:vdd! \3\:I25\|net013 \12\:net075 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP2 (\142\:vdd! \3\:I22\|net013 \12\:net47 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP1 (I8\|I1\|net8 \13\:net44 \1\:Z3 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP1 (I7\|I1\|net8 \13\:net32 \1\:Z2 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP0 (\132\:vdd! \16\:Y0 \4\:I14\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP1 (\124\:vdd! \10\:X0 \4\:I17\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP0 (\65\:vdd! I8\|I1\|Ai I8\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP0 (\128\:vdd! I7\|I1\|Ai I7\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP1 (\7\:I8\|I3\|net013 \17\:net44 \70\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP2 (I8\|I1\|net022 \5\:I8\|I1\|Bi \69\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP1 (\7\:I7\|I3\|net013 \17\:net32 \147\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP2 (I7\|I1\|net022 \5\:I7\|I1\|Bi \136\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP2 (\12\:net35 \4\:I6\|I3\|net013 \158\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP5 (\140\:vdd! \3\:net0127 \5\:I6\|I1\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP0 (\68\:vdd! \8\:net075 \7\:I8\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP3 (\7\:Z3 \16\:net075 I8\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP0 (\143\:vdd! \8\:net47 \7\:I7\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP3 (\7\:Z2 \16\:net47 I7\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP1 (\164\:vdd! \8\:net0127 \7\:I6\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP2 (\150\:vdd! \4\:I6\|I1\|Bi I6\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP0 (\73\:vdd! \13\:Y3 \7\:I24\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP0 (I6\|I1\|net8 \6\:I6\|I1\|Ai \163\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP0 (\165\:vdd! \13\:Y2 \7\:I23\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP1 (\5\:Z1 \5\:net0127 I6\|I1\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP2 (\13\:net095 \7\:I16\|net013 \172\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP0 (\7\:I6\|I3\|net013 \14\:net0115 \171\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP3 (I6\|I1\|net022 \16\:net0115 \6\:Z1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP5 (I8\|I1\|Bi \15\:net44 \72\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP2 (\71\:vdd! \3\:I8\|I3\|net013 \13\:net5 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP5 (I7\|I1\|Bi \15\:net32 \146\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP2 (\151\:vdd! \3\:I7\|I3\|net013 \13\:net45 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP4 (\4\:I6\|I1\|Ai net0115 \174\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP1 (\4\:I16\|net013 \6\:X1 \185\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP0 (\157\:vdd! \5\:I2\|I4\|Ai I2\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP1 (\7\:I24\|net013 \12\:X1 \74\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP0 (\175\:vdd! \16\:Y1 \4\:I16\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP1 (\7\:I23\|net013 \17\:X1 \166\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP2 (\19\:net34 \7\:I13\|net013 \190\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP1 (I11\|I4\|net8 \13\:net0100 \15\:I11\|net3 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP2 (\76\:vdd! \3\:I24\|net013 \16\:net078 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP2 (\176\:vdd! \3\:I23\|net013 \16\:net28 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP1 (I2\|I4\|net8 \13\:net29 \15\:I2\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP0 (\75\:vdd! \5\:I11\|I4\|Ai I11\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MP0 (\7\:I1\|net1 \6\:net095 \225\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP4 (I1\|I4\|Ai \8\:net095 \206\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MP1 (\215\:vdd! \8\:net34 \7\:I1\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP0 (I1\|I4\|net8 \5\:I1\|I4\|Ai \195\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP5 (\203\:vdd! \9\:net34 \2\:I1\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP1 (\20\:I1\|net3 \16\:net34 I1\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP1 (\4\:I13\|net013 \24\:X2 \202\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP0 (\201\:vdd! \19\:Y0 \4\:I13\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP3 (I1\|I4\|net022 \4\:net095 \15\:I1\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP2 (\184\:vdd! \5\:I1\|I4\|Bi I1\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MP1 (\12\:net26 \7\:I2\|net6 \214\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MP0 (\207\:vdd! \3\:I2\|net1 \12\:net26 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MP1 (\7\:I2\|net1 \15\:net29 \196\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MP0 (\186\:vdd! \8\:net28 \7\:I2\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP4 (\177\:vdd! \9\:net28 \2\:I2\|I4\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP5 (\251\:vdd! \9\:net35 I1\|I3\|Bi vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP2 (I1\|I3\|net022 \5\:I1\|I3\|Bi \239\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP3 (\6\:net32 \3\:I1\|net3 I1\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MP0 (I1\|net6 \5\:I1\|net3 \250\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MP1 (\249\:vdd! \5\:net35 I1\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP1 (I1\|I3\|net8 \4\:net35 \7\:net32 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP0 (\228\:vdd! I1\|I3\|Ai I1\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MP1 (\12\:net31 \7\:I1\|net6 \240\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MP0 (\234\:vdd! \3\:I1\|net1 \12\:net31 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP4 (\218\:vdd! \11\:I1\|net3 \6\:I1\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP5 (\5\:I3\|I3\|Bi \9\:net26 \241\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP5 (\221\:vdd! \9\:net45 I2\|I3\|Bi vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MP0 (I2\|net6 \5\:I2\|net3 \220\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MP1 (\219\:vdd! \5\:net45 I2\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP2 (\224\:vdd! \2\:I3\|I3\|Bi I3\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP2 (I2\|I3\|net022 \5\:I2\|I3\|Bi \213\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP3 (\6\:net44 \3\:I2\|net3 I2\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP1 (I2\|I3\|net8 \4\:net45 \7\:net44 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP0 (\200\:vdd! I2\|I3\|Ai I2\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP4 (\189\:vdd! \12\:I2\|net3 \6\:I2\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP5 (I2\|I4\|Bi \17\:net29 \180\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP2 (I2\|I4\|net022 \5\:I2\|I4\|Bi \170\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP3 (\20\:I2\|net3 \19\:net28 I2\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP0 (\84\:vdd! I11\|I3\|Ai I11\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MP1 (\12\:net1 \7\:I11\|net6 \85\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MP0 (\83\:vdd! \3\:I11\|net1 \12\:net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP4 (\82\:vdd! \11\:I11\|net3 \6\:I11\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MP1 (\7\:I11\|net1 \15\:net0100 \81\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP5 (I11\|I4\|Bi \17\:net0100 \80\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MP0 (\79\:vdd! \8\:net078 \7\:I11\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP2 (I11\|I4\|net022 \5\:I11\|I4\|Bi \78\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP4 (\77\:vdd! \9\:net078 \2\:I11\|I4\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP3 (\20\:I11\|net3 \19\:net078 I11\|I4\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP2 (\90\:vdd! \2\:I10\|I3\|Bi I10\|I3\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP5 (\5\:I10\|I3\|Bi \9\:net1 \91\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP5 (\88\:vdd! \10\:net5 I11\|I3\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP2 (I11\|I3\|net022 \5\:I11\|I3\|Bi \89\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP3 (\6\:Z4 \3\:I11\|net3 I11\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MP0 (I11\|net6 \5\:I11\|net3 \87\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MP1 (\86\:vdd! \6\:net5 I11\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP1 (I11\|I3\|net8 \5\:net5 \7\:Z4 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP4 (\4\:I0\|I3\|Ai \10\:I0\|net3 \275\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MP1 (\23\:net55 \7\:I0\|net1 \282\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MP0 (\276\:vdd! \3\:I0\|net6 \23\:net55 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP0 (I0\|I3\|net8 \6\:I0\|I3\|Ai \263\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP1 (\6\:net29 \7\:net31 I0\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MP1 (\5\:I0\|net6 \6\:net31 \271\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MP0 (\270\:vdd! \17\:I0\|net3 \5\:I0\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP3 (I0\|I3\|net022 \18\:I0\|net3 \7\:net29 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP2 (\254\:vdd! \5\:I0\|I3\|Bi I0\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP5 (\3\:I0\|I3\|Bi \9\:net31 \269\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MP0 (\3\:I3\|net1 \18\:net087 \277\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MP1 (\264\:vdd! \12\:net54 \3\:I3\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MP1 (\13\:net21 \7\:I3\|net1 \255\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MP0 (\248\:vdd! \3\:I3\|net6 \13\:net21 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MP1 (\5\:I3\|net6 \6\:net26 \243\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MP0 (\242\:vdd! \17\:I3\|net3 \5\:I3\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP3 (I0\|I4\|net022 \6\:net38 I0\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP2 (\3\:net087 \7\:I21\|net013 \287\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP4 (I0\|I4\|Ai \17\:net38 \315\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP2 (\294\:vdd! \4\:I0\|I4\|Bi I0\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MP0 (\3\:I0\|net1 \18\:net38 \301\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP4 (I3\|I4\|Ai \17\:net087 \286\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP5 (\284\:vdd! \11\:net39 \7\:I0\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MP1 (\285\:vdd! \6\:net39 \3\:I0\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP1 (\317\:vdd! \3\:X2 \4\:I18\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP0 (I0\|I4\|net8 \5\:I0\|I4\|Ai \306\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP0 (\4\:I21\|net013 \10\:Y2 \295\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP1 (\4\:I0\|net3 \8\:net39 I0\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP1 (\291\:vdd! \17\:X2 \4\:I21\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP2 (\5\:net38 \7\:I18\|net013 \316\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP0 (I10\|I3\|net8 \6\:I10\|I3\|Ai \94\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP0 (I3\|I3\|net8 \6\:I3\|I3\|Ai \233\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP1 (\6\:Z5 \7\:net1 I10\|I3\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MP1 (\5\:I10\|net6 \6\:net1 \93\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP1 (\6\:net0100 \7\:net26 I3\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MP0 (\92\:vdd! \17\:I10\|net3 \5\:I10\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP3 (I10\|I3\|net022 \18\:I10\|net3 \7\:Z5 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP3 (I3\|I3\|net022 \18\:I3\|net3 \7\:net0100 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP5 (\99\:vdd! \17\:net17 \7\:I10\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP5 (\258\:vdd! \17\:net54 \7\:I3\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MP1 (\98\:vdd! \12\:net17 \3\:I10\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP4 (\4\:I10\|I3\|Ai \10\:I10\|net3 \97\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP4 (\4\:I3\|I3\|Ai \10\:I3\|net3 \247\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MP1 (\14\:net15 \7\:I10\|net1 \96\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MP0 (\95\:vdd! \3\:I10\|net6 \14\:net15 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP3 (I10\|I4\|net022 \6\:net8 I10\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP3 (I3\|I4\|net022 \6\:net087 I3\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP4 (\4\:I10\|I4\|Ai \17\:net8 \102\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP2 (\101\:vdd! \4\:I10\|I4\|Bi I10\|I4\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP2 (\268\:vdd! \4\:I3\|I4\|Bi I3\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MP0 (\3\:I10\|net1 \18\:net8 \100\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP0 (\4\:I26\|net013 \10\:Y3 \106\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP1 (\104\:vdd! \9\:X2 \4\:I26\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP0 (I10\|I4\|net8 \2\:I10\|I4\|Ai \105\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP0 (I3\|I4\|net8 \5\:I3\|I4\|Ai \281\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP1 (\4\:I10\|net3 \14\:net17 I10\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP1 (\4\:I3\|net3 \14\:net54 I3\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP2 (\3\:net8 \7\:I26\|net013 \103\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MP1 (\5\:I4\|net6 \7\:net21 \309\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MP0 (\308\:vdd! \17\:I4\|net3 \5\:I4\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP4 (\320\:vdd! \19\:net55 \4\:I5\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP2 (\3\:net39 \7\:I12\|net013 \335\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP5 (\5\:I4\|I3\|Bi \10\:net21 \307\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP0 (\4\:I18\|net013 \9\:Y1 \325\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP0 (\348\:vdd! \8\:net55 \7\:I5\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP3 (\7\:net54 \13\:net55 I5\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MP1 (\15\:net16 \7\:I4\|net1 \321\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP1 (I5\|I1\|net8 \7\:net093 net54 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MP0 (\314\:vdd! \3\:I4\|net6 \15\:net16 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP1 (\4\:I12\|net013 \23\:X3 \347\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP0 (\330\:vdd! I5\|I1\|Ai I5\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP0 (\336\:vdd! \22\:Y0 \4\:I12\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP4 (I4\|I4\|Ai \14\:net090 \353\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP5 (I5\|I1\|Bi \9\:net093 \351\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP2 (\357\:vdd! \3\:I5\|I3\|net013 \2\:net19 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MP0 (\3\:I4\|net1 \16\:net090 \341\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP1 (\7\:I5\|I3\|net013 \11\:net093 \352\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP2 (I5\|I1\|net022 \5\:I5\|I1\|Bi \340\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MP1 (\331\:vdd! \10\:net19 \3\:I4\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP1 (\4\:I20\|net013 \12\:X3 \360\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP0 (\4\:I15\|net013 \12\:Y0 \367\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP1 (\4\:I19\|net013 \15\:X3 \369\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP0 (\355\:vdd! \3\:Y2 \4\:I20\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP1 (\363\:vdd! \4\:X0 \4\:I15\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP0 (\368\:vdd! \3\:Y1 \4\:I19\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP2 (\5\:net090 \7\:I20\|net013 \354\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP2 (\1\:Z0 \5\:I15\|net013 \359\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP2 (\3\:net093 \7\:I19\|net013 \364\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP4 (\4\:I4\|I3\|Ai \10\:I4\|net3 \313\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP0 (I4\|I3\|net8 \6\:I4\|I3\|Ai \300\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP1 (\8\:net17 \8\:net21 I4\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP3 (I4\|I3\|net022 \18\:I4\|net3 \9\:net17 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP2 (\290\:vdd! \2\:I4\|I3\|Bi I4\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MP1 (\115\:vdd! \5\:net16 \3\:I9\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP4 (\4\:I9\|I3\|Ai \10\:I9\|net3 \114\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MP1 (\3\:Z7 \7\:I9\|net1 \113\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MP0 (\112\:vdd! \3\:I9\|net6 \3\:Z7 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP0 (I9\|I3\|net8 \6\:I9\|I3\|Ai \111\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP1 (\6\:Z6 \8\:net15 I9\|I3\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MP1 (\5\:I9\|net6 \7\:net15 \110\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MP0 (\109\:vdd! \17\:I9\|net3 \5\:I9\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP3 (I9\|I3\|net022 \18\:I9\|net3 \7\:Z6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP2 (\107\:vdd! \2\:I9\|I3\|Bi I9\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP5 (\5\:I9\|I3\|Bi \10\:net15 \108\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP3 (I4\|I4\|net022 \6\:net090 I4\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP3 (I9\|I4\|net022 \6\:net13 I9\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP4 (I9\|I4\|Ai \14\:net13 \119\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP2 (\334\:vdd! \4\:I4\|I4\|Bi I4\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP2 (\118\:vdd! \4\:I9\|I4\|Bi I9\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MP0 (\3\:I9\|net1 \16\:net13 \117\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP5 (\324\:vdd! \15\:net19 \7\:I4\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP5 (\116\:vdd! \10\:net16 \7\:I9\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP1 (\4\:I27\|net013 \9\:X3 \58\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP0 (\121\:vdd! \3\:Y3 \4\:I27\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP0 (I4\|I4\|net8 \5\:I4\|I4\|Ai \346\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP0 (I9\|I4\|net8 \5\:I9\|I4\|Ai \122\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP1 (\4\:I4\|net3 \12\:net19 I4\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP1 (\4\:I9\|net3 \7\:net16 I9\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP2 (\5\:net13 \7\:I27\|net013 \120\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN0 (I25\|net9 \18\:Y3 \21\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN0 (I22\|net9 \18\:Y2 \317\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN2 (\11\:net0127 \5\:I14\|net013 \287\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN2 (\23\:net0115 \7\:I17\|net013 \319\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN1 (\5\:I25\|net013 \15\:X0 I25\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN1 (\5\:I22\|net013 \19\:X0 I22\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN4 (\293\:gnd! \21\:net075 \6\:I8\|I1\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN4 (\1\:gnd! \21\:net47 \6\:I7\|I1\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN1 (I14\|net9 \19\:X1 \3\:I14\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN0 (I17\|net9 \24\:Y1 \3\:I17\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN2 (\23\:gnd! \4\:I25\|net013 \10\:net075 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN2 (\315\:gnd! \4\:I22\|net013 \10\:net47 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN2 (I8\|I1\|net17 \13\:net075 \6\:Z3 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN2 (I7\|I1\|net17 \13\:net47 \6\:Z2 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN0 (\280\:gnd! \14\:Y0 I14\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN1 (\318\:gnd! \9\:X0 I17\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN3 (\290\:gnd! \12\:net44 I8\|I1\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN3 (\22\:gnd! \12\:net32 I7\|I1\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN1 (I8\|I3\|net9 \19\:net44 \24\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN1 (I8\|I1\|net32 \7\:I8\|I1\|Bi \282\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN1 (I7\|I3\|net9 \19\:net32 \309\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN1 (I7\|I1\|net32 \7\:I7\|I1\|Bi \25\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN2 (\10\:net35 I6\|I3\|net013 \270\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN5 (\312\:gnd! \7\:net0127 \7\:I6\|I1\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN0 (\5\:I8\|I3\|net013 \9\:net075 I8\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN0 (\5\:Z3 \3\:I8\|I1\|Ai I8\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN0 (\5\:I7\|I3\|net013 \9\:net47 I7\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN0 (\5\:Z2 \3\:I7\|I1\|Ai I7\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN1 (\262\:gnd! \10\:net0127 I6\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN1 (\310\:gnd! \3\:I6\|I1\|Bi I6\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN0 (\5\:I24\|net013 \14\:Y3 I24\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN3 (I6\|I1\|net17 \6\:net0127 \304\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN0 (\5\:I23\|net013 \14\:Y2 I23\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN2 (\7\:Z1 \19\:net0115 I6\|I1\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN2 (\11\:net095 \5\:I16\|net013 \253\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN0 (I6\|I3\|net9 \12\:net0115 \5\:I6\|I3\|net013 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN0 (I6\|I1\|net32 \5\:I6\|I1\|Ai \1\:Z1 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN5 (\3\:I8\|I1\|Bi \16\:net44 \274\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN2 (\26\:gnd! \4\:I8\|I3\|net013 \14\:net5 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN5 (\3\:I7\|I1\|Bi \16\:net32 \27\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN2 (\307\:gnd! \4\:I7\|I3\|net013 \14\:net45 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN4 (\3\:I6\|I1\|Ai \4\:net0115 \300\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN1 (I16\|net9 \4\:X1 \3\:I16\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN3 (\29\:gnd! \12\:net29 I2\|I4\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN1 (I24\|net9 \10\:X1 \28\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN0 (\246\:gnd! \17\:Y1 I16\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN1 (I23\|net9 \15\:X1 \302\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN2 (\17\:net34 \5\:I13\|net013 \240\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN2 (I11\|I4\|net17 \17\:net078 \18\:I11\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN2 (\30\:gnd! \4\:I24\|net013 \14\:net078 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN2 (\299\:gnd! \4\:I23\|net013 \15\:net28 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN2 (I2\|I4\|net17 \17\:net28 \18\:I2\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN3 (\264\:gnd! \12\:net0100 I11\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN1 (\19\:I1\|net3 \4\:I1\|I4\|Bi I1\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MN1 (I2\|I0\|net9 \19\:net29 \292\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MN0 (\5\:I2\|net1 \11\:net28 I2\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN1 (I13\|net9 \22\:X2 \3\:I13\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN0 (\232\:gnd! \17\:Y0 I13\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN3 (I1\|I4\|net17 \14\:net34 \18\:I1\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN4 (\296\:gnd! \5\:net28 I2\|I4\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN2 (\297\:gnd! \3\:net095 I1\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN5 (\3\:I11\|I4\|Bi \18\:net0100 \247\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MN0 (\5\:I11\|net1 \11\:net078 I11\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN5 (\3\:I2\|I4\|Bi \18\:net29 \33\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN1 (I11\|I4\|net32 \7\:I11\|I4\|Bi \249\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN4 (\31\:gnd! \5\:net078 I11\|I4\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN1 (I2\|I4\|net32 \7\:I2\|I4\|Bi \32\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN0 (\19\:I11\|net3 \4\:I11\|I4\|Ai I11\|I4\|net32 0) nmos1 \ + w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN0 (\19\:I2\|net3 \4\:I2\|I4\|Ai I2\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MN0 (I1\|I0\|net9 \10\:net095 \218\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN4 (\3\:I1\|I4\|Ai \9\:net095 \283\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MN1 (I2\|I1\|net9 \5\:I2\|net6 \277\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MN1 (\5\:I1\|net1 \11\:net34 I1\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MN0 (\10\:net26 \4\:I2\|net1 I2\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN0 (I1\|I4\|net32 \7\:I1\|I4\|Ai \286\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN5 (\227\:gnd! \5\:net34 I1\|I4\|Bi 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN2 (I2\|I3\|net17 I2\|net3 net44 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN3 (\220\:gnd! \4\:net5 I11\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MN1 (I11\|I1\|net9 \5\:I11\|net6 \37\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN3 (\36\:gnd! \3\:net45 I2\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MN0 (\10\:net1 \4\:I11\|net1 I11\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN4 (\234\:gnd! \10\:I11\|net3 \5\:I11\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN4 (\35\:gnd! \11\:I2\|net3 \5\:I2\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MN1 (I11\|I0\|net9 \19\:net0100 \34\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MN1 (\203\:gnd! \7\:net35 I1\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN2 (I1\|I3\|net17 I1\|net3 net32 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN5 (\259\:gnd! \8\:net45 \4\:I2\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN3 (\265\:gnd! \3\:net35 I1\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MN1 (I1\|I1\|net9 \5\:I1\|net6 \210\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MN0 (I2\|I2\|net9 \6\:I2\|net3 \3\:I2\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MN0 (\10\:net31 \4\:I1\|net1 I1\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN4 (\275\:gnd! \10\:I1\|net3 \5\:I1\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MN1 (\268\:gnd! \7\:net45 I2\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN5 (\39\:gnd! \9\:net5 \4\:I11\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN1 (I11\|I3\|net32 \6\:I11\|I3\|Bi \206\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN1 (I2\|I3\|net32 \6\:I2\|I3\|Bi \40\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN0 (\4\:Z4 \3\:I11\|I3\|Ai I11\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN0 (\4\:net44 \3\:I2\|I3\|Ai I2\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MN0 (I11\|I2\|net9 \6\:I11\|net3 \3\:I11\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MN1 (\38\:gnd! \8\:net5 I11\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN2 (I11\|I3\|net17 I11\|net3 \2\:Z4 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN1 (\198\:gnd! \3\:I10\|I3\|Bi I10\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN5 (\6\:I10\|I3\|Bi \3\:net1 \44\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN1 (\45\:gnd! \3\:I3\|I3\|Bi I3\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN5 (\6\:I3\|I3\|Bi \3\:net26 \243\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN5 (\196\:gnd! \8\:net35 \4\:I1\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN1 (I1\|I3\|net32 \6\:I1\|I3\|Bi \251\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN0 (\4\:net32 \3\:I1\|I3\|Ai I1\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MN0 (I1\|I2\|net9 \6\:I1\|net3 \3\:I1\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MN1 (I0\|I2\|net9 \4\:net31 \185\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MN1 (\224\:gnd! \4\:I3\|net6 I3\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MN0 (\7\:I0\|net6 \16\:I0\|net3 I0\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN0 (I0\|I3\|net32 \5\:I0\|I3\|Ai net29 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MN1 (I3\|I2\|net9 \4\:net26 \230\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN1 (\237\:gnd! \6\:I0\|I3\|Bi I0\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN5 (\4\:I0\|I3\|Bi \3\:net31 \190\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MN0 (\7\:I3\|net6 \16\:I3\|net3 I3\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MN0 (I3\|I0\|net9 \13\:net087 I3\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN4 (\3\:I0\|I3\|Ai \12\:I0\|net3 \208\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MN0 (I0\|I1\|net9 \5\:I0\|net1 \22\:net55 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MN1 (\215\:gnd! \16\:net54 I3\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MN1 (\179\:gnd! \4\:I0\|net6 I0\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN3 (I0\|I3\|net17 \8\:net31 \221\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MN0 (I3\|I1\|net9 \5\:I3\|net1 \11\:net21 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN2 (\4\:net29 \20\:I0\|net3 I0\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN0 (I0\|I4\|net32 \4\:I0\|I4\|Ai \5\:I0\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN2 (net087 \5\:I21\|net013 \183\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN4 (\2\:I0\|I4\|Ai \19\:net38 \165\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN1 (\188\:gnd! \3\:I0\|I4\|Bi I0\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MN0 (I0\|I0\|net9 \13\:net38 I0\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN4 (\2\:I3\|I4\|Ai \19\:net087 \194\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN5 (\201\:gnd! \12\:net39 \5\:I0\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MN1 (\172\:gnd! \10\:net39 I0\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN1 (\151\:gnd! \4\:X2 I18\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN3 (I0\|I4\|net17 \9\:net39 \169\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN0 (I21\|net9 \8\:Y2 \3\:I21\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN2 (\7\:I0\|net3 \8\:net38 I0\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN1 (\176\:gnd! \18\:X2 I21\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN2 (\3\:net38 \5\:I18\|net013 \159\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN3 (I10\|I3\|net17 \8\:net1 \191\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN3 (I3\|I3\|net17 \8\:net26 \55\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN2 (\4\:Z5 \20\:I10\|net3 I10\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MN1 (I10\|I2\|net9 \4\:net1 \48\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN2 (\4\:net0100 \20\:I3\|net3 I3\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MN0 (\7\:I10\|net6 \16\:I10\|net3 I10\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN0 (I10\|I3\|net32 \5\:I10\|I3\|Ai \1\:Z5 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN0 (I3\|I3\|net32 \5\:I3\|I3\|Ai net0100 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN5 (\167\:gnd! \18\:net17 \5\:I10\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN5 (\61\:gnd! \18\:net54 \5\:I3\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MN1 (\54\:gnd! \16\:net17 I10\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN4 (\3\:I10\|I3\|Ai \12\:I10\|net3 \181\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN4 (\3\:I3\|I3\|Ai \12\:I3\|net3 \56\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MN0 (I10\|I1\|net9 \5\:I10\|net1 \13\:net15 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MN1 (\50\:gnd! \4\:I10\|net6 I10\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN0 (I10\|I4\|net32 I10\|I4\|Ai \5\:I10\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN0 (I3\|I4\|net32 \4\:I3\|I4\|Ai \5\:I3\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN4 (\5\:I10\|I4\|Ai \19\:net8 \60\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN1 (\161\:gnd! \3\:I10\|I4\|Bi I10\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN1 (\62\:gnd! \3\:I3\|I4\|Bi I3\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MN0 (I10\|I0\|net9 \13\:net8 I10\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN0 (I26\|net9 \8\:Y3 \3\:I26\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN1 (\67\:gnd! \10\:X2 I26\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN3 (I10\|I4\|net17 \15\:net17 \146\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN3 (I3\|I4\|net17 \15\:net54 \72\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN2 (\7\:I10\|net3 \8\:net8 I10\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN2 (\7\:I3\|net3 \8\:net087 I3\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN2 (net8 \5\:I26\|net013 \65\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MN1 (I4\|I2\|net9 \5\:net21 \148\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MN0 (\7\:I4\|net6 \16\:I4\|net3 I4\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN4 (\156\:gnd! \18\:net55 \6\:I5\|I1\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN2 (net39 \5\:I12\|net013 \144\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN5 (\6\:I4\|I3\|Bi \4\:net21 \163\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN0 (I18\|net9 \11\:Y1 \3\:I18\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN0 (\5\:I5\|I3\|net013 \9\:net55 I5\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN0 (\5\:net54 \3\:I5\|I1\|Ai I5\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MN0 (I4\|I1\|net9 \5\:I4\|net1 \14\:net16 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN2 (I5\|I1\|net17 \10\:net55 \6\:net54 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MN1 (\142\:gnd! \4\:I4\|net6 I4\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN1 (I12\|net9 \21\:X3 \3\:I12\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN3 (\154\:gnd! \6\:net093 I5\|I1\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN0 (\139\:gnd! \20\:Y0 I12\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN4 (\2\:I4\|I4\|Ai \17\:net090 \119\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN5 (\3\:I5\|I1\|Bi \10\:net093 \125\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN2 (\122\:gnd! \4\:I5\|I3\|net013 \3\:net19 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MN0 (I4\|I0\|net9 \9\:net090 I4\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN1 (I5\|I3\|net9 \13\:net093 \130\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN1 (I5\|I1\|net32 \7\:I5\|I1\|Bi \128\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MN1 (\136\:gnd! \14\:net19 I4\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN1 (I20\|net9 \10\:X3 \3\:I20\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN0 (I15\|net9 \23\:Y0 \3\:I15\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN1 (I19\|net9 \13\:X3 \3\:I19\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN0 (\104\:gnd! \4\:Y2 I20\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN1 (\110\:gnd! \3\:X0 I15\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN0 (\107\:gnd! \4\:Y1 I19\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN2 (\3\:net090 \5\:I20\|net013 \112\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN2 (\3\:Z0 \7\:I15\|net013 \117\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN2 (net093 \5\:I19\|net013 \114\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN2 (\6\:net17 \20\:I4\|net3 I4\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN2 (\4\:Z6 \20\:I9\|net3 I9\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MN1 (I9\|I2\|net9 \5\:net15 \75\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MN0 (\7\:I9\|net6 \16\:I9\|net3 I9\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN0 (I4\|I3\|net32 \5\:I4\|I3\|Ai \3\:net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN0 (I9\|I3\|net32 \5\:I9\|I3\|Ai \2\:Z6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN1 (\73\:gnd! \3\:I4\|I3\|Bi I4\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN1 (\134\:gnd! \3\:I9\|I3\|Bi I9\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN5 (\6\:I9\|I3\|Bi \4\:net15 \71\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MN1 (\79\:gnd! \9\:net16 I9\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN4 (\3\:I4\|I3\|Ai \12\:I4\|net3 \83\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN4 (\3\:I9\|I3\|Ai \12\:I9\|net3 \116\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MN0 (I9\|I1\|net9 \5\:I9\|net1 \2\:Z7 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MN1 (\77\:gnd! \4\:I9\|net6 I9\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN3 (I4\|I3\|net17 \9\:net21 \80\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN3 (I9\|I3\|net17 \9\:net15 \124\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN0 (I4\|I4\|net32 \4\:I4\|I4\|Ai \5\:I4\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN0 (I9\|I4\|net32 \4\:I9\|I4\|Ai \5\:I9\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN4 (\2\:I9\|I4\|Ai \17\:net13 \86\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN1 (\87\:gnd! \3\:I4\|I4\|Bi I4\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN1 (\101\:gnd! \3\:I9\|I4\|Bi I9\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MN0 (I9\|I0\|net9 \9\:net13 I9\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN5 (\84\:gnd! \16\:net19 \5\:I4\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN5 (\109\:gnd! \11\:net16 \5\:I9\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN1 (I27\|net9 \7\:X3 \3\:I27\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN0 (\92\:gnd! \4\:Y3 I27\|net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN3 (I4\|I4\|net17 \13\:net19 \96\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN3 (I9\|I4\|net17 \8\:net16 \95\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN2 (\7\:I4\|net3 \8\:net090 I4\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN2 (\7\:I9\|net3 \8\:net13 I9\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN2 (\3\:net13 \5\:I27\|net013 \90\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..27c6fd6584780c0ea944b8bd4e0f2cb72aa1ec12 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "4X4_multiplier" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "vdd! gnd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/4X4_multiplier/av_extracted" "multiplier_low_4X4_multiplier_av_extracted" ) + ) +( term + ) +( param + ) +( "multiplier_low_4X4_multiplier_av_extracted" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..dfb739e4b193429a708acaf79d58228a6c06775f --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlist @@ -0,0 +1,2919 @@ + +// Library name: multiplier_low +// Cell name: 4X4_multiplier +// View name: av_extracted +rd1 (\8\:net19 \5\:net19) resistor r=8.0091 c=0 +rd2 (\12\:net16 \3\:net16) resistor r=5.8364 c=0 +rd3 (\24\:X3 \25\:X3) resistor r=3.1579 c=0 +rd4 (\25\:X3 \26\:X3) resistor r=0.5024 c=0 +rd5 (\26\:X3 \17\:X3) resistor r=5.0228 c=0 +rd6 (\17\:X3 \16\:X3) resistor r=4.8777 c=0 +rd7 (\25\:X3 \18\:X3) resistor r=0.04452 c=0 +rd8 (\26\:X3 X3) resistor r=1.8728 c=0 +rd9 (\20\:net17 net17) resistor r=7.2124 c=0 +rd10 (\20\:net54 \8\:net54) resistor r=8.6175 c=0 +rd11 (\12\:net15 net15) resistor r=7.3099 c=0 +rd12 (\14\:net21 net21) resistor r=5.4346 c=0 +rd13 (\8\:net0100 \11\:net0100) resistor r=4.2422 c=0 +rd14 (\8\:net29 \11\:net29) resistor r=4.6625 c=0 +rd15 (X2 \25\:X2) resistor r=2.0091 c=0 +rd16 (\25\:X2 \6\:X2) resistor r=4.3508 c=0 +rd17 (\25\:X2 \26\:X2) resistor r=4.9199 c=0 +rd18 (\26\:X2 \14\:X2) resistor r=9.0609 c=0 +rd19 (\25\:X2 \21\:X2) resistor r=4.2095 c=0 +rd20 (\26\:X2 \15\:X2) resistor r=3.9144 c=0 +rd21 (\11\:net45 \10\:net45) resistor r=3.8783 c=0 +rd22 (\11\:net5 \3\:net5) resistor r=4.1 c=0 +rd23 (\11\:net44 \8\:net44) resistor r=2.3746 c=0 +rd24 (\11\:net32 \8\:net32) resistor r=2.3184 c=0 +rd25 (\24\:X1 \3\:X1) resistor r=3.2855 c=0 +rd26 (\3\:X1 \25\:X1) resistor r=0.05722 c=0 +rd27 (\25\:X1 X1) resistor r=2.0116 c=0 +rd28 (\25\:X1 \26\:X1) resistor r=4.9159 c=0 +rd29 (\26\:X1 \9\:X1) resistor r=5.0544 c=0 +rd30 (\26\:X1 \18\:X1) resistor r=0.03024 c=0 +rd31 (X0 \25\:X0) resistor r=4.3738 c=0 +rd32 (\25\:X0 \11\:X0) resistor r=1.0865 c=0 +rd33 (\25\:X0 \24\:X0) resistor r=0.8508 c=0 +rd34 (\24\:X0 \22\:X0) resistor r=1.5696 c=0 +rd35 (\22\:X0 \23\:X0) resistor r=4.8116 c=0 +re1 (\16\:X3 \1\:X3) resistor r=4.4678 c=0 +re2 (\17\:X3 \3\:X3) resistor r=4.4712 c=0 +re3 (\5\:X3 \18\:X3) resistor r=4 c=0 +re4 (\4\:net19 \5\:net19) resistor r=0.005495 c=0 +re5 (net19 \4\:net19) resistor r=2 c=0 +re6 (\18\:net090 \2\:net090) resistor r=3.1152 c=0 +re7 (\18\:net13 \2\:net13) resistor r=3.1152 c=0 +re8 (\19\:net090 \4\:net090) resistor r=4.9649 c=0 +re9 (\4\:net13 \19\:net13) resistor r=4.9666 c=0 +re10 (\5\:net093 \2\:net093) resistor r=3.1619 c=0 +re11 (\6\:net19 \8\:net19) resistor r=2 c=0 +re12 (\3\:net16 net16) resistor r=2 c=0 +re13 (Z7 \1\:Z7) resistor r=6.021 c=0 +re14 (\8\:net54 \9\:net54) resistor r=0.004082 c=0 +re15 (\3\:net54 \9\:net54) resistor r=2 c=0 +re16 (\12\:net16 \13\:net16) resistor r=4.0411 c=0 +re17 (\6\:net55 \4\:net55) resistor r=5.3786 c=0 +re18 (\19\:X3 \24\:X3) resistor r=4 c=0 +re19 (\13\:I4\|net3 \14\:I4\|net3) resistor r=2.6847 c=0 +re20 (\14\:I4\|net3 \6\:I4\|net3) resistor r=0.9844 c=0 +re21 (\8\:I4\|net3 \14\:I4\|net3) resistor r=2 c=0 +re22 (\13\:I9\|net3 \14\:I9\|net3) resistor r=2.6847 c=0 +re23 (\14\:I9\|net3 \6\:I9\|net3) resistor r=0.9844 c=0 +re24 (\8\:I9\|net3 \14\:I9\|net3) resistor r=2 c=0 +re25 (net21 \2\:net21) resistor r=4 c=0 +re26 (net15 \2\:net15) resistor r=0.001087 c=0 +re27 (net17 \2\:net17) resistor r=0.004082 c=0 +re28 (Z6 \1\:Z6) resistor r=3.0317 c=0 +re29 (\15\:net55 \20\:net55) resistor r=4.7641 c=0 +re30 (\5\:X2 \6\:X2) resistor r=2 c=0 +re31 (\11\:X2 \14\:X2) resistor r=2 c=0 +re32 (\15\:X2 \12\:X2) resistor r=2 c=0 +re33 (\10\:net38 \2\:net38) resistor r=3.1152 c=0 +re34 (\4\:net38 \11\:net38) resistor r=5.0824 c=0 +re35 (\9\:net8 \5\:net8) resistor r=5.1152 c=0 +re36 (\11\:net8 \2\:net8) resistor r=5.0534 c=0 +re37 (\13\:net39 \2\:net39) resistor r=5.7166 c=0 +re38 (\10\:net087 \5\:net087) resistor r=3.1152 c=0 +re39 (\11\:net087 \2\:net087) resistor r=5.0993 c=0 +re40 (\21\:net55 net55) resistor r=8.1859 c=0 +re41 (\20\:net17 \19\:net17) resistor r=3.0466 c=0 +re42 (\20\:net54 \19\:net54) resistor r=3.0379 c=0 +re43 (\11\:net15 \12\:net15) resistor r=4 c=0 +re44 (\14\:net21 \12\:net21) resistor r=4.0011 c=0 +re45 (\14\:I0\|net3 \15\:I0\|net3) resistor r=0.6847 c=0 +re46 (\15\:I0\|net3 \6\:I0\|net3) resistor r=0.9844 c=0 +re47 (\8\:I0\|net3 \15\:I0\|net3) resistor r=2 c=0 +re48 (\13\:I10\|net3 \14\:I10\|net3) resistor r=2.6847 c=0 +re49 (\14\:I10\|net3 \6\:I10\|net3) resistor r=0.9844 c=0 +re50 (\8\:I10\|net3 \14\:I10\|net3) resistor r=2 c=0 +re51 (\14\:I3\|net3 \15\:I3\|net3) resistor r=0.6847 c=0 +re52 (\15\:I3\|net3 \6\:I3\|net3) resistor r=0.9844 c=0 +re53 (\8\:I3\|net3 \15\:I3\|net3) resistor r=2 c=0 +re54 (Z5 \2\:Z5) resistor r=3.1416 c=0 +re55 (\8\:net0100 \2\:net0100) resistor r=5.4502 c=0 +re56 (\8\:net29 \2\:net29) resistor r=5.86 c=0 +re57 (Z4 \1\:Z4) resistor r=3.0829 c=0 +re58 (\11\:net31 \2\:net31) resistor r=5.438 c=0 +re59 (\3\:net5 \2\:net5) resistor r=2.422 c=0 +re60 (\10\:net45 \2\:net45) resistor r=2.4508 c=0 +re61 (\11\:net1 \2\:net1) resistor r=6.1255 c=0 +re62 (\11\:net26 \2\:net26) resistor r=6.1929 c=0 +re63 (\10\:net0100 \11\:net0100) resistor r=2 c=0 +re64 (\13\:I1\|net3 \14\:I1\|net3) resistor r=2.9844 c=0 +re65 (\14\:I1\|net3 \7\:I1\|net3) resistor r=0.6847 c=0 +re66 (\12\:I1\|net3 \14\:I1\|net3) resistor r=2 c=0 +re67 (\10\:net29 \11\:net29) resistor r=2 c=0 +re68 (\19\:X2 \21\:X2) resistor r=4.0089 c=0 +re69 (\3\:net34 \13\:net34) resistor r=3.1152 c=0 +re70 (\13\:I11\|net3 \14\:I11\|net3) resistor r=2.9844 c=0 +re71 (\14\:I11\|net3 \7\:I11\|net3) resistor r=0.6847 c=0 +re72 (\12\:I11\|net3 \14\:I11\|net3) resistor r=2 c=0 +re73 (\13\:I2\|net3 \14\:I2\|net3) resistor r=2.9844 c=0 +re74 (\14\:I2\|net3 \7\:I2\|net3) resistor r=0.6847 c=0 +re75 (\9\:I2\|net3 \14\:I2\|net3) resistor r=2 c=0 +re76 (\3\:net078 \13\:net078) resistor r=3.1152 c=0 +re77 (\3\:net28 \13\:net28) resistor r=3.1152 c=0 +re78 (\18\:net34 \2\:net34) resistor r=6.3777 c=0 +re79 (\15\:net078 \2\:net078) resistor r=5.3259 c=0 +re80 (\14\:net28 \2\:net28) resistor r=5.1758 c=0 +re81 (\1\:X1 \3\:X1) resistor r=4.0933 c=0 +re82 (\8\:net44 \3\:net44) resistor r=8.0252 c=0 +re83 (\8\:X1 \9\:X1) resistor r=2.3735 c=0 +re84 (\14\:X1 \18\:X1) resistor r=2.5129 c=0 +re85 (\6\:net0115 \5\:net0115) resistor r=4.7641 c=0 +re86 (\8\:net32 \3\:net32) resistor r=9.1881 c=0 +re87 (\2\:net095 \12\:net095) resistor r=7.462 c=0 +re88 (\9\:net0115 \10\:net0115) resistor r=5.3786 c=0 +re89 (\12\:net5 \11\:net5) resistor r=4.4477 c=0 +re90 (\12\:net45 \11\:net45) resistor r=4.4706 c=0 +re91 (\11\:net44 \10\:net44) resistor r=2.7182 c=0 +re92 (\10\:net32 \11\:net32) resistor r=2.553 c=0 +re93 (\2\:net35 \11\:net35) resistor r=11.1009 c=0 +re94 (\6\:net075 \4\:net075) resistor r=5.3786 c=0 +re95 (\6\:net47 \4\:net47) resistor r=5.3786 c=0 +re96 (net075 \11\:net075) resistor r=2.6252 c=0 +re97 (\11\:net47 net47) resistor r=2.6218 c=0 +re98 (\23\:X1 \24\:X1) resistor r=4 c=0 +re99 (\11\:X0 \6\:X0) resistor r=2.0078 c=0 +re100 (\12\:net0127 net0127) resistor r=5.6983 c=0 +re101 (\22\:net0115 \20\:net0115) resistor r=7.1937 c=0 +re102 (\18\:net075 \23\:net075) resistor r=4.7641 c=0 +re103 (\18\:net47 \23\:net47) resistor r=4.7641 c=0 +re104 (\22\:X0 \21\:X0) resistor r=4.2267 c=0 +re105 (\23\:X0 \20\:X0) resistor r=4.2289 c=0 +re106 (\24\:X0 \5\:X0) resistor r=21.5123 c=0 +re107 (Z3 \3\:Z3) resistor r=3.8779 c=0 +re108 (Z2 \3\:Z2) resistor r=4.033 c=0 +re109 (Z1 \3\:Z1) resistor r=5.9155 c=0 +re110 (Y2 \21\:Y2) resistor r=1.1311 c=0 +re111 (\21\:Y2 \22\:Y2) resistor r=2.7111 c=0 +re112 (\22\:Y2 \23\:Y2) resistor r=10.4714 c=0 +re113 (\23\:Y2 \5\:Y2) resistor r=5.6954 c=0 +re114 (\21\:Y2 \17\:Y2) resistor r=1.078 c=0 +re115 (\22\:Y2 \15\:Y2) resistor r=3.023 c=0 +re116 (\23\:Y2 \6\:Y2) resistor r=3.1738 c=0 +re117 (Y3 \21\:Y3) resistor r=1.1311 c=0 +re118 (\21\:Y3 \22\:Y3) resistor r=2.8324 c=0 +re119 (\22\:Y3 \23\:Y3) resistor r=10.4206 c=0 +re120 (\23\:Y3 \5\:Y3) resistor r=5.6155 c=0 +re121 (\21\:Y3 \17\:Y3) resistor r=1.0707 c=0 +re122 (\22\:Y3 \15\:Y3) resistor r=3.0112 c=0 +re123 (\23\:Y3 \6\:Y3) resistor r=3.1534 c=0 +re124 (Z0 \2\:Z0) resistor r=20.9575 c=0 +rf1 (\1\:X3 \2\:X3) resistor r=0.01 c=0 +rf2 (\3\:X3 \4\:X3) resistor r=0.01 c=0 +rf4 (\5\:X3 \6\:X3) resistor r=0.01 c=0 +rf5 (\5\:Y3 \1\:Y3) resistor r=2.01 c=0 +rf6 (\5\:Y2 \1\:Y2) resistor r=2.01 c=0 +rf7 (\5\:X0 \1\:X0) resistor r=2.01 c=0 +rf9 (I27\|net013 \2\:I27\|net013) resistor r=0.2434 c=0 +rf10 (\2\:I27\|net013 \3\:I27\|net013) resistor r=0.3205 c=0 +rf11 (\2\:I27\|net013 \4\:I27\|net013) resistor r=0.5422 c=0 +rf12 (I20\|net013 \2\:I20\|net013) resistor r=0.2434 c=0 +rf13 (\2\:I20\|net013 \3\:I20\|net013) resistor r=0.3205 c=0 +rf14 (\2\:I20\|net013 \4\:I20\|net013) resistor r=0.5422 c=0 +rf15 (I15\|net013 \2\:I15\|net013) resistor r=0.2434 c=0 +rf16 (\2\:I15\|net013 \3\:I15\|net013) resistor r=0.3205 c=0 +rf17 (\2\:I15\|net013 \4\:I15\|net013) resistor r=0.5422 c=0 +rf18 (I19\|net013 \2\:I19\|net013) resistor r=0.2434 c=0 +rf19 (\2\:I19\|net013 \3\:I19\|net013) resistor r=0.3205 c=0 +rf20 (\2\:I19\|net013 \4\:I19\|net013) resistor r=0.5422 c=0 +rf21 (net090 \2\:net090) resistor r=2.0022 c=0 +rf22 (net13 \2\:net13) resistor r=2.0022 c=0 +rf23 (\3\:net13 \4\:net13) resistor r=0.2066 c=0 +rf24 (\4\:net13 \5\:net13) resistor r=0.6132 c=0 +rf25 (\3\:net090 \4\:net090) resistor r=0.2066 c=0 +rf26 (\4\:net090 \5\:net090) resistor r=0.6132 c=0 +rf27 (\1\:Z0 \2\:Z0) resistor r=0.6132 c=0 +rf28 (\2\:Z0 \3\:Z0) resistor r=0.2066 c=0 +rf29 (net093 \2\:net093) resistor r=0.2066 c=0 +rf30 (\2\:net093 \3\:net093) resistor r=0.6132 c=0 +rf31 (net19 \2\:net19) resistor r=0.285 c=0 +rf32 (net19 \3\:net19) resistor r=0.8307 c=0 +rf33 (I4\|net3 \2\:I4\|net3) resistor r=0.7396 c=0 +rf34 (\2\:I4\|net3 \3\:I4\|net3) resistor r=0.4087 c=0 +rf35 (\3\:I4\|net3 \4\:I4\|net3) resistor r=0.7213 c=0 +rf36 (\2\:I4\|net3 \5\:I4\|net3) resistor r=0.2896 c=0 +rf37 (\2\:I4\|net3 \6\:I4\|net3) resistor r=2.2056 c=0 +rf38 (\3\:I4\|net3 \7\:I4\|net3) resistor r=0.2841 c=0 +rf39 (I9\|net3 \2\:I9\|net3) resistor r=0.7396 c=0 +rf40 (\2\:I9\|net3 \3\:I9\|net3) resistor r=0.4087 c=0 +rf41 (\3\:I9\|net3 \4\:I9\|net3) resistor r=0.7213 c=0 +rf42 (\2\:I9\|net3 \5\:I9\|net3) resistor r=0.2896 c=0 +rf43 (\2\:I9\|net3 \6\:I9\|net3) resistor r=2.2056 c=0 +rf44 (\3\:I9\|net3 \7\:I9\|net3) resistor r=0.2841 c=0 +rf45 (I4\|I4\|Ai \2\:I4\|I4\|Ai) resistor r=0.84 c=0 +rf46 (I4\|I4\|Ai \3\:I4\|I4\|Ai) resistor r=0.2475 c=0 +rf47 (I9\|I4\|Ai \2\:I9\|I4\|Ai) resistor r=0.84 c=0 +rf48 (I9\|I4\|Ai \3\:I9\|I4\|Ai) resistor r=0.2475 c=0 +rf49 (\12\:net090 \18\:net090) resistor r=2.0267 c=0 +rf50 (\19\:net090 \15\:net090) resistor r=0.02222 c=0 +rf51 (\12\:net13 \18\:net13) resistor r=2.0267 c=0 +rf52 (\19\:net13 \15\:net13) resistor r=0.02222 c=0 +rf53 (\4\:net093 \5\:net093) resistor r=2.0111 c=0 +rf54 (I5\|I1\|Bi \2\:I5\|I1\|Bi) resistor r=0.3619 c=0 +rf55 (\2\:I5\|I1\|Bi \3\:I5\|I1\|Bi) resistor r=0.6109 c=0 +rf56 (\2\:I5\|I1\|Bi \4\:I5\|I1\|Bi) resistor r=0.2422 c=0 +rf57 (\5\:I4\|I4\|Bi \6\:I4\|I4\|Bi) resistor r=0.3789 c=0 +rf58 (\6\:I4\|I4\|Bi I4\|I4\|Bi) resistor r=0.2425 c=0 +rf59 (\6\:I4\|I4\|Bi \7\:I4\|I4\|Bi) resistor r=0.3634 c=0 +rf60 (\5\:I9\|I4\|Bi \6\:I9\|I4\|Bi) resistor r=0.3789 c=0 +rf61 (\6\:I9\|I4\|Bi I9\|I4\|Bi) resistor r=0.2425 c=0 +rf62 (\6\:I9\|I4\|Bi \7\:I9\|I4\|Bi) resistor r=0.3634 c=0 +rf63 (\6\:net19 \7\:net19) resistor r=2.0233 c=0 +rf64 (net16 \2\:net16) resistor r=2.0233 c=0 +rf65 (net55 \2\:net55) resistor r=2.01 c=0 +rf66 (\5\:I5\|I3\|net013 \6\:I5\|I3\|net013) resistor r=0.4307 c=0 +rf67 (\6\:I5\|I3\|net013 I5\|I3\|net013) resistor r=0.5507 c=0 +rf68 (\6\:I5\|I3\|net013 \7\:I5\|I3\|net013) resistor r=0.8338 c=0 +rf69 (\8\:I4\|net3 \9\:I4\|net3) resistor r=0.01 c=0 +rf70 (\8\:I9\|net3 \9\:I9\|net3) resistor r=0.01 c=0 +rf71 (\3\:net55 \4\:net55) resistor r=0.002222 c=0 +rf72 (I4\|net1 \2\:I4\|net1) resistor r=0.7023 c=0 +rf73 (\2\:I4\|net1 \3\:I4\|net1) resistor r=0.5764 c=0 +rf74 (\2\:I4\|net1 \4\:I4\|net1) resistor r=0.5108 c=0 +rf75 (I9\|net1 \2\:I9\|net1) resistor r=0.7023 c=0 +rf76 (\2\:I9\|net1 \3\:I9\|net1) resistor r=0.5764 c=0 +rf77 (\2\:I9\|net1 \4\:I9\|net1) resistor r=0.5108 c=0 +rf78 (\5\:net55 \6\:net55) resistor r=0.002222 c=0 +rf79 (net54 \2\:net54) resistor r=0.629 c=0 +rf80 (\2\:net54 \3\:net54) resistor r=0.1083 c=0 +rf81 (\3\:net54 \4\:net54) resistor r=0.1123 c=0 +rf82 (\4\:net54 \5\:net54) resistor r=0.4382 c=0 +rf83 (\2\:net54 \6\:net54) resistor r=0.4386 c=0 +rf84 (\4\:net54 \7\:net54) resistor r=0.6387 c=0 +rf85 (I4\|I3\|Ai \2\:I4\|I3\|Ai) resistor r=0.04192 c=0 +rf86 (\2\:I4\|I3\|Ai \3\:I4\|I3\|Ai) resistor r=0.6961 c=0 +rf87 (\2\:I4\|I3\|Ai \4\:I4\|I3\|Ai) resistor r=0.4006 c=0 +rf88 (I9\|I3\|Ai \2\:I9\|I3\|Ai) resistor r=0.04192 c=0 +rf89 (\2\:I9\|I3\|Ai \3\:I9\|I3\|Ai) resistor r=0.6961 c=0 +rf90 (\2\:I9\|I3\|Ai \4\:I9\|I3\|Ai) resistor r=0.4006 c=0 +rf91 (\14\:net16 \13\:net16) resistor r=0.1956 c=0 +rf92 (\13\:net16 \15\:net16) resistor r=1.0615 c=0 +rf93 (\2\:Z7 \1\:Z7) resistor r=0.1956 c=0 +rf94 (\1\:Z7 \3\:Z7) resistor r=1.0615 c=0 +rf95 (\19\:X3 \20\:X3) resistor r=0.01 c=0 +rf96 (\14\:net55 \15\:net55) resistor r=0.01 c=0 +rf97 (\15\:I4\|net3 \13\:I4\|net3) resistor r=0.08472 c=0 +rf98 (\15\:I9\|net3 \13\:I9\|net3) resistor r=0.08472 c=0 +rf99 (\3\:net21 \2\:net21) resistor r=0.1 c=0 +rf100 (\3\:net15 \2\:net15) resistor r=2.1 c=0 +rf102 (I12\|net013 \2\:I12\|net013) resistor r=0.2434 c=0 +rf103 (\2\:I12\|net013 \3\:I12\|net013) resistor r=0.3205 c=0 +rf104 (\2\:I12\|net013 \4\:I12\|net013) resistor r=0.5422 c=0 +rf105 (\4\:I5\|I1\|Ai \5\:I5\|I1\|Ai) resistor r=0.2765 c=0 +rf106 (\5\:I5\|I1\|Ai \2\:I5\|I1\|Ai) resistor r=0.04519 c=0 +rf107 (\5\:I5\|I1\|Ai \6\:I5\|I1\|Ai) resistor r=0.7634 c=0 +rf108 (\3\:net17 \4\:net17) resistor r=0.2905 c=0 +rf109 (\4\:net17 \5\:net17) resistor r=0.08276 c=0 +rf110 (\5\:net17 \6\:net17) resistor r=0.2973 c=0 +rf111 (\5\:net17 \7\:net17) resistor r=0.4127 c=0 +rf112 (\7\:net17 \8\:net17) resistor r=0.3748 c=0 +rf113 (\7\:net17 \9\:net17) resistor r=0.5859 c=0 +rf114 (\2\:net17 \4\:net17) resistor r=2 c=0 +rf115 (\2\:Z6 \1\:Z6) resistor r=0.2905 c=0 +rf116 (\1\:Z6 \3\:Z6) resistor r=0.08276 c=0 +rf117 (\3\:Z6 \4\:Z6) resistor r=0.2973 c=0 +rf118 (\3\:Z6 \5\:Z6) resistor r=0.4127 c=0 +rf119 (\5\:Z6 \6\:Z6) resistor r=0.3748 c=0 +rf120 (\5\:Z6 \7\:Z6) resistor r=0.5859 c=0 +rf121 (\16\:net55 \20\:net55) resistor r=0.01 c=0 +rf122 (\5\:I4\|net6 \6\:I4\|net6) resistor r=0.7681 c=0 +rf123 (\6\:I4\|net6 I4\|net6) resistor r=0.8057 c=0 +rf124 (\6\:I4\|net6 \7\:I4\|net6) resistor r=0.4319 c=0 +rf125 (\5\:I9\|net6 \6\:I9\|net6) resistor r=0.7681 c=0 +rf126 (\6\:I9\|net6 I9\|net6) resistor r=0.8057 c=0 +rf127 (\6\:I9\|net6 \7\:I9\|net6) resistor r=0.4319 c=0 +rf128 (net39 \2\:net39) resistor r=0.2066 c=0 +rf129 (\2\:net39 \3\:net39) resistor r=0.6132 c=0 +rf131 (I4\|I3\|Bi \4\:I4\|I3\|Bi) resistor r=0.07769 c=0 +rf132 (\4\:I4\|I3\|Bi \5\:I4\|I3\|Bi) resistor r=0.2684 c=0 +rf133 (\4\:I4\|I3\|Bi \6\:I4\|I3\|Bi) resistor r=0.5661 c=0 +rf134 (I9\|I3\|Bi \4\:I9\|I3\|Bi) resistor r=0.07769 c=0 +rf135 (\4\:I9\|I3\|Bi \5\:I9\|I3\|Bi) resistor r=0.2684 c=0 +rf136 (\4\:I9\|I3\|Bi \6\:I9\|I3\|Bi) resistor r=0.5661 c=0 +rf137 (\6\:Y3 \7\:Y3) resistor r=0.01 c=0 +rf138 (\5\:X2 \1\:X2) resistor r=2.01 c=0 +rf139 (\6\:Y2 \7\:Y2) resistor r=0.01 c=0 +rf140 (I18\|net013 \2\:I18\|net013) resistor r=0.2434 c=0 +rf141 (\2\:I18\|net013 \3\:I18\|net013) resistor r=0.3205 c=0 +rf142 (\2\:I18\|net013 \4\:I18\|net013) resistor r=0.5422 c=0 +rf143 (\11\:X2 \7\:X2) resistor r=2.01 c=0 +rf144 (\12\:X2 \13\:X2) resistor r=2.01 c=0 +rf145 (I26\|net013 \2\:I26\|net013) resistor r=0.2434 c=0 +rf146 (\2\:I26\|net013 \3\:I26\|net013) resistor r=0.3205 c=0 +rf147 (\2\:I26\|net013 \4\:I26\|net013) resistor r=0.5422 c=0 +rf148 (I21\|net013 \2\:I21\|net013) resistor r=0.2434 c=0 +rf149 (\2\:I21\|net013 \3\:I21\|net013) resistor r=0.3205 c=0 +rf150 (\2\:I21\|net013 \4\:I21\|net013) resistor r=0.5422 c=0 +rf151 (net38 \2\:net38) resistor r=2.0022 c=0 +rf152 (\3\:net38 \4\:net38) resistor r=0.2066 c=0 +rf153 (\4\:net38 \5\:net38) resistor r=0.6132 c=0 +rf154 (I0\|net3 \2\:I0\|net3) resistor r=0.7396 c=0 +rf155 (\2\:I0\|net3 \3\:I0\|net3) resistor r=0.4087 c=0 +rf156 (\3\:I0\|net3 \4\:I0\|net3) resistor r=0.7213 c=0 +rf157 (\2\:I0\|net3 \5\:I0\|net3) resistor r=0.2896 c=0 +rf158 (\2\:I0\|net3 \6\:I0\|net3) resistor r=2.2056 c=0 +rf159 (\3\:I0\|net3 \7\:I0\|net3) resistor r=0.2841 c=0 +rf160 (net8 \2\:net8) resistor r=0.2066 c=0 +rf161 (\2\:net8 \3\:net8) resistor r=0.6132 c=0 +rf162 (\4\:net8 \5\:net8) resistor r=2.0022 c=0 +rf163 (net087 \2\:net087) resistor r=0.2066 c=0 +rf164 (\2\:net087 \3\:net087) resistor r=0.6132 c=0 +rf165 (\4\:net087 \5\:net087) resistor r=2.0022 c=0 +rf166 (I0\|I4\|Ai \2\:I0\|I4\|Ai) resistor r=0.84 c=0 +rf167 (I0\|I4\|Ai \3\:I0\|I4\|Ai) resistor r=0.2475 c=0 +rf168 (\9\:net38 \10\:net38) resistor r=2.0267 c=0 +rf169 (\11\:net38 \12\:net38) resistor r=0.02222 c=0 +rf170 (I10\|net3 \2\:I10\|net3) resistor r=0.7396 c=0 +rf171 (\2\:I10\|net3 \3\:I10\|net3) resistor r=0.4087 c=0 +rf172 (\3\:I10\|net3 \4\:I10\|net3) resistor r=0.7213 c=0 +rf173 (\2\:I10\|net3 \5\:I10\|net3) resistor r=0.2896 c=0 +rf174 (\2\:I10\|net3 \6\:I10\|net3) resistor r=2.2056 c=0 +rf175 (\3\:I10\|net3 \7\:I10\|net3) resistor r=0.2841 c=0 +rf176 (\5\:I0\|I4\|Bi \6\:I0\|I4\|Bi) resistor r=0.3789 c=0 +rf177 (\6\:I0\|I4\|Bi I0\|I4\|Bi) resistor r=0.2425 c=0 +rf178 (\6\:I0\|I4\|Bi \7\:I0\|I4\|Bi) resistor r=0.3634 c=0 +rf179 (I3\|net3 \2\:I3\|net3) resistor r=0.7396 c=0 +rf180 (\2\:I3\|net3 \3\:I3\|net3) resistor r=0.4087 c=0 +rf181 (\3\:I3\|net3 \4\:I3\|net3) resistor r=0.7213 c=0 +rf182 (\2\:I3\|net3 \5\:I3\|net3) resistor r=0.2896 c=0 +rf183 (\2\:I3\|net3 \6\:I3\|net3) resistor r=2.2056 c=0 +rf184 (\3\:I3\|net3 \7\:I3\|net3) resistor r=0.2841 c=0 +rf185 (\4\:I10\|I4\|Ai \5\:I10\|I4\|Ai) resistor r=0.84 c=0 +rf186 (\4\:I10\|I4\|Ai \3\:I10\|I4\|Ai) resistor r=0.2475 c=0 +rf187 (I3\|I4\|Ai \2\:I3\|I4\|Ai) resistor r=0.84 c=0 +rf188 (I3\|I4\|Ai \3\:I3\|I4\|Ai) resistor r=0.2475 c=0 +rf189 (\10\:net8 \9\:net8) resistor r=0.02667 c=0 +rf190 (\11\:net8 \12\:net8) resistor r=0.02222 c=0 +rf191 (\13\:net39 \4\:net39) resistor r=2.0233 c=0 +rf192 (\5\:I10\|I4\|Bi \6\:I10\|I4\|Bi) resistor r=0.3789 c=0 +rf193 (\6\:I10\|I4\|Bi I10\|I4\|Bi) resistor r=0.2425 c=0 +rf194 (\6\:I10\|I4\|Bi \7\:I10\|I4\|Bi) resistor r=0.3634 c=0 +rf195 (\9\:net087 \10\:net087) resistor r=2.0267 c=0 +rf196 (\11\:net087 \12\:net087) resistor r=0.02222 c=0 +rf197 (\8\:I0\|net3 \9\:I0\|net3) resistor r=0.01 c=0 +rf198 (\5\:I3\|I4\|Bi \6\:I3\|I4\|Bi) resistor r=0.3789 c=0 +rf199 (\6\:I3\|I4\|Bi I3\|I4\|Bi) resistor r=0.2425 c=0 +rf200 (\6\:I3\|I4\|Bi \7\:I3\|I4\|Bi) resistor r=0.3634 c=0 +rf201 (I0\|net1 \2\:I0\|net1) resistor r=0.7023 c=0 +rf202 (\2\:I0\|net1 \3\:I0\|net1) resistor r=0.5764 c=0 +rf203 (\2\:I0\|net1 \4\:I0\|net1) resistor r=0.5108 c=0 +rf204 (\19\:net17 \10\:net17) resistor r=2.0233 c=0 +rf205 (I0\|I3\|Ai \2\:I0\|I3\|Ai) resistor r=0.04192 c=0 +rf206 (\2\:I0\|I3\|Ai \3\:I0\|I3\|Ai) resistor r=0.6961 c=0 +rf207 (\2\:I0\|I3\|Ai \4\:I0\|I3\|Ai) resistor r=0.4006 c=0 +rf208 (\22\:net55 \21\:net55) resistor r=0.1956 c=0 +rf209 (\21\:net55 \23\:net55) resistor r=1.0615 c=0 +rf210 (\19\:net54 \10\:net54) resistor r=2.0233 c=0 +rf211 (\8\:I10\|net3 \9\:I10\|net3) resistor r=0.01 c=0 +rf212 (\8\:I3\|net3 \9\:I3\|net3) resistor r=0.01 c=0 +rf213 (I10\|net1 \2\:I10\|net1) resistor r=0.7023 c=0 +rf214 (\2\:I10\|net1 \3\:I10\|net1) resistor r=0.5764 c=0 +rf215 (\2\:I10\|net1 \4\:I10\|net1) resistor r=0.5108 c=0 +rf216 (I3\|net1 \2\:I3\|net1) resistor r=0.7023 c=0 +rf217 (\2\:I3\|net1 \3\:I3\|net1) resistor r=0.5764 c=0 +rf218 (\2\:I3\|net1 \4\:I3\|net1) resistor r=0.5108 c=0 +rf219 (I10\|I3\|Ai \2\:I10\|I3\|Ai) resistor r=0.04192 c=0 +rf220 (\2\:I10\|I3\|Ai \3\:I10\|I3\|Ai) resistor r=0.6961 c=0 +rf221 (\2\:I10\|I3\|Ai \4\:I10\|I3\|Ai) resistor r=0.4006 c=0 +rf222 (\13\:I0\|net3 \14\:I0\|net3) resistor r=2.0847 c=0 +rf223 (\13\:net15 \11\:net15) resistor r=0.1956 c=0 +rf224 (\11\:net15 \14\:net15) resistor r=1.0615 c=0 +rf225 (net31 \2\:net31) resistor r=2.1 c=0 +rf226 (I3\|I3\|Ai \2\:I3\|I3\|Ai) resistor r=0.04192 c=0 +rf227 (\2\:I3\|I3\|Ai \3\:I3\|I3\|Ai) resistor r=0.6961 c=0 +rf228 (\2\:I3\|I3\|Ai \4\:I3\|I3\|Ai) resistor r=0.4006 c=0 +rf229 (\11\:net21 \12\:net21) resistor r=0.1956 c=0 +rf230 (\12\:net21 \13\:net21) resistor r=1.0615 c=0 +rf231 (\15\:I10\|net3 \13\:I10\|net3) resistor r=0.08472 c=0 +rf232 (net29 \2\:net29) resistor r=0.2905 c=0 +rf233 (\2\:net29 \3\:net29) resistor r=0.08276 c=0 +rf234 (\3\:net29 \4\:net29) resistor r=0.2973 c=0 +rf235 (\3\:net29 \5\:net29) resistor r=0.4127 c=0 +rf236 (\5\:net29 \6\:net29) resistor r=0.3748 c=0 +rf237 (\5\:net29 \7\:net29) resistor r=0.5859 c=0 +rf238 (net1 \2\:net1) resistor r=2.1 c=0 +rf239 (\5\:I0\|net6 \6\:I0\|net6) resistor r=0.7681 c=0 +rf240 (\6\:I0\|net6 I0\|net6) resistor r=0.8057 c=0 +rf241 (\6\:I0\|net6 \7\:I0\|net6) resistor r=0.4319 c=0 +rf242 (\13\:I3\|net3 \14\:I3\|net3) resistor r=2.0847 c=0 +rf243 (net26 \2\:net26) resistor r=2.1 c=0 +rf244 (\1\:Z5 \2\:Z5) resistor r=0.2905 c=0 +rf245 (\2\:Z5 \3\:Z5) resistor r=0.08276 c=0 +rf246 (\3\:Z5 \4\:Z5) resistor r=0.2973 c=0 +rf247 (\3\:Z5 \5\:Z5) resistor r=0.4127 c=0 +rf248 (\5\:Z5 \6\:Z5) resistor r=0.3748 c=0 +rf249 (\5\:Z5 \7\:Z5) resistor r=0.5859 c=0 +rf250 (\5\:I10\|net6 \6\:I10\|net6) resistor r=0.7681 c=0 +rf251 (\6\:I10\|net6 I10\|net6) resistor r=0.8057 c=0 +rf252 (\6\:I10\|net6 \7\:I10\|net6) resistor r=0.4319 c=0 +rf253 (net0100 \2\:net0100) resistor r=0.2905 c=0 +rf254 (\2\:net0100 \3\:net0100) resistor r=0.08276 c=0 +rf255 (\3\:net0100 \4\:net0100) resistor r=0.2973 c=0 +rf256 (\3\:net0100 \5\:net0100) resistor r=0.4127 c=0 +rf257 (\5\:net0100 \6\:net0100) resistor r=0.3748 c=0 +rf258 (\5\:net0100 \7\:net0100) resistor r=0.5859 c=0 +rf259 (\5\:I3\|net6 \6\:I3\|net6) resistor r=0.7681 c=0 +rf260 (\6\:I3\|net6 I3\|net6) resistor r=0.8057 c=0 +rf261 (\6\:I3\|net6 \7\:I3\|net6) resistor r=0.4319 c=0 +rf262 (I0\|I3\|Bi \2\:I0\|I3\|Bi) resistor r=0.07769 c=0 +rf263 (\2\:I0\|I3\|Bi \3\:I0\|I3\|Bi) resistor r=0.2684 c=0 +rf264 (\2\:I0\|I3\|Bi \4\:I0\|I3\|Bi) resistor r=0.5661 c=0 +rf265 (I1\|I3\|Bi \2\:I1\|I3\|Bi) resistor r=0.2684 c=0 +rf266 (\2\:I1\|I3\|Bi \3\:I1\|I3\|Bi) resistor r=0.07769 c=0 +rf267 (\2\:I1\|I3\|Bi \4\:I1\|I3\|Bi) resistor r=0.5661 c=0 +rf268 (I10\|I3\|Bi \4\:I10\|I3\|Bi) resistor r=0.07769 c=0 +rf269 (\4\:I10\|I3\|Bi \5\:I10\|I3\|Bi) resistor r=0.2684 c=0 +rf270 (\4\:I10\|I3\|Bi \6\:I10\|I3\|Bi) resistor r=0.5661 c=0 +rf271 (I3\|I3\|Bi \4\:I3\|I3\|Bi) resistor r=0.07769 c=0 +rf272 (\4\:I3\|I3\|Bi \5\:I3\|I3\|Bi) resistor r=0.2684 c=0 +rf273 (\4\:I3\|I3\|Bi \6\:I3\|I3\|Bi) resistor r=0.5661 c=0 +rf274 (I11\|I3\|Bi \2\:I11\|I3\|Bi) resistor r=0.2684 c=0 +rf275 (\2\:I11\|I3\|Bi \3\:I11\|I3\|Bi) resistor r=0.07769 c=0 +rf276 (\2\:I11\|I3\|Bi \4\:I11\|I3\|Bi) resistor r=0.5661 c=0 +rf277 (net32 \2\:net32) resistor r=0.2973 c=0 +rf278 (\2\:net32 \3\:net32) resistor r=0.08276 c=0 +rf279 (\3\:net32 \4\:net32) resistor r=0.2905 c=0 +rf280 (\2\:net32 \5\:net32) resistor r=0.4127 c=0 +rf281 (\5\:net32 \6\:net32) resistor r=0.5859 c=0 +rf282 (\5\:net32 \7\:net32) resistor r=0.3748 c=0 +rf283 (I2\|I3\|Bi \2\:I2\|I3\|Bi) resistor r=0.2684 c=0 +rf284 (\2\:I2\|I3\|Bi \3\:I2\|I3\|Bi) resistor r=0.07769 c=0 +rf285 (\2\:I2\|I3\|Bi \4\:I2\|I3\|Bi) resistor r=0.5661 c=0 +rf286 (net35 \2\:net35) resistor r=2.1 c=0 +rf287 (\4\:I1\|net3 \7\:I1\|net3) resistor r=2.0847 c=0 +rf288 (I1\|net6 \2\:I1\|net6) resistor r=0.7681 c=0 +rf289 (\2\:I1\|net6 \3\:I1\|net6) resistor r=0.4319 c=0 +rf290 (\2\:I1\|net6 \4\:I1\|net6) resistor r=0.8057 c=0 +rf291 (\2\:Z4 \3\:Z4) resistor r=0.2973 c=0 +rf292 (\3\:Z4 \1\:Z4) resistor r=0.08276 c=0 +rf293 (\1\:Z4 \4\:Z4) resistor r=0.2905 c=0 +rf294 (\3\:Z4 \5\:Z4) resistor r=0.4127 c=0 +rf295 (\5\:Z4 \6\:Z4) resistor r=0.5859 c=0 +rf296 (\5\:Z4 \7\:Z4) resistor r=0.3748 c=0 +rf297 (\2\:I1\|I3\|Ai \4\:I1\|I3\|Ai) resistor r=0.04192 c=0 +rf298 (\4\:I1\|I3\|Ai \5\:I1\|I3\|Ai) resistor r=0.6961 c=0 +rf299 (\4\:I1\|I3\|Ai \6\:I1\|I3\|Ai) resistor r=0.4006 c=0 +rf300 (\10\:net31 \11\:net31) resistor r=0.1956 c=0 +rf301 (\11\:net31 \12\:net31) resistor r=1.0615 c=0 +rf302 (net44 \2\:net44) resistor r=0.2973 c=0 +rf303 (\2\:net44 \3\:net44) resistor r=0.08276 c=0 +rf304 (\3\:net44 \4\:net44) resistor r=0.2905 c=0 +rf305 (\2\:net44 \5\:net44) resistor r=0.4127 c=0 +rf306 (\5\:net44 \6\:net44) resistor r=0.5859 c=0 +rf307 (\5\:net44 \7\:net44) resistor r=0.3748 c=0 +rf308 (net5 \2\:net5) resistor r=2.1 c=0 +rf309 (\8\:I1\|net3 \12\:I1\|net3) resistor r=0.01 c=0 +rf310 (\4\:I11\|net3 \7\:I11\|net3) resistor r=2.0847 c=0 +rf311 (I11\|net6 \2\:I11\|net6) resistor r=0.7681 c=0 +rf312 (\2\:I11\|net6 \3\:I11\|net6) resistor r=0.4319 c=0 +rf313 (\2\:I11\|net6 \4\:I11\|net6) resistor r=0.8057 c=0 +rf314 (net095 \2\:net095) resistor r=2.0233 c=0 +rf315 (net45 \2\:net45) resistor r=2.1 c=0 +rf316 (\4\:I2\|net3 \7\:I2\|net3) resistor r=2.0847 c=0 +rf317 (I2\|net6 \2\:I2\|net6) resistor r=0.7681 c=0 +rf318 (\2\:I2\|net6 \3\:I2\|net6) resistor r=0.4319 c=0 +rf319 (\2\:I2\|net6 \4\:I2\|net6) resistor r=0.8057 c=0 +rf320 (\2\:I11\|I3\|Ai \4\:I11\|I3\|Ai) resistor r=0.04192 c=0 +rf321 (\4\:I11\|I3\|Ai \5\:I11\|I3\|Ai) resistor r=0.6961 c=0 +rf322 (\4\:I11\|I3\|Ai \6\:I11\|I3\|Ai) resistor r=0.4006 c=0 +rf323 (\10\:net1 \11\:net1) resistor r=0.1956 c=0 +rf324 (\11\:net1 \12\:net1) resistor r=1.0615 c=0 +rf325 (net34 \2\:net34) resistor r=0.02222 c=0 +rf326 (\3\:net34 \4\:net34) resistor r=2.0267 c=0 +rf327 (\5\:I1\|net1 \6\:I1\|net1) resistor r=0.7023 c=0 +rf328 (\6\:I1\|net1 I1\|net1) resistor r=0.5108 c=0 +rf329 (\6\:I1\|net1 \7\:I1\|net1) resistor r=0.5764 c=0 +rf330 (\8\:I11\|net3 \12\:I11\|net3) resistor r=0.01 c=0 +rf331 (\2\:I2\|I3\|Ai \4\:I2\|I3\|Ai) resistor r=0.04192 c=0 +rf332 (\4\:I2\|I3\|Ai \5\:I2\|I3\|Ai) resistor r=0.6961 c=0 +rf333 (\4\:I2\|I3\|Ai \6\:I2\|I3\|Ai) resistor r=0.4006 c=0 +rf334 (I1\|I4\|Ai \2\:I1\|I4\|Ai) resistor r=0.3634 c=0 +rf335 (\2\:I1\|I4\|Ai \3\:I1\|I4\|Ai) resistor r=0.3789 c=0 +rf336 (\2\:I1\|I4\|Ai \4\:I1\|I4\|Ai) resistor r=0.2425 c=0 +rf337 (\10\:net26 \11\:net26) resistor r=0.1956 c=0 +rf338 (\11\:net26 \12\:net26) resistor r=1.0615 c=0 +rf339 (I1\|I4\|Bi \2\:I1\|I4\|Bi) resistor r=0.84 c=0 +rf340 (\2\:I1\|I4\|Bi \3\:I1\|I4\|Bi) resistor r=0.2475 c=0 +rf341 (\9\:net0100 \10\:net0100) resistor r=2.0233 c=0 +rf342 (\8\:I2\|net3 \9\:I2\|net3) resistor r=0.01 c=0 +rf343 (\9\:net29 \10\:net29) resistor r=2.0233 c=0 +rf344 (net078 \2\:net078) resistor r=0.02222 c=0 +rf345 (\3\:net078 \4\:net078) resistor r=2.0267 c=0 +rf346 (\5\:I11\|net1 \6\:I11\|net1) resistor r=0.7023 c=0 +rf347 (\6\:I11\|net1 I11\|net1) resistor r=0.5108 c=0 +rf348 (\6\:I11\|net1 \7\:I11\|net1) resistor r=0.5764 c=0 +rf349 (\19\:X2 \20\:X2) resistor r=0.01 c=0 +rf350 (\12\:net34 \13\:net34) resistor r=2.0022 c=0 +rf351 (I11\|I4\|Bi \2\:I11\|I4\|Bi) resistor r=0.3634 c=0 +rf352 (\2\:I11\|I4\|Bi \3\:I11\|I4\|Bi) resistor r=0.3789 c=0 +rf353 (\2\:I11\|I4\|Bi \4\:I11\|I4\|Bi) resistor r=0.2425 c=0 +rf354 (net28 \2\:net28) resistor r=0.02222 c=0 +rf355 (\3\:net28 \4\:net28) resistor r=2.0267 c=0 +rf356 (\5\:I2\|net1 \6\:I2\|net1) resistor r=0.7023 c=0 +rf357 (\6\:I2\|net1 I2\|net1) resistor r=0.5108 c=0 +rf358 (\6\:I2\|net1 \7\:I2\|net1) resistor r=0.5764 c=0 +rf359 (I11\|I4\|Ai \2\:I11\|I4\|Ai) resistor r=0.84 c=0 +rf360 (\2\:I11\|I4\|Ai \3\:I11\|I4\|Ai) resistor r=0.2475 c=0 +rf361 (\15\:I1\|net3 \16\:I1\|net3) resistor r=0.7213 c=0 +rf362 (\16\:I1\|net3 \17\:I1\|net3) resistor r=0.4087 c=0 +rf363 (\17\:I1\|net3 \13\:I1\|net3) resistor r=0.2056 c=0 +rf364 (\16\:I1\|net3 \18\:I1\|net3) resistor r=0.2841 c=0 +rf365 (\17\:I1\|net3 \19\:I1\|net3) resistor r=0.2896 c=0 +rf366 (\17\:I1\|net3 \20\:I1\|net3) resistor r=0.7396 c=0 +rf367 (I2\|I4\|Bi \2\:I2\|I4\|Bi) resistor r=0.3634 c=0 +rf368 (\2\:I2\|I4\|Bi \3\:I2\|I4\|Bi) resistor r=0.3789 c=0 +rf369 (\2\:I2\|I4\|Bi \4\:I2\|I4\|Bi) resistor r=0.2425 c=0 +rf370 (I2\|I4\|Ai \2\:I2\|I4\|Ai) resistor r=0.84 c=0 +rf371 (\2\:I2\|I4\|Ai \3\:I2\|I4\|Ai) resistor r=0.2475 c=0 +rf373 (I13\|net013 \2\:I13\|net013) resistor r=0.2434 c=0 +rf374 (\2\:I13\|net013 \3\:I13\|net013) resistor r=0.3205 c=0 +rf375 (\2\:I13\|net013 \4\:I13\|net013) resistor r=0.5422 c=0 +rf376 (\12\:net078 \13\:net078) resistor r=2.0022 c=0 +rf377 (\15\:I11\|net3 \16\:I11\|net3) resistor r=0.7213 c=0 +rf378 (\16\:I11\|net3 \17\:I11\|net3) resistor r=0.4087 c=0 +rf379 (\17\:I11\|net3 \13\:I11\|net3) resistor r=0.2056 c=0 +rf380 (\16\:I11\|net3 \18\:I11\|net3) resistor r=0.2841 c=0 +rf381 (\17\:I11\|net3 \19\:I11\|net3) resistor r=0.2896 c=0 +rf382 (\17\:I11\|net3 \20\:I11\|net3) resistor r=0.7396 c=0 +rf383 (\12\:net28 \13\:net28) resistor r=2.0022 c=0 +rf384 (\17\:net34 \18\:net34) resistor r=0.2066 c=0 +rf385 (\18\:net34 \19\:net34) resistor r=0.6132 c=0 +rf386 (\14\:net078 \15\:net078) resistor r=0.2066 c=0 +rf387 (\15\:net078 \16\:net078) resistor r=0.6132 c=0 +rf388 (\15\:net28 \14\:net28) resistor r=0.2066 c=0 +rf389 (\14\:net28 \16\:net28) resistor r=0.6132 c=0 +rf390 (\15\:I2\|net3 \16\:I2\|net3) resistor r=0.7213 c=0 +rf391 (\16\:I2\|net3 \17\:I2\|net3) resistor r=0.4087 c=0 +rf392 (\17\:I2\|net3 \13\:I2\|net3) resistor r=0.2056 c=0 +rf393 (\16\:I2\|net3 \18\:I2\|net3) resistor r=0.2841 c=0 +rf394 (\17\:I2\|net3 \19\:I2\|net3) resistor r=0.2896 c=0 +rf395 (\17\:I2\|net3 \20\:I2\|net3) resistor r=0.7396 c=0 +rf396 (\5\:net0115 \3\:net0115) resistor r=0.01 c=0 +rf397 (\1\:X1 \2\:X1) resistor r=0.01 c=0 +rf398 (\7\:X1 \8\:X1) resistor r=2.01 c=0 +rf399 (I6\|I1\|Ai \2\:I6\|I1\|Ai) resistor r=0.04519 c=0 +rf400 (\2\:I6\|I1\|Ai \3\:I6\|I1\|Ai) resistor r=0.7634 c=0 +rf401 (\2\:I6\|I1\|Ai \4\:I6\|I1\|Ai) resistor r=0.2765 c=0 +rf402 (\13\:X1 \14\:X1) resistor r=2.01 c=0 +rf404 (I16\|net013 \2\:I16\|net013) resistor r=0.2434 c=0 +rf405 (\2\:I16\|net013 \3\:I16\|net013) resistor r=0.3205 c=0 +rf406 (\2\:I16\|net013 \4\:I16\|net013) resistor r=0.5422 c=0 +rf407 (\11\:Y3 \15\:Y3) resistor r=0.01 c=0 +rf408 (\5\:I24\|net013 \6\:I24\|net013) resistor r=0.236 c=0 +rf409 (\6\:I24\|net013 I24\|net013) resistor r=0.2322 c=0 +rf410 (\6\:I24\|net013 \7\:I24\|net013) resistor r=0.5701 c=0 +rf411 (\6\:net0115 \7\:net0115) resistor r=0.01 c=0 +rf412 (\11\:Y2 \15\:Y2) resistor r=0.01 c=0 +rf413 (\5\:I23\|net013 \6\:I23\|net013) resistor r=0.236 c=0 +rf414 (\6\:I23\|net013 I23\|net013) resistor r=0.2322 c=0 +rf415 (\6\:I23\|net013 \7\:I23\|net013) resistor r=0.5701 c=0 +rf416 (\11\:net095 \12\:net095) resistor r=0.2066 c=0 +rf417 (\12\:net095 \13\:net095) resistor r=0.6132 c=0 +rf418 (\8\:net0115 \9\:net0115) resistor r=0.002222 c=0 +rf419 (\10\:net0115 \11\:net0115) resistor r=0.002222 c=0 +rf420 (\1\:Z1 \2\:Z1) resistor r=0.4382 c=0 +rf421 (\2\:Z1 \3\:Z1) resistor r=0.1123 c=0 +rf422 (\3\:Z1 \4\:Z1) resistor r=0.1083 c=0 +rf423 (\4\:Z1 \5\:Z1) resistor r=0.629 c=0 +rf424 (\2\:Z1 \6\:Z1) resistor r=0.6387 c=0 +rf425 (\4\:Z1 \7\:Z1) resistor r=0.4386 c=0 +rf426 (\15\:net0115 \20\:net0115) resistor r=2.01 c=0 +rf427 (\12\:net5 \13\:net5) resistor r=0.285 c=0 +rf428 (\12\:net5 \14\:net5) resistor r=0.8307 c=0 +rf429 (\12\:net45 \13\:net45) resistor r=0.285 c=0 +rf430 (\12\:net45 \14\:net45) resistor r=0.8307 c=0 +rf431 (net0127 \2\:net0127) resistor r=2.0111 c=0 +rf432 (\9\:net44 \10\:net44) resistor r=2.0111 c=0 +rf433 (I8\|I1\|Bi \2\:I8\|I1\|Bi) resistor r=0.3619 c=0 +rf434 (\2\:I8\|I1\|Bi \3\:I8\|I1\|Bi) resistor r=0.6109 c=0 +rf435 (\2\:I8\|I1\|Bi \4\:I8\|I1\|Bi) resistor r=0.2422 c=0 +rf436 (\9\:net32 \10\:net32) resistor r=2.0111 c=0 +rf437 (I7\|I1\|Bi \2\:I7\|I1\|Bi) resistor r=0.3619 c=0 +rf438 (\2\:I7\|I1\|Bi \3\:I7\|I1\|Bi) resistor r=0.6109 c=0 +rf439 (\2\:I7\|I1\|Bi \4\:I7\|I1\|Bi) resistor r=0.2422 c=0 +rf440 (\5\:I6\|I1\|Bi \6\:I6\|I1\|Bi) resistor r=0.3619 c=0 +rf441 (\6\:I6\|I1\|Bi I6\|I1\|Bi) resistor r=0.2422 c=0 +rf442 (\6\:I6\|I1\|Bi \7\:I6\|I1\|Bi) resistor r=0.6109 c=0 +rf443 (\5\:I6\|I3\|net013 \6\:I6\|I3\|net013) resistor r=0.4307 c=0 +rf444 (\6\:I6\|I3\|net013 \7\:I6\|I3\|net013) resistor r=0.8338 c=0 +rf445 (\6\:I6\|I3\|net013 \3\:I6\|I3\|net013) resistor r=0.5507 c=0 +rf446 (net075 \2\:net075) resistor r=2.01 c=0 +rf447 (net47 \2\:net47) resistor r=2.01 c=0 +rf448 (\10\:net35 \11\:net35) resistor r=0.8307 c=0 +rf449 (\11\:net35 \12\:net35) resistor r=0.285 c=0 +rf450 (\5\:I8\|I3\|net013 \6\:I8\|I3\|net013) resistor r=0.4307 c=0 +rf451 (\6\:I8\|I3\|net013 I8\|I3\|net013) resistor r=0.5507 c=0 +rf452 (\6\:I8\|I3\|net013 \7\:I8\|I3\|net013) resistor r=0.8338 c=0 +rf453 (\5\:I7\|I3\|net013 \6\:I7\|I3\|net013) resistor r=0.4307 c=0 +rf454 (\6\:I7\|I3\|net013 I7\|I3\|net013) resistor r=0.5507 c=0 +rf455 (\6\:I7\|I3\|net013 \7\:I7\|I3\|net013) resistor r=0.8338 c=0 +rf456 (\3\:net075 \4\:net075) resistor r=0.002222 c=0 +rf457 (\3\:net47 \4\:net47) resistor r=0.002222 c=0 +rf458 (\5\:net075 \6\:net075) resistor r=0.002222 c=0 +rf459 (\5\:net47 \6\:net47) resistor r=0.002222 c=0 +rf460 (\10\:net075 \11\:net075) resistor r=0.2066 c=0 +rf461 (\11\:net075 \12\:net075) resistor r=0.6132 c=0 +rf462 (\10\:net47 \11\:net47) resistor r=0.2066 c=0 +rf463 (\11\:net47 \12\:net47) resistor r=0.6132 c=0 +rf464 (\23\:X1 \21\:X1) resistor r=0.01 c=0 +rf466 (\1\:Z3 \2\:Z3) resistor r=0.629 c=0 +rf467 (\2\:Z3 \3\:Z3) resistor r=0.1083 c=0 +rf468 (\3\:Z3 \4\:Z3) resistor r=0.1123 c=0 +rf469 (\4\:Z3 \5\:Z3) resistor r=0.4382 c=0 +rf470 (\2\:Z3 \6\:Z3) resistor r=0.4386 c=0 +rf471 (\4\:Z3 \7\:Z3) resistor r=0.6387 c=0 +rf472 (\1\:Z2 \2\:Z2) resistor r=0.629 c=0 +rf473 (\2\:Z2 \3\:Z2) resistor r=0.1083 c=0 +rf474 (\3\:Z2 \4\:Z2) resistor r=0.1123 c=0 +rf475 (\4\:Z2 \5\:Z2) resistor r=0.4382 c=0 +rf476 (\2\:Z2 \6\:Z2) resistor r=0.4386 c=0 +rf477 (\4\:Z2 \7\:Z2) resistor r=0.6387 c=0 +rf478 (\17\:net075 \18\:net075) resistor r=0.01 c=0 +rf479 (\17\:net47 \18\:net47) resistor r=0.01 c=0 +rf481 (\6\:X0 \7\:X0) resistor r=2.01 c=0 +rf482 (I14\|net013 \2\:I14\|net013) resistor r=0.2434 c=0 +rf483 (\2\:I14\|net013 \3\:I14\|net013) resistor r=0.3205 c=0 +rf484 (\2\:I14\|net013 \4\:I14\|net013) resistor r=0.5422 c=0 +rf485 (I17\|net013 \2\:I17\|net013) resistor r=0.2434 c=0 +rf486 (\2\:I17\|net013 \3\:I17\|net013) resistor r=0.3205 c=0 +rf487 (\2\:I17\|net013 \4\:I17\|net013) resistor r=0.5422 c=0 +rf488 (\16\:Y3 \17\:Y3) resistor r=2.01 c=0 +rf489 (\16\:Y2 \17\:Y2) resistor r=2.01 c=0 +rf490 (\4\:I8\|I1\|Ai \5\:I8\|I1\|Ai) resistor r=0.2765 c=0 +rf491 (\5\:I8\|I1\|Ai \2\:I8\|I1\|Ai) resistor r=0.04519 c=0 +rf492 (\5\:I8\|I1\|Ai \6\:I8\|I1\|Ai) resistor r=0.7634 c=0 +rf493 (\4\:I7\|I1\|Ai \5\:I7\|I1\|Ai) resistor r=0.2765 c=0 +rf494 (\5\:I7\|I1\|Ai \2\:I7\|I1\|Ai) resistor r=0.04519 c=0 +rf495 (\5\:I7\|I1\|Ai \6\:I7\|I1\|Ai) resistor r=0.7634 c=0 +rf496 (\12\:X0 \20\:X0) resistor r=0.01 c=0 +rf497 (\16\:X0 \21\:X0) resistor r=0.01 c=0 +rf498 (\11\:net0127 \12\:net0127) resistor r=0.2066 c=0 +rf499 (\12\:net0127 \13\:net0127) resistor r=0.6132 c=0 +rf500 (\21\:net0115 \22\:net0115) resistor r=0.6132 c=0 +rf501 (\22\:net0115 \23\:net0115) resistor r=0.2066 c=0 +rf502 (\5\:I25\|net013 \6\:I25\|net013) resistor r=0.236 c=0 +rf503 (\6\:I25\|net013 I25\|net013) resistor r=0.2322 c=0 +rf504 (\6\:I25\|net013 \7\:I25\|net013) resistor r=0.5701 c=0 +rf505 (\5\:I22\|net013 \6\:I22\|net013) resistor r=0.236 c=0 +rf506 (\6\:I22\|net013 I22\|net013) resistor r=0.2322 c=0 +rf507 (\6\:I22\|net013 \7\:I22\|net013) resistor r=0.5701 c=0 +rf508 (\19\:net075 \23\:net075) resistor r=0.01 c=0 +rf509 (\19\:net47 \23\:net47) resistor r=0.01 c=0 +rf510 (\1\:gnd! \2\:gnd!) resistor r=0.5373 c=0 +rf511 (\2\:gnd! \3\:gnd!) resistor r=0.06105 c=0 +rf512 (\3\:gnd! \4\:gnd!) resistor r=0.089 c=0 +rf513 (\4\:gnd! \5\:gnd!) resistor r=0.1325 c=0 +rf514 (\5\:gnd! \6\:gnd!) resistor r=0.0567 c=0 +rf515 (\6\:gnd! \7\:gnd!) resistor r=0.05137 c=0 +rf516 (\7\:gnd! \8\:gnd!) resistor r=0.04013 c=0 +rf517 (\8\:gnd! \9\:gnd!) resistor r=0.1485 c=0 +rf518 (\9\:gnd! \10\:gnd!) resistor r=0.07027 c=0 +rf519 (\10\:gnd! \11\:gnd!) resistor r=0.07573 c=0 +rf520 (\11\:gnd! \12\:gnd!) resistor r=0.1984 c=0 +rf521 (\12\:gnd! \13\:gnd!) resistor r=0.1201 c=0 +rf522 (\13\:gnd! \14\:gnd!) resistor r=0.02927 c=0 +rf523 (\14\:gnd! \15\:gnd!) resistor r=0.03312 c=0 +rf524 (\15\:gnd! \16\:gnd!) resistor r=0.09389 c=0 +rf525 (\16\:gnd! \17\:gnd!) resistor r=0.07629 c=0 +rf526 (\17\:gnd! \18\:gnd!) resistor r=0.05008 c=0 +rf527 (\18\:gnd! \19\:gnd!) resistor r=0.02223 c=0 +rf528 (\19\:gnd! \20\:gnd!) resistor r=0.1485 c=0 +rf529 (\2\:gnd! \21\:gnd!) resistor r=0.4051 c=0 +rf530 (\2\:gnd! \22\:gnd!) resistor r=0.4778 c=0 +rf531 (\3\:gnd! \23\:gnd!) resistor r=0.3083 c=0 +rf532 (\5\:gnd! \24\:gnd!) resistor r=0.4782 c=0 +rf533 (\5\:gnd! \25\:gnd!) resistor r=0.4924 c=0 +rf534 (\6\:gnd! \26\:gnd!) resistor r=0.3585 c=0 +rf535 (\7\:gnd! \27\:gnd!) resistor r=0.3845 c=0 +rf536 (\10\:gnd! \28\:gnd!) resistor r=0.3925 c=0 +rf537 (\10\:gnd! \29\:gnd!) resistor r=0.4802 c=0 +rf538 (\11\:gnd! \30\:gnd!) resistor r=0.44 c=0 +rf539 (\12\:gnd! \31\:gnd!) resistor r=0.3843 c=0 +rf540 (\12\:gnd! \32\:gnd!) resistor r=0.4444 c=0 +rf541 (\13\:gnd! \33\:gnd!) resistor r=0.3833 c=0 +rf542 (\15\:gnd! \34\:gnd!) resistor r=0.3817 c=0 +rf543 (\15\:gnd! \35\:gnd!) resistor r=0.4721 c=0 +rf544 (\16\:gnd! \36\:gnd!) resistor r=0.4967 c=0 +rf545 (\17\:gnd! \37\:gnd!) resistor r=0.3196 c=0 +rf546 (\18\:gnd! \38\:gnd!) resistor r=0.3196 c=0 +rf547 (\20\:gnd! \39\:gnd!) resistor r=0.4346 c=0 +rf548 (\20\:gnd! \40\:gnd!) resistor r=0.486 c=0 +rf549 (\20\:gnd! \41\:gnd!) resistor r=0.1486 c=0 +rf550 (\41\:gnd! \42\:gnd!) resistor r=0.03801 c=0 +rf551 (\42\:gnd! \43\:gnd!) resistor r=0.07419 c=0 +rf552 (\43\:gnd! \44\:gnd!) resistor r=0.3142 c=0 +rf553 (\42\:gnd! \45\:gnd!) resistor r=0.3864 c=0 +rf554 (\43\:gnd! \46\:gnd!) resistor r=0.0911 c=0 +rf555 (\46\:gnd! \47\:gnd!) resistor r=0.06504 c=0 +rf556 (\47\:gnd! \48\:gnd!) resistor r=0.3175 c=0 +rf557 (\47\:gnd! \49\:gnd!) resistor r=0.04775 c=0 +rf558 (\49\:gnd! \50\:gnd!) resistor r=0.4116 c=0 +rf559 (\49\:gnd! \51\:gnd!) resistor r=0.03353 c=0 +rf560 (\51\:gnd! \52\:gnd!) resistor r=0.07914 c=0 +rf561 (\52\:gnd! \53\:gnd!) resistor r=0.05225 c=0 +rf562 (\53\:gnd! \54\:gnd!) resistor r=0.4218 c=0 +rf563 (\49\:gnd! \55\:gnd!) resistor r=0.4813 c=0 +rf564 (\52\:gnd! \56\:gnd!) resistor r=0.3864 c=0 +rf565 (\53\:gnd! \57\:gnd!) resistor r=0.1034 c=0 +rf566 (\57\:gnd! \58\:gnd!) resistor r=0.04537 c=0 +rf567 (\58\:gnd! \59\:gnd!) resistor r=0.05274 c=0 +rf568 (\59\:gnd! \60\:gnd!) resistor r=0.3142 c=0 +rf569 (\53\:gnd! \61\:gnd!) resistor r=0.4674 c=0 +rf570 (\57\:gnd! \62\:gnd!) resistor r=0.3864 c=0 +rf571 (\59\:gnd! \63\:gnd!) resistor r=0.09297 c=0 +rf572 (\63\:gnd! \64\:gnd!) resistor r=0.03064 c=0 +rf573 (\64\:gnd! \65\:gnd!) resistor r=0.3023 c=0 +rf574 (\64\:gnd! \66\:gnd!) resistor r=0.06745 c=0 +rf575 (\66\:gnd! \67\:gnd!) resistor r=0.3835 c=0 +rf576 (\66\:gnd! \68\:gnd!) resistor r=0.04394 c=0 +rf577 (\68\:gnd! \69\:gnd!) resistor r=0.1358 c=0 +rf578 (\69\:gnd! \70\:gnd!) resistor r=0.04148 c=0 +rf579 (\70\:gnd! \71\:gnd!) resistor r=0.4407 c=0 +rf580 (\66\:gnd! \72\:gnd!) resistor r=0.4754 c=0 +rf581 (\69\:gnd! \73\:gnd!) resistor r=0.3833 c=0 +rf582 (\70\:gnd! \74\:gnd!) resistor r=0.1489 c=0 +rf583 (\74\:gnd! \75\:gnd!) resistor r=0.4043 c=0 +rf584 (\74\:gnd! \76\:gnd!) resistor r=0.07477 c=0 +rf585 (\76\:gnd! \77\:gnd!) resistor r=0.3848 c=0 +rf586 (\76\:gnd! \78\:gnd!) resistor r=0.1353 c=0 +rf587 (\78\:gnd! \79\:gnd!) resistor r=0.3869 c=0 +rf588 (\76\:gnd! \80\:gnd!) resistor r=0.47 c=0 +rf589 (\78\:gnd! \81\:gnd!) resistor r=0.0387 c=0 +rf590 (\81\:gnd! \82\:gnd!) resistor r=0.1067 c=0 +rf591 (\78\:gnd! \83\:gnd!) resistor r=0.4452 c=0 +rf592 (\81\:gnd! \84\:gnd!) resistor r=0.3793 c=0 +rf593 (\82\:gnd! \85\:gnd!) resistor r=0.0706 c=0 +rf594 (\85\:gnd! \86\:gnd!) resistor r=0.3122 c=0 +rf595 (\82\:gnd! \87\:gnd!) resistor r=0.4967 c=0 +rf596 (\85\:gnd! \88\:gnd!) resistor r=0.06608 c=0 +rf597 (\88\:gnd! \89\:gnd!) resistor r=0.04684 c=0 +rf598 (\89\:gnd! \90\:gnd!) resistor r=0.306 c=0 +rf599 (\89\:gnd! \91\:gnd!) resistor r=0.09403 c=0 +rf600 (\91\:gnd! \92\:gnd!) resistor r=0.3596 c=0 +rf601 (\91\:gnd! \93\:gnd!) resistor r=0.3451 c=0 +rf602 (\93\:gnd! \94\:gnd!) resistor r=4.7066 c=0 +rf603 (\94\:gnd! \95\:gnd!) resistor r=0.476 c=0 +rf604 (\91\:gnd! \96\:gnd!) resistor r=0.442 c=0 +rf605 (\93\:gnd! \97\:gnd!) resistor r=4.2632 c=0 +rf606 (\97\:gnd! \98\:gnd!) resistor r=4.2744 c=0 +rf607 (\98\:gnd! 0) resistor r=0.4005 c=0 +rf608 (\94\:gnd! \99\:gnd!) resistor r=0.1317 c=0 +rf609 (\99\:gnd! \100\:gnd!) resistor r=0.1396 c=0 +rf610 (\100\:gnd! \101\:gnd!) resistor r=0.52 c=0 +rf611 (\97\:gnd! \102\:gnd!) resistor r=0.3328 c=0 +rf612 (\102\:gnd! \103\:gnd!) resistor r=0.05392 c=0 +rf613 (\103\:gnd! \104\:gnd!) resistor r=0.3949 c=0 +rf614 (\98\:gnd! \105\:gnd!) resistor r=0.359 c=0 +rf615 (\105\:gnd! \106\:gnd!) resistor r=0.09621 c=0 +rf616 (\106\:gnd! \107\:gnd!) resistor r=0.2996 c=0 +rf617 (\100\:gnd! \108\:gnd!) resistor r=0.1085 c=0 +rf618 (\108\:gnd! \109\:gnd!) resistor r=0.3877 c=0 +rf619 (\103\:gnd! \110\:gnd!) resistor r=0.3965 c=0 +rf620 (\103\:gnd! \111\:gnd!) resistor r=0.09221 c=0 +rf621 (\111\:gnd! \112\:gnd!) resistor r=0.3649 c=0 +rf622 (\106\:gnd! \113\:gnd!) resistor r=0.07337 c=0 +rf623 (\113\:gnd! \114\:gnd!) resistor r=0.3083 c=0 +rf624 (\108\:gnd! \115\:gnd!) resistor r=0.03889 c=0 +rf625 (\115\:gnd! \116\:gnd!) resistor r=0.4877 c=0 +rf626 (\111\:gnd! \117\:gnd!) resistor r=0.3954 c=0 +rf627 (\111\:gnd! \118\:gnd!) resistor r=0.09227 c=0 +rf628 (\118\:gnd! \119\:gnd!) resistor r=0.3971 c=0 +rf629 (\113\:gnd! \120\:gnd!) resistor r=0.03456 c=0 +rf630 (\120\:gnd! \121\:gnd!) resistor r=0.1383 c=0 +rf631 (\121\:gnd! \122\:gnd!) resistor r=0.4467 c=0 +rf632 (\115\:gnd! \123\:gnd!) resistor r=0.1292 c=0 +rf633 (\123\:gnd! \124\:gnd!) resistor r=0.3918 c=0 +rf634 (\118\:gnd! \125\:gnd!) resistor r=0.473 c=0 +rf635 (\118\:gnd! \126\:gnd!) resistor r=0.06553 c=0 +rf636 (\126\:gnd! \127\:gnd!) resistor r=0.046 c=0 +rf637 (\127\:gnd! \128\:gnd!) resistor r=0.3896 c=0 +rf638 (\121\:gnd! \129\:gnd!) resistor r=0.04511 c=0 +rf639 (\129\:gnd! \130\:gnd!) resistor r=0.358 c=0 +rf640 (\123\:gnd! \131\:gnd!) resistor r=0.08824 c=0 +rf641 (\131\:gnd! \132\:gnd!) resistor r=0.1508 c=0 +rf642 (\132\:gnd! \133\:gnd!) resistor r=0.04236 c=0 +rf643 (\133\:gnd! \134\:gnd!) resistor r=0.3918 c=0 +rf644 (\127\:gnd! \135\:gnd!) resistor r=0.1014 c=0 +rf645 (\135\:gnd! \136\:gnd!) resistor r=0.3965 c=0 +rf646 (\129\:gnd! \137\:gnd!) resistor r=0.09948 c=0 +rf647 (\137\:gnd! \138\:gnd!) resistor r=0.2186 c=0 +rf648 (\138\:gnd! \139\:gnd!) resistor r=0.3811 c=0 +rf649 (\133\:gnd! \140\:gnd!) resistor r=0.1372 c=0 +rf650 (\135\:gnd! \141\:gnd!) resistor r=0.15 c=0 +rf651 (\141\:gnd! \142\:gnd!) resistor r=0.3196 c=0 +rf652 (\138\:gnd! \143\:gnd!) resistor r=0.07421 c=0 +rf653 (\143\:gnd! \144\:gnd!) resistor r=0.3105 c=0 +rf654 (\140\:gnd! \145\:gnd!) resistor r=0.0255 c=0 +rf655 (\145\:gnd! \146\:gnd!) resistor r=0.3873 c=0 +rf656 (\141\:gnd! \147\:gnd!) resistor r=0.06745 c=0 +rf657 (\147\:gnd! \148\:gnd!) resistor r=0.3617 c=0 +rf658 (\143\:gnd! \149\:gnd!) resistor r=0.07653 c=0 +rf659 (\149\:gnd! \150\:gnd!) resistor r=0.1347 c=0 +rf660 (\150\:gnd! \151\:gnd!) resistor r=0.3038 c=0 +rf661 (\145\:gnd! \152\:gnd!) resistor r=0.1216 c=0 +rf662 (\152\:gnd! \153\:gnd!) resistor r=0.148 c=0 +rf663 (\147\:gnd! \154\:gnd!) resistor r=0.4707 c=0 +rf664 (\147\:gnd! \155\:gnd!) resistor r=0.09352 c=0 +rf665 (\155\:gnd! \156\:gnd!) resistor r=0.3896 c=0 +rf666 (\150\:gnd! \157\:gnd!) resistor r=0.0463 c=0 +rf667 (\157\:gnd! \158\:gnd!) resistor r=0.02722 c=0 +rf668 (\158\:gnd! \159\:gnd!) resistor r=0.3 c=0 +rf669 (\153\:gnd! \160\:gnd!) resistor r=0.02188 c=0 +rf670 (\160\:gnd! \161\:gnd!) resistor r=0.3873 c=0 +rf671 (\155\:gnd! \162\:gnd!) resistor r=0.05615 c=0 +rf672 (\162\:gnd! \163\:gnd!) resistor r=0.3941 c=0 +rf673 (\158\:gnd! \164\:gnd!) resistor r=0.1173 c=0 +rf674 (\164\:gnd! \165\:gnd!) resistor r=0.4044 c=0 +rf675 (\160\:gnd! \166\:gnd!) resistor r=0.1038 c=0 +rf676 (\166\:gnd! \167\:gnd!) resistor r=0.3833 c=0 +rf677 (\162\:gnd! \168\:gnd!) resistor r=0.1077 c=0 +rf678 (\168\:gnd! \169\:gnd!) resistor r=0.3874 c=0 +rf679 (\164\:gnd! \170\:gnd!) resistor r=0.1447 c=0 +rf680 (\170\:gnd! \171\:gnd!) resistor r=0.05704 c=0 +rf681 (\171\:gnd! \172\:gnd!) resistor r=0.3215 c=0 +rf682 (\166\:gnd! \173\:gnd!) resistor r=0.02269 c=0 +rf683 (\168\:gnd! \174\:gnd!) resistor r=0.0715 c=0 +rf684 (\174\:gnd! \175\:gnd!) resistor r=0.05637 c=0 +rf685 (\175\:gnd! \176\:gnd!) resistor r=0.3019 c=0 +rf686 (\171\:gnd! \177\:gnd!) resistor r=0.08887 c=0 +rf687 (\177\:gnd! \178\:gnd!) resistor r=0.06637 c=0 +rf688 (\178\:gnd! \179\:gnd!) resistor r=0.3215 c=0 +rf689 (\173\:gnd! \180\:gnd!) resistor r=0.02879 c=0 +rf690 (\180\:gnd! \181\:gnd!) resistor r=0.3873 c=0 +rf691 (\175\:gnd! \182\:gnd!) resistor r=0.09058 c=0 +rf692 (\182\:gnd! \183\:gnd!) resistor r=0.3708 c=0 +rf693 (\178\:gnd! \184\:gnd!) resistor r=0.06251 c=0 +rf694 (\184\:gnd! \185\:gnd!) resistor r=0.3843 c=0 +rf695 (\180\:gnd! \186\:gnd!) resistor r=0.1034 c=0 +rf696 (\182\:gnd! \187\:gnd!) resistor r=0.07183 c=0 +rf697 (\187\:gnd! \188\:gnd!) resistor r=0.3874 c=0 +rf698 (\184\:gnd! \189\:gnd!) resistor r=0.1469 c=0 +rf699 (\189\:gnd! \190\:gnd!) resistor r=0.4044 c=0 +rf700 (\186\:gnd! \191\:gnd!) resistor r=0.4477 c=0 +rf701 (\186\:gnd! \192\:gnd!) resistor r=0.1503 c=0 +rf702 (\187\:gnd! \193\:gnd!) resistor r=0.04481 c=0 +rf703 (\193\:gnd! \194\:gnd!) resistor r=0.3163 c=0 +rf704 (\189\:gnd! \195\:gnd!) resistor r=0.2039 c=0 +rf705 (\195\:gnd! \196\:gnd!) resistor r=0.4022 c=0 +rf706 (\192\:gnd! \197\:gnd!) resistor r=0.1433 c=0 +rf707 (\197\:gnd! \198\:gnd!) resistor r=0.3873 c=0 +rf708 (\193\:gnd! \199\:gnd!) resistor r=0.02922 c=0 +rf709 (\199\:gnd! \200\:gnd!) resistor r=0.02857 c=0 +rf710 (\200\:gnd! \201\:gnd!) resistor r=0.3834 c=0 +rf711 (\195\:gnd! \202\:gnd!) resistor r=0.1456 c=0 +rf712 (\202\:gnd! \203\:gnd!) resistor r=0.3767 c=0 +rf713 (\197\:gnd! \204\:gnd!) resistor r=0.06184 c=0 +rf714 (\204\:gnd! \205\:gnd!) resistor r=0.109 c=0 +rf715 (\205\:gnd! \206\:gnd!) resistor r=0.3873 c=0 +rf716 (\200\:gnd! \207\:gnd!) resistor r=0.05138 c=0 +rf717 (\207\:gnd! \208\:gnd!) resistor r=0.3874 c=0 +rf718 (\202\:gnd! \209\:gnd!) resistor r=0.06647 c=0 +rf719 (\209\:gnd! \210\:gnd!) resistor r=0.3213 c=0 +rf720 (\205\:gnd! \211\:gnd!) resistor r=0.03833 c=0 +rf721 (\211\:gnd! \212\:gnd!) resistor r=0.148 c=0 +rf722 (\207\:gnd! \213\:gnd!) resistor r=0.06821 c=0 +rf723 (\213\:gnd! \214\:gnd!) resistor r=0.03653 c=0 +rf724 (\214\:gnd! \215\:gnd!) resistor r=0.3929 c=0 +rf725 (\209\:gnd! \216\:gnd!) resistor r=0.07812 c=0 +rf726 (\216\:gnd! \217\:gnd!) resistor r=0.07812 c=0 +rf727 (\217\:gnd! \218\:gnd!) resistor r=0.3213 c=0 +rf728 (\212\:gnd! \219\:gnd!) resistor r=0.09425 c=0 +rf729 (\219\:gnd! \220\:gnd!) resistor r=0.3873 c=0 +rf730 (\214\:gnd! \221\:gnd!) resistor r=0.4741 c=0 +rf731 (\214\:gnd! \222\:gnd!) resistor r=0.09179 c=0 +rf732 (\222\:gnd! \223\:gnd!) resistor r=0.0567 c=0 +rf733 (\223\:gnd! \224\:gnd!) resistor r=0.3197 c=0 +rf734 (\217\:gnd! \225\:gnd!) resistor r=0.06873 c=0 +rf735 (\225\:gnd! \226\:gnd!) resistor r=0.1307 c=0 +rf736 (\226\:gnd! \227\:gnd!) resistor r=0.4022 c=0 +rf737 (\219\:gnd! \228\:gnd!) resistor r=0.0551 c=0 +rf738 (\223\:gnd! \229\:gnd!) resistor r=0.04991 c=0 +rf739 (\229\:gnd! \230\:gnd!) resistor r=0.3197 c=0 +rf740 (\226\:gnd! \231\:gnd!) resistor r=0.1662 c=0 +rf741 (\231\:gnd! \232\:gnd!) resistor r=0.3027 c=0 +rf742 (\228\:gnd! \233\:gnd!) resistor r=0.06004 c=0 +rf743 (\233\:gnd! \234\:gnd!) resistor r=0.3873 c=0 +rf744 (\229\:gnd! \235\:gnd!) resistor r=0.04157 c=0 +rf745 (\235\:gnd! \236\:gnd!) resistor r=0.04519 c=0 +rf746 (\236\:gnd! \237\:gnd!) resistor r=0.3874 c=0 +rf747 (\231\:gnd! \238\:gnd!) resistor r=0.05028 c=0 +rf748 (\238\:gnd! \239\:gnd!) resistor r=0.02337 c=0 +rf749 (\239\:gnd! \240\:gnd!) resistor r=0.3093 c=0 +rf750 (\233\:gnd! \241\:gnd!) resistor r=0.07188 c=0 +rf751 (\236\:gnd! \242\:gnd!) resistor r=0.06896 c=0 +rf752 (\242\:gnd! \243\:gnd!) resistor r=0.3173 c=0 +rf753 (\239\:gnd! \244\:gnd!) resistor r=0.1061 c=0 +rf754 (\244\:gnd! \245\:gnd!) resistor r=0.148 c=0 +rf755 (\245\:gnd! \246\:gnd!) resistor r=0.3515 c=0 +rf756 (\241\:gnd! \247\:gnd!) resistor r=0.442 c=0 +rf757 (\241\:gnd! \248\:gnd!) resistor r=0.08461 c=0 +rf758 (\248\:gnd! \249\:gnd!) resistor r=0.3873 c=0 +rf759 (\242\:gnd! \250\:gnd!) resistor r=0.04495 c=0 +rf760 (\250\:gnd! \251\:gnd!) resistor r=0.3896 c=0 +rf761 (\245\:gnd! \252\:gnd!) resistor r=0.0544 c=0 +rf762 (\252\:gnd! \253\:gnd!) resistor r=0.3085 c=0 +rf763 (\248\:gnd! \254\:gnd!) resistor r=0.06497 c=0 +rf764 (\254\:gnd! \255\:gnd!) resistor r=0.1977 c=0 +rf765 (\250\:gnd! \256\:gnd!) resistor r=0.04402 c=0 +rf766 (\256\:gnd! \257\:gnd!) resistor r=0.1485 c=0 +rf767 (\257\:gnd! \258\:gnd!) resistor r=0.07299 c=0 +rf768 (\258\:gnd! \259\:gnd!) resistor r=0.3788 c=0 +rf769 (\252\:gnd! \260\:gnd!) resistor r=0.09236 c=0 +rf770 (\260\:gnd! \261\:gnd!) resistor r=0.1489 c=0 +rf771 (\261\:gnd! \262\:gnd!) resistor r=0.4122 c=0 +rf772 (\255\:gnd! \263\:gnd!) resistor r=0.02879 c=0 +rf773 (\263\:gnd! \264\:gnd!) resistor r=0.3873 c=0 +rf774 (\258\:gnd! \265\:gnd!) resistor r=0.4741 c=0 +rf775 (\258\:gnd! \266\:gnd!) resistor r=0.06936 c=0 +rf776 (\266\:gnd! \267\:gnd!) resistor r=0.06287 c=0 +rf777 (\267\:gnd! \268\:gnd!) resistor r=0.3949 c=0 +rf778 (\261\:gnd! \269\:gnd!) resistor r=0.03693 c=0 +rf779 (\269\:gnd! \270\:gnd!) resistor r=0.3611 c=0 +rf780 (\263\:gnd! \271\:gnd!) resistor r=0.1186 c=0 +rf781 (\271\:gnd! \272\:gnd!) resistor r=0.1485 c=0 +rf782 (\272\:gnd! \273\:gnd!) resistor r=0.03889 c=0 +rf783 (\273\:gnd! \274\:gnd!) resistor r=0.3844 c=0 +rf784 (\267\:gnd! \275\:gnd!) resistor r=0.4764 c=0 +rf785 (\267\:gnd! \276\:gnd!) resistor r=0.04763 c=0 +rf786 (\276\:gnd! \277\:gnd!) resistor r=0.3962 c=0 +rf787 (\269\:gnd! \278\:gnd!) resistor r=0.09408 c=0 +rf788 (\278\:gnd! \279\:gnd!) resistor r=0.1513 c=0 +rf789 (\279\:gnd! \280\:gnd!) resistor r=0.3627 c=0 +rf790 (\273\:gnd! \281\:gnd!) resistor r=0.1108 c=0 +rf791 (\281\:gnd! \282\:gnd!) resistor r=0.5167 c=0 +rf792 (\276\:gnd! \283\:gnd!) resistor r=0.4722 c=0 +rf793 (\276\:gnd! \284\:gnd!) resistor r=0.03195 c=0 +rf794 (\284\:gnd! \285\:gnd!) resistor r=0.06382 c=0 +rf795 (\285\:gnd! \286\:gnd!) resistor r=0.3896 c=0 +rf796 (\279\:gnd! \287\:gnd!) resistor r=0.3647 c=0 +rf797 (\281\:gnd! \288\:gnd!) resistor r=0.1333 c=0 +rf798 (\288\:gnd! \289\:gnd!) resistor r=0.1508 c=0 +rf799 (\289\:gnd! \290\:gnd!) resistor r=0.5167 c=0 +rf800 (\285\:gnd! \291\:gnd!) resistor r=0.06844 c=0 +rf801 (\291\:gnd! \292\:gnd!) resistor r=0.4133 c=0 +rf802 (\289\:gnd! \293\:gnd!) resistor r=0.521 c=0 +rf803 (\291\:gnd! \294\:gnd!) resistor r=0.1508 c=0 +rf804 (\294\:gnd! \295\:gnd!) resistor r=0.06482 c=0 +rf805 (\295\:gnd! \296\:gnd!) resistor r=0.3936 c=0 +rf806 (\295\:gnd! \297\:gnd!) resistor r=0.4764 c=0 +rf807 (\295\:gnd! \298\:gnd!) resistor r=0.1289 c=0 +rf808 (\298\:gnd! \299\:gnd!) resistor r=0.364 c=0 +rf809 (\298\:gnd! \300\:gnd!) resistor r=0.4713 c=0 +rf810 (\298\:gnd! \301\:gnd!) resistor r=0.09652 c=0 +rf811 (\301\:gnd! \302\:gnd!) resistor r=0.302 c=0 +rf812 (\301\:gnd! \303\:gnd!) resistor r=0.04996 c=0 +rf813 (\303\:gnd! \304\:gnd!) resistor r=0.5113 c=0 +rf814 (\303\:gnd! \305\:gnd!) resistor r=0.1477 c=0 +rf815 (\305\:gnd! \306\:gnd!) resistor r=0.0937 c=0 +rf816 (\306\:gnd! \307\:gnd!) resistor r=0.3575 c=0 +rf817 (\306\:gnd! \308\:gnd!) resistor r=0.0552 c=0 +rf818 (\308\:gnd! \309\:gnd!) resistor r=0.4108 c=0 +rf819 (\308\:gnd! \310\:gnd!) resistor r=0.4821 c=0 +rf820 (\308\:gnd! \311\:gnd!) resistor r=0.09077 c=0 +rf821 (\311\:gnd! \312\:gnd!) resistor r=0.3857 c=0 +rf822 (\311\:gnd! \313\:gnd!) resistor r=0.07145 c=0 +rf823 (\313\:gnd! \314\:gnd!) resistor r=0.05835 c=0 +rf824 (\314\:gnd! \315\:gnd!) resistor r=0.3063 c=0 +rf825 (\314\:gnd! \316\:gnd!) resistor r=0.09091 c=0 +rf826 (\316\:gnd! \317\:gnd!) resistor r=0.3306 c=0 +rf827 (\316\:gnd! \318\:gnd!) resistor r=0.3711 c=0 +rf828 (\316\:gnd! \319\:gnd!) resistor r=0.3343 c=0 +rf829 (Y1 \21\:Y1) resistor r=0.2212 c=0 +rf830 (\21\:Y1 \18\:Y1) resistor r=3.8017 c=0 +rf831 (\18\:Y1 \12\:Y1) resistor r=10.0519 c=0 +rf832 (\12\:Y1 \5\:Y1) resistor r=4.0448 c=0 +rf833 (vdd! \1\:vdd!) resistor r=1.9259 c=0 +rf834 (\1\:vdd! \2\:vdd!) resistor r=4.4079 c=0 +rf835 (\2\:vdd! \3\:vdd!) resistor r=4.3331 c=0 +rf836 (\3\:vdd! \4\:vdd!) resistor r=0.1142 c=0 +rf837 (\4\:vdd! \5\:vdd!) resistor r=0.07026 c=0 +rf838 (\5\:vdd! \6\:vdd!) resistor r=0.1185 c=0 +rf839 (\6\:vdd! \7\:vdd!) resistor r=0.1058 c=0 +rf840 (\7\:vdd! \8\:vdd!) resistor r=0.05382 c=0 +rf841 (\8\:vdd! \9\:vdd!) resistor r=0.05336 c=0 +rf842 (\9\:vdd! \10\:vdd!) resistor r=0.1554 c=0 +rf843 (\10\:vdd! \11\:vdd!) resistor r=0.1068 c=0 +rf844 (\11\:vdd! \12\:vdd!) resistor r=0.0441 c=0 +rf845 (\12\:vdd! \13\:vdd!) resistor r=0.02879 c=0 +rf846 (\13\:vdd! \14\:vdd!) resistor r=0.1886 c=0 +rf847 (\14\:vdd! \15\:vdd!) resistor r=0.07569 c=0 +rf848 (\15\:vdd! \16\:vdd!) resistor r=0.03265 c=0 +rf849 (\16\:vdd! \17\:vdd!) resistor r=0.07166 c=0 +rf850 (\17\:vdd! \18\:vdd!) resistor r=0.02575 c=0 +rf851 (\18\:vdd! \19\:vdd!) resistor r=0.02916 c=0 +rf852 (\19\:vdd! \20\:vdd!) resistor r=0.0265 c=0 +rf853 (\20\:vdd! \21\:vdd!) resistor r=0.1023 c=0 +rf854 (\21\:vdd! \22\:vdd!) resistor r=0.05449 c=0 +rf855 (\22\:vdd! \23\:vdd!) resistor r=0.1069 c=0 +rf856 (\23\:vdd! \24\:vdd!) resistor r=0.05069 c=0 +rf857 (\24\:vdd! \25\:vdd!) resistor r=0.05136 c=0 +rf858 (\25\:vdd! \26\:vdd!) resistor r=0.1725 c=0 +rf859 (\26\:vdd! \27\:vdd!) resistor r=0.05118 c=0 +rf860 (\27\:vdd! \28\:vdd!) resistor r=0.0506 c=0 +rf861 (\28\:vdd! \29\:vdd!) resistor r=0.1064 c=0 +rf862 (\29\:vdd! \30\:vdd!) resistor r=0.05445 c=0 +rf863 (\30\:vdd! \31\:vdd!) resistor r=0.1029 c=0 +rf864 (\31\:vdd! \32\:vdd!) resistor r=0.03453 c=0 +rf865 (\32\:vdd! \33\:vdd!) resistor r=0.03083 c=0 +rf866 (\33\:vdd! \34\:vdd!) resistor r=0.0257 c=0 +rf867 (\34\:vdd! \35\:vdd!) resistor r=0.07181 c=0 +rf868 (\35\:vdd! \36\:vdd!) resistor r=0.03262 c=0 +rf869 (\36\:vdd! \37\:vdd!) resistor r=0.07526 c=0 +rf870 (\37\:vdd! \38\:vdd!) resistor r=0.1245 c=0 +rf871 (\38\:vdd! \39\:vdd!) resistor r=0.06644 c=0 +rf872 (\39\:vdd! \40\:vdd!) resistor r=0.02911 c=0 +rf873 (\40\:vdd! \41\:vdd!) resistor r=0.08239 c=0 +rf874 (\41\:vdd! \42\:vdd!) resistor r=0.07195 c=0 +rf875 (\42\:vdd! \43\:vdd!) resistor r=0.05037 c=0 +rf876 (\43\:vdd! \44\:vdd!) resistor r=0.04978 c=0 +rf877 (\44\:vdd! \45\:vdd!) resistor r=0.1047 c=0 +rf878 (\45\:vdd! \46\:vdd!) resistor r=0.05363 c=0 +rf879 (\46\:vdd! \47\:vdd!) resistor r=0.1009 c=0 +rf880 (\47\:vdd! \48\:vdd!) resistor r=0.02613 c=0 +rf881 (\48\:vdd! \49\:vdd!) resistor r=0.02876 c=0 +rf882 (\49\:vdd! \50\:vdd!) resistor r=0.02535 c=0 +rf883 (\50\:vdd! \51\:vdd!) resistor r=0.07067 c=0 +rf884 (\51\:vdd! \52\:vdd!) resistor r=0.03216 c=0 +rf885 (\52\:vdd! \53\:vdd!) resistor r=0.07448 c=0 +rf886 (\53\:vdd! \54\:vdd!) resistor r=0.1082 c=0 +rf887 (\54\:vdd! \55\:vdd!) resistor r=0.07267 c=0 +rf888 (\55\:vdd! \56\:vdd!) resistor r=0.0317 c=0 +rf889 (\56\:vdd! \57\:vdd!) resistor r=0.06006 c=0 +rf890 (\57\:vdd! \58\:vdd!) resistor r=0.429 c=0 +rf891 (\1\:vdd! \59\:vdd!) resistor r=0.2893 c=0 +rf892 (\59\:vdd! \60\:vdd!) resistor r=0.3835 c=0 +rf893 (\2\:vdd! \61\:vdd!) resistor r=0.08985 c=0 +rf894 (\61\:vdd! \62\:vdd!) resistor r=0.5222 c=0 +rf895 (\3\:vdd! \63\:vdd!) resistor r=0.7491 c=0 +rf896 (\3\:vdd! \64\:vdd!) resistor r=0.7418 c=0 +rf897 (\4\:vdd! \65\:vdd!) resistor r=0.5159 c=0 +rf898 (\4\:vdd! \66\:vdd!) resistor r=0.5159 c=0 +rf899 (\5\:vdd! \67\:vdd!) resistor r=0.4015 c=0 +rf900 (\6\:vdd! \68\:vdd!) resistor r=0.3716 c=0 +rf901 (\7\:vdd! \69\:vdd!) resistor r=0.4979 c=0 +rf902 (\7\:vdd! \70\:vdd!) resistor r=0.468 c=0 +rf903 (\8\:vdd! \71\:vdd!) resistor r=0.3726 c=0 +rf904 (\9\:vdd! \72\:vdd!) resistor r=0.3984 c=0 +rf905 (\10\:vdd! \73\:vdd!) resistor r=0.4004 c=0 +rf906 (\11\:vdd! \74\:vdd!) resistor r=0.3994 c=0 +rf907 (\12\:vdd! \75\:vdd!) resistor r=0.3996 c=0 +rf908 (\13\:vdd! \76\:vdd!) resistor r=0.3997 c=0 +rf909 (\14\:vdd! \77\:vdd!) resistor r=0.3775 c=0 +rf910 (\15\:vdd! \78\:vdd!) resistor r=0.4015 c=0 +rf911 (\16\:vdd! \79\:vdd!) resistor r=0.522 c=0 +rf912 (\17\:vdd! \80\:vdd!) resistor r=0.3972 c=0 +rf913 (\18\:vdd! \81\:vdd!) resistor r=0.3878 c=0 +rf914 (\19\:vdd! \82\:vdd!) resistor r=0.4068 c=0 +rf915 (\20\:vdd! \83\:vdd!) resistor r=0.3805 c=0 +rf916 (\21\:vdd! \84\:vdd!) resistor r=0.521 c=0 +rf917 (\21\:vdd! \85\:vdd!) resistor r=0.5021 c=0 +rf918 (\22\:vdd! \86\:vdd!) resistor r=0.3815 c=0 +rf919 (\23\:vdd! \87\:vdd!) resistor r=0.3815 c=0 +rf920 (\24\:vdd! \88\:vdd!) resistor r=0.3775 c=0 +rf921 (\25\:vdd! \89\:vdd!) resistor r=0.4015 c=0 +rf922 (\26\:vdd! \90\:vdd!) resistor r=0.3994 c=0 +rf923 (\27\:vdd! \91\:vdd!) resistor r=0.3774 c=0 +rf924 (\28\:vdd! \92\:vdd!) resistor r=0.3815 c=0 +rf925 (\29\:vdd! \93\:vdd!) resistor r=0.3815 c=0 +rf926 (\30\:vdd! \94\:vdd!) resistor r=0.521 c=0 +rf927 (\30\:vdd! \95\:vdd!) resistor r=0.5021 c=0 +rf928 (\31\:vdd! \96\:vdd!) resistor r=0.3805 c=0 +rf929 (\32\:vdd! \97\:vdd!) resistor r=0.3968 c=0 +rf930 (\33\:vdd! \98\:vdd!) resistor r=0.3878 c=0 +rf931 (\34\:vdd! \99\:vdd!) resistor r=0.3973 c=0 +rf932 (\35\:vdd! \100\:vdd!) resistor r=0.5236 c=0 +rf933 (\36\:vdd! \101\:vdd!) resistor r=0.3994 c=0 +rf934 (\37\:vdd! \102\:vdd!) resistor r=0.3733 c=0 +rf935 (\38\:vdd! \103\:vdd!) resistor r=0.4019 c=0 +rf936 (\39\:vdd! \104\:vdd!) resistor r=0.4246 c=0 +rf937 (\40\:vdd! \105\:vdd!) resistor r=0.4226 c=0 +rf938 (\41\:vdd! \106\:vdd!) resistor r=0.4019 c=0 +rf939 (\42\:vdd! \107\:vdd!) resistor r=0.3955 c=0 +rf940 (\43\:vdd! \108\:vdd!) resistor r=0.3769 c=0 +rf941 (\44\:vdd! \109\:vdd!) resistor r=0.3809 c=0 +rf942 (\45\:vdd! \110\:vdd!) resistor r=0.3809 c=0 +rf943 (\46\:vdd! \111\:vdd!) resistor r=0.5188 c=0 +rf944 (\46\:vdd! \112\:vdd!) resistor r=0.5043 c=0 +rf945 (\47\:vdd! \113\:vdd!) resistor r=0.3809 c=0 +rf946 (\48\:vdd! \114\:vdd!) resistor r=0.4028 c=0 +rf947 (\49\:vdd! \115\:vdd!) resistor r=0.3882 c=0 +rf948 (\50\:vdd! \116\:vdd!) resistor r=0.3934 c=0 +rf949 (\51\:vdd! \117\:vdd!) resistor r=0.5224 c=0 +rf950 (\52\:vdd! \118\:vdd!) resistor r=0.3975 c=0 +rf951 (\53\:vdd! \119\:vdd!) resistor r=0.3769 c=0 +rf952 (\54\:vdd! \120\:vdd!) resistor r=0.3965 c=0 +rf953 (\55\:vdd! \121\:vdd!) resistor r=0.3965 c=0 +rf954 (\56\:vdd! \122\:vdd!) resistor r=0.3975 c=0 +rf955 (\59\:vdd! \123\:vdd!) resistor r=0.09153 c=0 +rf956 (\123\:vdd! \124\:vdd!) resistor r=0.4738 c=0 +rf957 (\59\:vdd! \125\:vdd!) resistor r=0.4236 c=0 +rf958 (\61\:vdd! \126\:vdd!) resistor r=0.08918 c=0 +rf959 (\126\:vdd! \127\:vdd!) resistor r=0.02324 c=0 +rf960 (\127\:vdd! \128\:vdd!) resistor r=0.5125 c=0 +rf961 (\61\:vdd! \129\:vdd!) resistor r=0.5256 c=0 +rf962 (\123\:vdd! \130\:vdd!) resistor r=0.08497 c=0 +rf963 (\130\:vdd! \131\:vdd!) resistor r=0.4974 c=0 +rf964 (\123\:vdd! \132\:vdd!) resistor r=0.4853 c=0 +rf965 (\127\:vdd! \133\:vdd!) resistor r=0.08278 c=0 +rf966 (\133\:vdd! \134\:vdd!) resistor r=0.1069 c=0 +rf967 (\134\:vdd! \135\:vdd!) resistor r=0.1034 c=0 +rf968 (\135\:vdd! \136\:vdd!) resistor r=0.4972 c=0 +rf969 (\127\:vdd! \137\:vdd!) resistor r=0.5158 c=0 +rf970 (\130\:vdd! \138\:vdd!) resistor r=0.0271 c=0 +rf971 (\138\:vdd! \139\:vdd!) resistor r=0.04574 c=0 +rf972 (\139\:vdd! \140\:vdd!) resistor r=0.3976 c=0 +rf973 (\130\:vdd! \141\:vdd!) resistor r=0.5029 c=0 +rf974 (\133\:vdd! \142\:vdd!) resistor r=0.4829 c=0 +rf975 (\134\:vdd! \143\:vdd!) resistor r=0.4789 c=0 +rf976 (\135\:vdd! \144\:vdd!) resistor r=0.06491 c=0 +rf977 (\144\:vdd! \145\:vdd!) resistor r=0.04205 c=0 +rf978 (\145\:vdd! \146\:vdd!) resistor r=0.3944 c=0 +rf979 (\135\:vdd! \147\:vdd!) resistor r=0.4717 c=0 +rf980 (\139\:vdd! \148\:vdd!) resistor r=0.06326 c=0 +rf981 (\148\:vdd! \149\:vdd!) resistor r=0.04045 c=0 +rf982 (\149\:vdd! \150\:vdd!) resistor r=0.5014 c=0 +rf983 (\144\:vdd! \151\:vdd!) resistor r=0.4564 c=0 +rf984 (\145\:vdd! \152\:vdd!) resistor r=0.06014 c=0 +rf985 (\152\:vdd! \153\:vdd!) resistor r=0.0715 c=0 +rf986 (\153\:vdd! \154\:vdd!) resistor r=0.03861 c=0 +rf987 (\154\:vdd! \155\:vdd!) resistor r=0.06161 c=0 +rf988 (\155\:vdd! \156\:vdd!) resistor r=0.02915 c=0 +rf989 (\156\:vdd! \157\:vdd!) resistor r=0.4154 c=0 +rf990 (\148\:vdd! \158\:vdd!) resistor r=0.4621 c=0 +rf991 (\149\:vdd! \159\:vdd!) resistor r=0.1028 c=0 +rf992 (\159\:vdd! \160\:vdd!) resistor r=0.06303 c=0 +rf993 (\160\:vdd! \161\:vdd!) resistor r=0.05368 c=0 +rf994 (\161\:vdd! \162\:vdd!) resistor r=0.05529 c=0 +rf995 (\162\:vdd! \163\:vdd!) resistor r=0.52 c=0 +rf996 (\149\:vdd! \164\:vdd!) resistor r=0.467 c=0 +rf997 (\153\:vdd! \165\:vdd!) resistor r=0.3985 c=0 +rf998 (\155\:vdd! \166\:vdd!) resistor r=0.4154 c=0 +rf999 (\156\:vdd! \167\:vdd!) resistor r=0.04924 c=0 +rf1000 (\167\:vdd! \168\:vdd!) resistor r=0.1599 c=0 +rf1001 (\168\:vdd! \169\:vdd!) resistor r=0.07474 c=0 +rf1002 (\169\:vdd! \170\:vdd!) resistor r=0.3985 c=0 +rf1003 (\159\:vdd! \171\:vdd!) resistor r=0.3658 c=0 +rf1004 (\161\:vdd! \172\:vdd!) resistor r=0.4003 c=0 +rf1005 (\162\:vdd! \173\:vdd!) resistor r=0.1145 c=0 +rf1006 (\173\:vdd! \174\:vdd!) resistor r=0.4992 c=0 +rf1007 (\162\:vdd! \175\:vdd!) resistor r=0.5011 c=0 +rf1008 (\167\:vdd! \176\:vdd!) resistor r=0.3985 c=0 +rf1009 (\168\:vdd! \177\:vdd!) resistor r=0.3768 c=0 +rf1010 (\169\:vdd! \178\:vdd!) resistor r=0.03227 c=0 +rf1011 (\178\:vdd! \179\:vdd!) resistor r=0.07091 c=0 +rf1012 (\179\:vdd! \180\:vdd!) resistor r=0.3944 c=0 +rf1013 (\173\:vdd! \181\:vdd!) resistor r=0.11 c=0 +rf1014 (\181\:vdd! \182\:vdd!) resistor r=0.01688 c=0 +rf1015 (\182\:vdd! \183\:vdd!) resistor r=0.02859 c=0 +rf1016 (\183\:vdd! \184\:vdd!) resistor r=0.4171 c=0 +rf1017 (\173\:vdd! \185\:vdd!) resistor r=0.5267 c=0 +rf1018 (\178\:vdd! \186\:vdd!) resistor r=0.5222 c=0 +rf1019 (\179\:vdd! \187\:vdd!) resistor r=0.02544 c=0 +rf1020 (\187\:vdd! \188\:vdd!) resistor r=0.02894 c=0 +rf1021 (\188\:vdd! \189\:vdd!) resistor r=0.4059 c=0 +rf1022 (\182\:vdd! \190\:vdd!) resistor r=0.4193 c=0 +rf1023 (\183\:vdd! \191\:vdd!) resistor r=0.04829 c=0 +rf1024 (\191\:vdd! \192\:vdd!) resistor r=0.1035 c=0 +rf1025 (\192\:vdd! \193\:vdd!) resistor r=0.05234 c=0 +rf1026 (\193\:vdd! \194\:vdd!) resistor r=0.07331 c=0 +rf1027 (\194\:vdd! \195\:vdd!) resistor r=0.4003 c=0 +rf1028 (\187\:vdd! \196\:vdd!) resistor r=0.3881 c=0 +rf1029 (\188\:vdd! \197\:vdd!) resistor r=0.02627 c=0 +rf1030 (\197\:vdd! \198\:vdd!) resistor r=0.02216 c=0 +rf1031 (\198\:vdd! \199\:vdd!) resistor r=0.07917 c=0 +rf1032 (\199\:vdd! \200\:vdd!) resistor r=0.5204 c=0 +rf1033 (\191\:vdd! \201\:vdd!) resistor r=0.4025 c=0 +rf1034 (\192\:vdd! \202\:vdd!) resistor r=0.4025 c=0 +rf1035 (\193\:vdd! \203\:vdd!) resistor r=0.3697 c=0 +rf1036 (\194\:vdd! \204\:vdd!) resistor r=0.03166 c=0 +rf1037 (\204\:vdd! \205\:vdd!) resistor r=0.06955 c=0 +rf1038 (\205\:vdd! \206\:vdd!) resistor r=0.3961 c=0 +rf1039 (\197\:vdd! \207\:vdd!) resistor r=0.3808 c=0 +rf1040 (\199\:vdd! \208\:vdd!) resistor r=0.01667 c=0 +rf1041 (\208\:vdd! \209\:vdd!) resistor r=0.03729 c=0 +rf1042 (\209\:vdd! \210\:vdd!) resistor r=0.1055 c=0 +rf1043 (\210\:vdd! \211\:vdd!) resistor r=0.05007 c=0 +rf1044 (\211\:vdd! \212\:vdd!) resistor r=0.05073 c=0 +rf1045 (\212\:vdd! \213\:vdd!) resistor r=0.3985 c=0 +rf1046 (\199\:vdd! \214\:vdd!) resistor r=0.5026 c=0 +rf1047 (\204\:vdd! \215\:vdd!) resistor r=0.511 c=0 +rf1048 (\205\:vdd! \216\:vdd!) resistor r=0.02496 c=0 +rf1049 (\216\:vdd! \217\:vdd!) resistor r=0.02839 c=0 +rf1050 (\217\:vdd! \218\:vdd!) resistor r=0.4076 c=0 +rf1051 (\209\:vdd! \219\:vdd!) resistor r=0.3808 c=0 +rf1052 (\210\:vdd! \220\:vdd!) resistor r=0.3808 c=0 +rf1053 (\211\:vdd! \221\:vdd!) resistor r=0.3768 c=0 +rf1054 (\212\:vdd! \222\:vdd!) resistor r=0.1583 c=0 +rf1055 (\222\:vdd! \223\:vdd!) resistor r=0.03795 c=0 +rf1056 (\223\:vdd! \224\:vdd!) resistor r=0.3997 c=0 +rf1057 (\216\:vdd! \225\:vdd!) resistor r=0.3809 c=0 +rf1058 (\217\:vdd! \226\:vdd!) resistor r=0.02577 c=0 +rf1059 (\226\:vdd! \227\:vdd!) resistor r=0.08626 c=0 +rf1060 (\227\:vdd! \228\:vdd!) resistor r=0.444 c=0 +rf1061 (\223\:vdd! \229\:vdd!) resistor r=0.05073 c=0 +rf1062 (\229\:vdd! \230\:vdd!) resistor r=0.05007 c=0 +rf1063 (\230\:vdd! \231\:vdd!) resistor r=0.1055 c=0 +rf1064 (\231\:vdd! \232\:vdd!) resistor r=0.05397 c=0 +rf1065 (\232\:vdd! \233\:vdd!) resistor r=0.5215 c=0 +rf1066 (\226\:vdd! \234\:vdd!) resistor r=0.3736 c=0 +rf1067 (\227\:vdd! \235\:vdd!) resistor r=0.06722 c=0 +rf1068 (\235\:vdd! \236\:vdd!) resistor r=0.1035 c=0 +rf1069 (\236\:vdd! \237\:vdd!) resistor r=0.04912 c=0 +rf1070 (\237\:vdd! \238\:vdd!) resistor r=0.04976 c=0 +rf1071 (\238\:vdd! \239\:vdd!) resistor r=0.4003 c=0 +rf1072 (\227\:vdd! \240\:vdd!) resistor r=0.4204 c=0 +rf1073 (\229\:vdd! \241\:vdd!) resistor r=0.3757 c=0 +rf1074 (\230\:vdd! \242\:vdd!) resistor r=0.3797 c=0 +rf1075 (\231\:vdd! \243\:vdd!) resistor r=0.3797 c=0 +rf1076 (\232\:vdd! \244\:vdd!) resistor r=0.0772 c=0 +rf1077 (\244\:vdd! \245\:vdd!) resistor r=0.02413 c=0 +rf1078 (\245\:vdd! \246\:vdd!) resistor r=0.02627 c=0 +rf1079 (\246\:vdd! \247\:vdd!) resistor r=0.407 c=0 +rf1080 (\232\:vdd! \248\:vdd!) resistor r=0.5015 c=0 +rf1081 (\235\:vdd! \249\:vdd!) resistor r=0.3736 c=0 +rf1082 (\236\:vdd! \250\:vdd!) resistor r=0.3736 c=0 +rf1083 (\237\:vdd! \251\:vdd!) resistor r=0.3697 c=0 +rf1084 (\238\:vdd! \252\:vdd!) resistor r=0.08109 c=0 +rf1085 (\252\:vdd! \253\:vdd!) resistor r=0.03142 c=0 +rf1086 (\253\:vdd! \254\:vdd!) resistor r=0.4025 c=0 +rf1087 (\245\:vdd! \255\:vdd!) resistor r=0.3797 c=0 +rf1088 (\246\:vdd! \256\:vdd!) resistor r=0.02894 c=0 +rf1089 (\256\:vdd! \257\:vdd!) resistor r=0.02544 c=0 +rf1090 (\257\:vdd! \258\:vdd!) resistor r=0.3954 c=0 +rf1091 (\253\:vdd! \259\:vdd!) resistor r=0.04976 c=0 +rf1092 (\259\:vdd! \260\:vdd!) resistor r=0.04912 c=0 +rf1093 (\260\:vdd! \261\:vdd!) resistor r=0.1035 c=0 +rf1094 (\261\:vdd! \262\:vdd!) resistor r=0.039 c=0 +rf1095 (\262\:vdd! \263\:vdd!) resistor r=0.4719 c=0 +rf1096 (\256\:vdd! \264\:vdd!) resistor r=0.387 c=0 +rf1097 (\257\:vdd! \265\:vdd!) resistor r=0.0506 c=0 +rf1098 (\265\:vdd! \266\:vdd!) resistor r=0.02031 c=0 +rf1099 (\266\:vdd! \267\:vdd!) resistor r=0.03227 c=0 +rf1100 (\267\:vdd! \268\:vdd!) resistor r=0.3997 c=0 +rf1101 (\259\:vdd! \269\:vdd!) resistor r=0.3675 c=0 +rf1102 (\260\:vdd! \270\:vdd!) resistor r=0.3714 c=0 +rf1103 (\261\:vdd! \271\:vdd!) resistor r=0.3714 c=0 +rf1104 (\262\:vdd! \272\:vdd!) resistor r=0.03309 c=0 +rf1105 (\272\:vdd! \273\:vdd!) resistor r=0.07884 c=0 +rf1106 (\273\:vdd! \274\:vdd!) resistor r=0.0398 c=0 +rf1107 (\274\:vdd! \275\:vdd!) resistor r=0.457 c=0 +rf1108 (\262\:vdd! \276\:vdd!) resistor r=0.469 c=0 +rf1109 (\266\:vdd! \277\:vdd!) resistor r=0.5205 c=0 +rf1110 (\267\:vdd! \278\:vdd!) resistor r=0.07474 c=0 +rf1111 (\278\:vdd! \279\:vdd!) resistor r=0.1343 c=0 +rf1112 (\279\:vdd! \280\:vdd!) resistor r=0.07645 c=0 +rf1113 (\280\:vdd! \281\:vdd!) resistor r=0.5178 c=0 +rf1114 (\273\:vdd! \282\:vdd!) resistor r=0.3714 c=0 +rf1115 (\274\:vdd! \283\:vdd!) resistor r=0.0406 c=0 +rf1116 (\283\:vdd! \284\:vdd!) resistor r=0.3983 c=0 +rf1117 (\274\:vdd! \285\:vdd!) resistor r=0.4394 c=0 +rf1118 (\278\:vdd! \286\:vdd!) resistor r=0.3757 c=0 +rf1119 (\279\:vdd! \287\:vdd!) resistor r=0.3997 c=0 +rf1120 (\280\:vdd! \288\:vdd!) resistor r=0.1145 c=0 +rf1121 (\288\:vdd! \289\:vdd!) resistor r=0.07545 c=0 +rf1122 (\289\:vdd! \290\:vdd!) resistor r=0.3985 c=0 +rf1123 (\280\:vdd! \291\:vdd!) resistor r=0.5178 c=0 +rf1124 (\283\:vdd! \292\:vdd!) resistor r=0.06955 c=0 +rf1125 (\292\:vdd! \293\:vdd!) resistor r=0.03166 c=0 +rf1126 (\293\:vdd! \294\:vdd!) resistor r=0.4025 c=0 +rf1127 (\288\:vdd! \295\:vdd!) resistor r=0.4804 c=0 +rf1128 (\289\:vdd! \296\:vdd!) resistor r=0.05073 c=0 +rf1129 (\296\:vdd! \297\:vdd!) resistor r=0.05007 c=0 +rf1130 (\297\:vdd! \298\:vdd!) resistor r=0.1055 c=0 +rf1131 (\298\:vdd! \299\:vdd!) resistor r=0.05397 c=0 +rf1132 (\299\:vdd! \300\:vdd!) resistor r=0.5204 c=0 +rf1133 (\292\:vdd! \301\:vdd!) resistor r=0.5076 c=0 +rf1134 (\293\:vdd! \302\:vdd!) resistor r=0.07331 c=0 +rf1135 (\302\:vdd! \303\:vdd!) resistor r=0.1136 c=0 +rf1136 (\303\:vdd! \304\:vdd!) resistor r=0.06973 c=0 +rf1137 (\304\:vdd! \305\:vdd!) resistor r=0.02618 c=0 +rf1138 (\305\:vdd! \306\:vdd!) resistor r=0.4025 c=0 +rf1139 (\296\:vdd! \307\:vdd!) resistor r=0.3768 c=0 +rf1140 (\297\:vdd! \308\:vdd!) resistor r=0.3808 c=0 +rf1141 (\298\:vdd! \309\:vdd!) resistor r=0.3808 c=0 +rf1142 (\299\:vdd! \310\:vdd!) resistor r=0.06371 c=0 +rf1143 (\310\:vdd! \311\:vdd!) resistor r=0.03762 c=0 +rf1144 (\311\:vdd! \312\:vdd!) resistor r=0.02627 c=0 +rf1145 (\312\:vdd! \313\:vdd!) resistor r=0.4059 c=0 +rf1146 (\299\:vdd! \314\:vdd!) resistor r=0.5026 c=0 +rf1147 (\302\:vdd! \315\:vdd!) resistor r=0.3675 c=0 +rf1148 (\303\:vdd! \316\:vdd!) resistor r=0.4014 c=0 +rf1149 (\304\:vdd! \317\:vdd!) resistor r=0.4044 c=0 +rf1150 (\305\:vdd! \318\:vdd!) resistor r=0.09561 c=0 +rf1151 (\318\:vdd! \319\:vdd!) resistor r=0.0604 c=0 +rf1152 (\319\:vdd! \320\:vdd!) resistor r=0.4159 c=0 +rf1153 (\311\:vdd! \321\:vdd!) resistor r=0.3808 c=0 +rf1154 (\312\:vdd! \322\:vdd!) resistor r=0.02894 c=0 +rf1155 (\322\:vdd! \323\:vdd!) resistor r=0.02544 c=0 +rf1156 (\323\:vdd! \324\:vdd!) resistor r=0.3944 c=0 +rf1157 (\318\:vdd! \325\:vdd!) resistor r=0.4861 c=0 +rf1158 (\319\:vdd! \326\:vdd!) resistor r=0.02853 c=0 +rf1159 (\326\:vdd! \327\:vdd!) resistor r=0.03782 c=0 +rf1160 (\327\:vdd! \328\:vdd!) resistor r=0.0281 c=0 +rf1161 (\328\:vdd! \329\:vdd!) resistor r=0.02813 c=0 +rf1162 (\329\:vdd! \330\:vdd!) resistor r=0.4038 c=0 +rf1163 (\322\:vdd! \331\:vdd!) resistor r=0.3881 c=0 +rf1164 (\323\:vdd! \332\:vdd!) resistor r=0.05784 c=0 +rf1165 (\332\:vdd! \333\:vdd!) resistor r=0.04585 c=0 +rf1166 (\333\:vdd! \334\:vdd!) resistor r=0.3985 c=0 +rf1167 (\326\:vdd! \335\:vdd!) resistor r=0.4148 c=0 +rf1168 (\328\:vdd! \336\:vdd!) resistor r=0.4027 c=0 +rf1169 (\329\:vdd! \337\:vdd!) resistor r=0.06649 c=0 +rf1170 (\337\:vdd! \338\:vdd!) resistor r=0.1013 c=0 +rf1171 (\338\:vdd! \339\:vdd!) resistor r=0.1159 c=0 +rf1172 (\339\:vdd! \340\:vdd!) resistor r=0.5024 c=0 +rf1173 (\332\:vdd! \341\:vdd!) resistor r=0.617 c=0 +rf1174 (\333\:vdd! \342\:vdd!) resistor r=0.07474 c=0 +rf1175 (\342\:vdd! \343\:vdd!) resistor r=0.1076 c=0 +rf1176 (\343\:vdd! \344\:vdd!) resistor r=0.07294 c=0 +rf1177 (\344\:vdd! \345\:vdd!) resistor r=0.03281 c=0 +rf1178 (\345\:vdd! \346\:vdd!) resistor r=0.3985 c=0 +rf1179 (\337\:vdd! \347\:vdd!) resistor r=0.5065 c=0 +rf1180 (\338\:vdd! \348\:vdd!) resistor r=0.4589 c=0 +rf1181 (\339\:vdd! \349\:vdd!) resistor r=0.04944 c=0 +rf1182 (\349\:vdd! \350\:vdd!) resistor r=0.04887 c=0 +rf1183 (\350\:vdd! \351\:vdd!) resistor r=0.4238 c=0 +rf1184 (\339\:vdd! \352\:vdd!) resistor r=0.4635 c=0 +rf1185 (\342\:vdd! \353\:vdd!) resistor r=0.3768 c=0 +rf1186 (\343\:vdd! \354\:vdd!) resistor r=0.4019 c=0 +rf1187 (\344\:vdd! \355\:vdd!) resistor r=0.4019 c=0 +rf1188 (\345\:vdd! \356\:vdd!) resistor r=0.06262 c=0 +rf1189 (\349\:vdd! \357\:vdd!) resistor r=0.49 c=0 +rf1190 (\350\:vdd! \358\:vdd!) resistor r=0.1152 c=0 +rf1191 (\358\:vdd! \359\:vdd!) resistor r=0.4926 c=0 +rf1192 (\356\:vdd! \360\:vdd!) resistor r=0.4309 c=0 +rf1193 (\358\:vdd! \361\:vdd!) resistor r=0.02438 c=0 +rf1194 (\361\:vdd! \362\:vdd!) resistor r=0.04862 c=0 +rf1195 (\362\:vdd! \363\:vdd!) resistor r=0.5103 c=0 +rf1196 (\358\:vdd! \364\:vdd!) resistor r=0.5128 c=0 +rf1197 (\362\:vdd! \365\:vdd!) resistor r=0.07402 c=0 +rf1198 (\365\:vdd! \366\:vdd!) resistor r=0.0174 c=0 +rf1199 (\366\:vdd! \367\:vdd!) resistor r=0.4537 c=0 +rf1200 (\362\:vdd! \368\:vdd!) resistor r=0.5159 c=0 +rf1201 (\366\:vdd! \369\:vdd!) resistor r=0.5053 c=0 +rg1 (\7\:X3 \8\:X3) resistor r=91.5933 c=0 +rg2 (\8\:X3 \2\:X3) resistor r=3.7604 c=0 +rg3 (\8\:X3 \9\:X3) resistor r=62.0099 c=0 +rg4 (\10\:X3 \11\:X3) resistor r=91.5933 c=0 +rg5 (\11\:X3 \4\:X3) resistor r=3.7604 c=0 +rg6 (\11\:X3 \12\:X3) resistor r=62.0099 c=0 +rg7 (\13\:X3 \14\:X3) resistor r=91.5933 c=0 +rg8 (\14\:X3 \6\:X3) resistor r=3.7604 c=0 +rg9 (\14\:X3 \15\:X3) resistor r=62.0099 c=0 +rg10 (\1\:Y3 \2\:Y3) resistor r=3.7604 c=0 +rg11 (\2\:Y3 \3\:Y3) resistor r=62.0099 c=0 +rg12 (\2\:Y3 \4\:Y3) resistor r=91.5933 c=0 +rg13 (\1\:Y2 \2\:Y2) resistor r=3.7604 c=0 +rg14 (\2\:Y2 \3\:Y2) resistor r=62.0099 c=0 +rg15 (\2\:Y2 \4\:Y2) resistor r=91.5933 c=0 +rg16 (\1\:X0 \2\:X0) resistor r=3.7604 c=0 +rg17 (\2\:X0 \3\:X0) resistor r=91.5933 c=0 +rg18 (\2\:X0 \4\:X0) resistor r=62.0099 c=0 +rg20 (\2\:Y1 \3\:Y1) resistor r=62.0099 c=0 +rg21 (\2\:Y1 \4\:Y1) resistor r=91.5933 c=0 +rg22 (\4\:Y1 \5\:Y1) resistor r=134.735 c=0 +rg23 (\5\:I27\|net013 \6\:I27\|net013) resistor r=37.6755 c=0 +rg24 (\6\:I27\|net013 I27\|net013) resistor r=19.7812 c=0 +rg25 (\6\:I27\|net013 \7\:I27\|net013) resistor r=115.592 c=0 +rg26 (\5\:I20\|net013 \6\:I20\|net013) resistor r=37.6755 c=0 +rg27 (\6\:I20\|net013 I20\|net013) resistor r=19.7812 c=0 +rg28 (\6\:I20\|net013 \7\:I20\|net013) resistor r=115.592 c=0 +rg29 (\5\:I15\|net013 \6\:I15\|net013) resistor r=115.592 c=0 +rg30 (\6\:I15\|net013 I15\|net013) resistor r=19.7812 c=0 +rg31 (\6\:I15\|net013 \7\:I15\|net013) resistor r=37.6755 c=0 +rg32 (\5\:I19\|net013 \6\:I19\|net013) resistor r=37.6755 c=0 +rg33 (\6\:I19\|net013 I19\|net013) resistor r=19.7812 c=0 +rg34 (\6\:I19\|net013 \7\:I19\|net013) resistor r=115.592 c=0 +rg35 (\6\:net090 \7\:net090) resistor r=132.954 c=0 +rg36 (\7\:net090 \8\:net090) resistor r=83.7878 c=0 +rg37 (\7\:net090 net090) resistor r=15.5249 c=0 +rg38 (\6\:net13 \7\:net13) resistor r=132.954 c=0 +rg39 (\7\:net13 \8\:net13) resistor r=83.7878 c=0 +rg40 (\7\:net13 net13) resistor r=15.5249 c=0 +rg41 (I5\|I3\|net013 \2\:I5\|I3\|net013) resistor r=3.7604 c=0 +rg42 (\2\:I5\|I3\|net013 \3\:I5\|I3\|net013) resistor r=109.302 c=0 +rg43 (\2\:I5\|I3\|net013 \4\:I5\|I3\|net013) resistor r=43.2599 c=0 +rg44 (I4\|I4\|Bi \2\:I4\|I4\|Bi) resistor r=3.4479 c=0 +rg45 (\2\:I4\|I4\|Bi \3\:I4\|I4\|Bi) resistor r=70.5516 c=0 +rg46 (\2\:I4\|I4\|Bi \4\:I4\|I4\|Bi) resistor r=68.2599 c=0 +rg47 (\4\:I4\|I4\|Ai \5\:I4\|I4\|Ai) resistor r=426.762 c=0 +rg48 (\5\:I4\|I4\|Ai \3\:I4\|I4\|Ai) resistor r=295.399 c=0 +rg49 (I9\|I4\|Bi \2\:I9\|I4\|Bi) resistor r=3.4479 c=0 +rg50 (\2\:I9\|I4\|Bi \3\:I9\|I4\|Bi) resistor r=70.5516 c=0 +rg51 (\2\:I9\|I4\|Bi \4\:I9\|I4\|Bi) resistor r=68.2599 c=0 +rg52 (\4\:I9\|I4\|Ai \5\:I9\|I4\|Ai) resistor r=426.762 c=0 +rg53 (\5\:I9\|I4\|Ai \3\:I9\|I4\|Ai) resistor r=295.399 c=0 +rg54 (\9\:net090 \10\:net090) resistor r=68.6766 c=0 +rg55 (\10\:net090 \11\:net090) resistor r=39.0198 c=0 +rg56 (\11\:net090 \12\:net090) resistor r=3.7604 c=0 +rg57 (\12\:net090 \13\:net090) resistor r=42.4747 c=0 +rg58 (\13\:net090 \14\:net090) resistor r=51.4263 c=0 +rg59 (\10\:net090 \15\:net090) resistor r=3.6562 c=0 +rg60 (\11\:net090 \16\:net090) resistor r=47.6349 c=0 +rg61 (\13\:net090 \17\:net090) resistor r=106.01 c=0 +rg62 (\9\:net13 \10\:net13) resistor r=68.6766 c=0 +rg63 (\10\:net13 \11\:net13) resistor r=39.0198 c=0 +rg64 (\11\:net13 \12\:net13) resistor r=3.7604 c=0 +rg65 (\12\:net13 \13\:net13) resistor r=42.4747 c=0 +rg66 (\13\:net13 \14\:net13) resistor r=51.4263 c=0 +rg67 (\10\:net13 \15\:net13) resistor r=3.6562 c=0 +rg68 (\11\:net13 \16\:net13) resistor r=47.6349 c=0 +rg69 (\13\:net13 \17\:net13) resistor r=106.01 c=0 +rg70 (\5\:I5\|I1\|Bi \6\:I5\|I1\|Bi) resistor r=53.0516 c=0 +rg71 (\6\:I5\|I1\|Bi \4\:I5\|I1\|Bi) resistor r=3.6562 c=0 +rg72 (\6\:I5\|I1\|Bi \7\:I5\|I1\|Bi) resistor r=84.0933 c=0 +rg73 (\7\:net19 \9\:net19) resistor r=3.7604 c=0 +rg74 (\9\:net19 \10\:net19) resistor r=47.6349 c=0 +rg75 (\10\:net19 \11\:net19) resistor r=149.112 c=0 +rg76 (\11\:net19 \12\:net19) resistor r=237.862 c=0 +rg77 (\12\:net19 \13\:net19) resistor r=167.131 c=0 +rg78 (\9\:net19 \14\:net19) resistor r=109.093 c=0 +rg79 (\11\:net19 \15\:net19) resistor r=54.2235 c=0 +rg80 (\15\:net19 \16\:net19) resistor r=140.208 c=0 +rg81 (\2\:net16 \4\:net16) resistor r=3.7604 c=0 +rg82 (\4\:net16 \5\:net16) resistor r=47.6349 c=0 +rg83 (\5\:net16 \6\:net16) resistor r=149.112 c=0 +rg84 (\6\:net16 \7\:net16) resistor r=237.862 c=0 +rg85 (\7\:net16 \8\:net16) resistor r=167.131 c=0 +rg86 (\4\:net16 \9\:net16) resistor r=109.093 c=0 +rg87 (\6\:net16 \10\:net16) resistor r=54.2235 c=0 +rg88 (\10\:net16 \11\:net16) resistor r=140.208 c=0 +rg89 (\10\:I4\|net3 \11\:I4\|net3) resistor r=97.8433 c=0 +rg90 (\11\:I4\|net3 \9\:I4\|net3) resistor r=3.7604 c=0 +rg91 (\11\:I4\|net3 \12\:I4\|net3) resistor r=40.9683 c=0 +rg92 (\10\:I9\|net3 \11\:I9\|net3) resistor r=97.8433 c=0 +rg93 (\11\:I9\|net3 \9\:I9\|net3) resistor r=3.7604 c=0 +rg94 (\11\:I9\|net3 \12\:I9\|net3) resistor r=40.9683 c=0 +rg95 (\2\:net55 \7\:net55) resistor r=3.7604 c=0 +rg96 (\7\:net55 \8\:net55) resistor r=73.0516 c=0 +rg97 (\7\:net55 \9\:net55) resistor r=79.5099 c=0 +rg98 (\8\:net55 \5\:net55) resistor r=77.3221 c=0 +rg99 (\5\:I4\|net1 \6\:I4\|net1) resistor r=80.5516 c=0 +rg100 (\6\:I4\|net1 \4\:I4\|net1) resistor r=3.5521 c=0 +rg101 (\6\:I4\|net1 \7\:I4\|net1) resistor r=76.1766 c=0 +rg102 (\5\:I9\|net1 \6\:I9\|net1) resistor r=80.5516 c=0 +rg103 (\6\:I9\|net1 \4\:I9\|net1) resistor r=3.5521 c=0 +rg104 (\6\:I9\|net1 \7\:I9\|net1) resistor r=76.1766 c=0 +rg105 (\21\:X3 \22\:X3) resistor r=91.5933 c=0 +rg106 (\22\:X3 \20\:X3) resistor r=3.7604 c=0 +rg107 (\22\:X3 \23\:X3) resistor r=62.0099 c=0 +rg108 (\10\:net55 \11\:net55) resistor r=47.3355 c=0 +rg109 (\11\:net55 \12\:net55) resistor r=120.434 c=0 +rg110 (\12\:net55 \13\:net55) resistor r=41.6577 c=0 +rg111 (\11\:net55 \14\:net55) resistor r=7.4762 c=0 +rg112 (\12\:net55 \3\:net55) resistor r=32.1097 c=0 +rg113 (I4\|net6 \2\:I4\|net6) resistor r=3.5521 c=0 +rg114 (\2\:I4\|net6 \3\:I4\|net6) resistor r=77.0099 c=0 +rg115 (\2\:I4\|net6 \4\:I4\|net6) resistor r=79.7183 c=0 +rg116 (I9\|net6 \2\:I9\|net6) resistor r=3.5521 c=0 +rg117 (\2\:I9\|net6 \3\:I9\|net6) resistor r=77.0099 c=0 +rg118 (\2\:I9\|net6 \4\:I9\|net6) resistor r=79.7183 c=0 +rg119 (\6\:net093 \7\:net093) resistor r=174.262 c=0 +rg120 (\7\:net093 \8\:net093) resistor r=165.153 c=0 +rg121 (\8\:net093 \9\:net093) resistor r=116.403 c=0 +rg122 (\9\:net093 \10\:net093) resistor r=138.542 c=0 +rg123 (\8\:net093 \11\:net093) resistor r=135.474 c=0 +rg124 (\11\:net093 \12\:net093) resistor r=72.4266 c=0 +rg125 (\12\:net093 \4\:net093) resistor r=3.7604 c=0 +rg126 (\12\:net093 \13\:net093) resistor r=80.1349 c=0 +rg127 (I5\|I1\|Ai \2\:I5\|I1\|Ai) resistor r=77.852 c=0 +rg128 (\2\:I5\|I1\|Ai \3\:I5\|I1\|Ai) resistor r=333.882 c=0 +rg129 (\16\:net55 \17\:net55) resistor r=3.7604 c=0 +rg130 (\17\:net55 \18\:net55) resistor r=55.3433 c=0 +rg131 (\17\:net55 \19\:net55) resistor r=81.8016 c=0 +rg132 (\5\:I12\|net013 \6\:I12\|net013) resistor r=37.6755 c=0 +rg133 (\6\:I12\|net013 I12\|net013) resistor r=19.7812 c=0 +rg134 (\6\:I12\|net013 \7\:I12\|net013) resistor r=115.592 c=0 +rg135 (\16\:I4\|net3 \17\:I4\|net3) resistor r=158.125 c=0 +rg136 (\17\:I4\|net3 \18\:I4\|net3) resistor r=211.449 c=0 +rg137 (\18\:I4\|net3 \19\:I4\|net3) resistor r=168.536 c=0 +rg138 (\19\:I4\|net3 \15\:I4\|net3) resistor r=6.3083 c=0 +rg139 (\19\:I4\|net3 \20\:I4\|net3) resistor r=38.7601 c=0 +rg140 (\5\:I4\|I3\|Ai I4\|I3\|Ai) resistor r=317.339 c=0 +rg141 (I4\|I3\|Ai \6\:I4\|I3\|Ai) resistor r=91.8988 c=0 +rg142 (\16\:I9\|net3 \17\:I9\|net3) resistor r=158.125 c=0 +rg143 (\17\:I9\|net3 \18\:I9\|net3) resistor r=211.449 c=0 +rg144 (\18\:I9\|net3 \19\:I9\|net3) resistor r=168.536 c=0 +rg145 (\19\:I9\|net3 \15\:I9\|net3) resistor r=6.3083 c=0 +rg146 (\19\:I9\|net3 \20\:I9\|net3) resistor r=38.7601 c=0 +rg147 (\5\:I9\|I3\|Ai I9\|I3\|Ai) resistor r=317.339 c=0 +rg148 (I9\|I3\|Ai \6\:I9\|I3\|Ai) resistor r=91.8988 c=0 +rg149 (\4\:net21 \5\:net21) resistor r=181.923 c=0 +rg150 (\5\:net21 \6\:net21) resistor r=107.843 c=0 +rg151 (\6\:net21 \7\:net21) resistor r=48.8849 c=0 +rg152 (\7\:net21 \8\:net21) resistor r=189.671 c=0 +rg153 (\8\:net21 \9\:net21) resistor r=180.126 c=0 +rg154 (\4\:net21 \10\:net21) resistor r=158.125 c=0 +rg155 (\6\:net21 \3\:net21) resistor r=3.4479 c=0 +rg156 (\4\:net15 \5\:net15) resistor r=181.923 c=0 +rg157 (\5\:net15 \6\:net15) resistor r=107.843 c=0 +rg158 (\6\:net15 \7\:net15) resistor r=48.8849 c=0 +rg159 (\7\:net15 \8\:net15) resistor r=189.671 c=0 +rg160 (\8\:net15 \9\:net15) resistor r=180.126 c=0 +rg161 (\4\:net15 \10\:net15) resistor r=158.125 c=0 +rg162 (\6\:net15 \3\:net15) resistor r=3.4479 c=0 +rg163 (\9\:Y1 \10\:Y1) resistor r=62.0099 c=0 +rg165 (\10\:Y1 \11\:Y1) resistor r=91.5933 c=0 +rg166 (\11\:Y1 \12\:Y1) resistor r=135.03 c=0 +rg167 (I4\|I3\|Bi \2\:I4\|I3\|Bi) resistor r=271.714 c=0 +rg168 (\2\:I4\|I3\|Bi \3\:I4\|I3\|Bi) resistor r=140.208 c=0 +rg169 (I9\|I3\|Bi \2\:I9\|I3\|Bi) resistor r=271.714 c=0 +rg170 (\2\:I9\|I3\|Bi \3\:I9\|I3\|Bi) resistor r=140.208 c=0 +rg171 (\1\:X2 \2\:X2) resistor r=3.7604 c=0 +rg172 (\2\:X2 \3\:X2) resistor r=62.0099 c=0 +rg173 (\2\:X2 \4\:X2) resistor r=91.5933 c=0 +rg174 (\8\:Y3 \9\:Y3) resistor r=91.5933 c=0 +rg175 (\9\:Y3 \7\:Y3) resistor r=3.7604 c=0 +rg176 (\9\:Y3 \10\:Y3) resistor r=62.0099 c=0 +rg177 (\8\:Y2 \9\:Y2) resistor r=91.5933 c=0 +rg178 (\9\:Y2 \7\:Y2) resistor r=3.7604 c=0 +rg179 (\9\:Y2 \10\:Y2) resistor r=62.0099 c=0 +rg180 (\7\:X2 \8\:X2) resistor r=3.7604 c=0 +rg181 (\8\:X2 \9\:X2) resistor r=62.0099 c=0 +rg182 (\8\:X2 \10\:X2) resistor r=91.5933 c=0 +rg183 (\13\:X2 \16\:X2) resistor r=3.7604 c=0 +rg184 (\16\:X2 \17\:X2) resistor r=62.0099 c=0 +rg185 (\16\:X2 \18\:X2) resistor r=91.5933 c=0 +rg186 (\5\:I18\|net013 \6\:I18\|net013) resistor r=37.6755 c=0 +rg187 (\6\:I18\|net013 I18\|net013) resistor r=19.7812 c=0 +rg188 (\6\:I18\|net013 \7\:I18\|net013) resistor r=115.592 c=0 +rg189 (\6\:net38 \7\:net38) resistor r=132.954 c=0 +rg190 (\7\:net38 \8\:net38) resistor r=83.7878 c=0 +rg191 (\7\:net38 net38) resistor r=15.5249 c=0 +rg192 (\5\:I26\|net013 \6\:I26\|net013) resistor r=37.6755 c=0 +rg193 (\6\:I26\|net013 I26\|net013) resistor r=19.7812 c=0 +rg194 (\6\:I26\|net013 \7\:I26\|net013) resistor r=115.592 c=0 +rg195 (\5\:I21\|net013 \6\:I21\|net013) resistor r=37.6755 c=0 +rg196 (\6\:I21\|net013 I21\|net013) resistor r=19.7812 c=0 +rg197 (\6\:I21\|net013 \7\:I21\|net013) resistor r=115.592 c=0 +rg198 (I0\|I4\|Bi \2\:I0\|I4\|Bi) resistor r=3.4479 c=0 +rg199 (\2\:I0\|I4\|Bi \3\:I0\|I4\|Bi) resistor r=70.5516 c=0 +rg200 (\2\:I0\|I4\|Bi \4\:I0\|I4\|Bi) resistor r=68.2599 c=0 +rg201 (\4\:I0\|I4\|Ai \5\:I0\|I4\|Ai) resistor r=426.762 c=0 +rg202 (\5\:I0\|I4\|Ai \3\:I0\|I4\|Ai) resistor r=295.399 c=0 +rg203 (\6\:net8 \7\:net8) resistor r=132.954 c=0 +rg204 (\7\:net8 \8\:net8) resistor r=83.7878 c=0 +rg205 (\7\:net8 \4\:net8) resistor r=15.5249 c=0 +rg206 (\6\:net087 \7\:net087) resistor r=132.954 c=0 +rg207 (\7\:net087 \8\:net087) resistor r=83.7878 c=0 +rg208 (\7\:net087 \4\:net087) resistor r=15.5249 c=0 +rg209 (\13\:net38 \14\:net38) resistor r=68.6766 c=0 +rg210 (\14\:net38 \15\:net38) resistor r=39.0198 c=0 +rg211 (\15\:net38 \9\:net38) resistor r=3.7604 c=0 +rg212 (\9\:net38 \16\:net38) resistor r=42.4747 c=0 +rg213 (\16\:net38 \17\:net38) resistor r=51.4263 c=0 +rg214 (\14\:net38 \12\:net38) resistor r=3.6562 c=0 +rg215 (\15\:net38 \18\:net38) resistor r=47.6349 c=0 +rg216 (\16\:net38 \19\:net38) resistor r=106.01 c=0 +rg217 (I10\|I4\|Bi \2\:I10\|I4\|Bi) resistor r=3.4479 c=0 +rg218 (\2\:I10\|I4\|Bi \3\:I10\|I4\|Bi) resistor r=70.5516 c=0 +rg219 (\2\:I10\|I4\|Bi \4\:I10\|I4\|Bi) resistor r=68.2599 c=0 +rg220 (I10\|I4\|Ai \2\:I10\|I4\|Ai) resistor r=426.762 c=0 +rg221 (\2\:I10\|I4\|Ai \3\:I10\|I4\|Ai) resistor r=295.399 c=0 +rg222 (I3\|I4\|Bi \2\:I3\|I4\|Bi) resistor r=3.4479 c=0 +rg223 (\2\:I3\|I4\|Bi \3\:I3\|I4\|Bi) resistor r=70.5516 c=0 +rg224 (\2\:I3\|I4\|Bi \4\:I3\|I4\|Bi) resistor r=68.2599 c=0 +rg225 (\4\:I3\|I4\|Ai \5\:I3\|I4\|Ai) resistor r=426.762 c=0 +rg226 (\5\:I3\|I4\|Ai \3\:I3\|I4\|Ai) resistor r=295.399 c=0 +rg227 (\4\:net39 \5\:net39) resistor r=3.7604 c=0 +rg228 (\5\:net39 \6\:net39) resistor r=47.6349 c=0 +rg229 (\6\:net39 \7\:net39) resistor r=149.112 c=0 +rg230 (\7\:net39 \8\:net39) resistor r=237.862 c=0 +rg231 (\8\:net39 \9\:net39) resistor r=167.131 c=0 +rg232 (\5\:net39 \10\:net39) resistor r=109.093 c=0 +rg233 (\7\:net39 \11\:net39) resistor r=54.2235 c=0 +rg234 (\11\:net39 \12\:net39) resistor r=140.208 c=0 +rg235 (\13\:net8 \14\:net8) resistor r=68.6766 c=0 +rg236 (\14\:net8 \15\:net8) resistor r=39.0198 c=0 +rg237 (\15\:net8 \10\:net8) resistor r=3.7604 c=0 +rg238 (\10\:net8 \16\:net8) resistor r=42.4747 c=0 +rg239 (\16\:net8 \17\:net8) resistor r=51.4263 c=0 +rg240 (\14\:net8 \12\:net8) resistor r=3.6562 c=0 +rg241 (\15\:net8 \18\:net8) resistor r=47.6349 c=0 +rg242 (\16\:net8 \19\:net8) resistor r=106.01 c=0 +rg243 (\13\:net087 \14\:net087) resistor r=68.6766 c=0 +rg244 (\14\:net087 \15\:net087) resistor r=39.0198 c=0 +rg245 (\15\:net087 \9\:net087) resistor r=3.7604 c=0 +rg246 (\9\:net087 \16\:net087) resistor r=42.4747 c=0 +rg247 (\16\:net087 \17\:net087) resistor r=51.4263 c=0 +rg248 (\14\:net087 \12\:net087) resistor r=3.6562 c=0 +rg249 (\15\:net087 \18\:net087) resistor r=47.6349 c=0 +rg250 (\16\:net087 \19\:net087) resistor r=106.01 c=0 +rg251 (\10\:I0\|net3 \11\:I0\|net3) resistor r=97.8433 c=0 +rg252 (\11\:I0\|net3 \9\:I0\|net3) resistor r=3.7604 c=0 +rg253 (\11\:I0\|net3 \12\:I0\|net3) resistor r=40.9683 c=0 +rg254 (\5\:I0\|net1 \6\:I0\|net1) resistor r=80.5516 c=0 +rg255 (\6\:I0\|net1 \4\:I0\|net1) resistor r=3.5521 c=0 +rg256 (\6\:I0\|net1 \7\:I0\|net1) resistor r=76.1766 c=0 +rg257 (\10\:net17 \11\:net17) resistor r=3.7604 c=0 +rg258 (\11\:net17 \12\:net17) resistor r=47.6349 c=0 +rg259 (\12\:net17 \13\:net17) resistor r=149.112 c=0 +rg260 (\13\:net17 \14\:net17) resistor r=237.862 c=0 +rg261 (\14\:net17 \15\:net17) resistor r=167.131 c=0 +rg262 (\11\:net17 \16\:net17) resistor r=109.093 c=0 +rg263 (\13\:net17 \17\:net17) resistor r=54.2235 c=0 +rg264 (\17\:net17 \18\:net17) resistor r=140.208 c=0 +rg265 (\10\:net54 \11\:net54) resistor r=3.7604 c=0 +rg266 (\11\:net54 \12\:net54) resistor r=47.6349 c=0 +rg267 (\12\:net54 \13\:net54) resistor r=149.112 c=0 +rg268 (\13\:net54 \14\:net54) resistor r=237.862 c=0 +rg269 (\14\:net54 \15\:net54) resistor r=167.131 c=0 +rg270 (\11\:net54 \16\:net54) resistor r=109.093 c=0 +rg271 (\13\:net54 \17\:net54) resistor r=54.2235 c=0 +rg272 (\17\:net54 \18\:net54) resistor r=140.208 c=0 +rg273 (\10\:I10\|net3 \11\:I10\|net3) resistor r=97.8433 c=0 +rg274 (\11\:I10\|net3 \9\:I10\|net3) resistor r=3.7604 c=0 +rg275 (\11\:I10\|net3 \12\:I10\|net3) resistor r=40.9683 c=0 +rg276 (I0\|net6 \2\:I0\|net6) resistor r=3.5521 c=0 +rg277 (\2\:I0\|net6 \3\:I0\|net6) resistor r=77.0099 c=0 +rg278 (\2\:I0\|net6 \4\:I0\|net6) resistor r=79.7183 c=0 +rg279 (\10\:I3\|net3 \11\:I3\|net3) resistor r=97.8433 c=0 +rg280 (\11\:I3\|net3 \9\:I3\|net3) resistor r=3.7604 c=0 +rg281 (\11\:I3\|net3 \12\:I3\|net3) resistor r=40.9683 c=0 +rg282 (\5\:I10\|net1 \6\:I10\|net1) resistor r=80.5516 c=0 +rg283 (\6\:I10\|net1 \4\:I10\|net1) resistor r=3.5521 c=0 +rg284 (\6\:I10\|net1 \7\:I10\|net1) resistor r=76.1766 c=0 +rg285 (\5\:I3\|net1 \6\:I3\|net1) resistor r=80.5516 c=0 +rg286 (\6\:I3\|net1 \4\:I3\|net1) resistor r=3.5521 c=0 +rg287 (\6\:I3\|net1 \7\:I3\|net1) resistor r=76.1766 c=0 +rg288 (I10\|net6 \2\:I10\|net6) resistor r=3.5521 c=0 +rg289 (\2\:I10\|net6 \3\:I10\|net6) resistor r=77.0099 c=0 +rg290 (\2\:I10\|net6 \4\:I10\|net6) resistor r=79.7183 c=0 +rg291 (I3\|net6 \2\:I3\|net6) resistor r=3.5521 c=0 +rg292 (\2\:I3\|net6 \3\:I3\|net6) resistor r=77.0099 c=0 +rg293 (\2\:I3\|net6 \4\:I3\|net6) resistor r=79.7183 c=0 +rg294 (\16\:I0\|net3 \17\:I0\|net3) resistor r=158.125 c=0 +rg295 (\17\:I0\|net3 \18\:I0\|net3) resistor r=211.449 c=0 +rg296 (\18\:I0\|net3 \19\:I0\|net3) resistor r=168.536 c=0 +rg297 (\19\:I0\|net3 \13\:I0\|net3) resistor r=6.3083 c=0 +rg298 (\19\:I0\|net3 \20\:I0\|net3) resistor r=38.7601 c=0 +rg299 (\5\:I0\|I3\|Ai I0\|I3\|Ai) resistor r=317.339 c=0 +rg300 (I0\|I3\|Ai \6\:I0\|I3\|Ai) resistor r=91.8988 c=0 +rg301 (\3\:net31 \4\:net31) resistor r=181.923 c=0 +rg302 (\4\:net31 \5\:net31) resistor r=107.843 c=0 +rg303 (\5\:net31 \6\:net31) resistor r=48.8849 c=0 +rg304 (\6\:net31 \7\:net31) resistor r=189.671 c=0 +rg305 (\7\:net31 \8\:net31) resistor r=180.126 c=0 +rg306 (\3\:net31 \9\:net31) resistor r=158.125 c=0 +rg307 (\5\:net31 net31) resistor r=3.4479 c=0 +rg308 (\16\:I10\|net3 \17\:I10\|net3) resistor r=158.125 c=0 +rg309 (\17\:I10\|net3 \18\:I10\|net3) resistor r=211.449 c=0 +rg310 (\18\:I10\|net3 \19\:I10\|net3) resistor r=168.536 c=0 +rg311 (\19\:I10\|net3 \15\:I10\|net3) resistor r=6.3083 c=0 +rg312 (\19\:I10\|net3 \20\:I10\|net3) resistor r=38.7601 c=0 +rg313 (\5\:I10\|I3\|Ai I10\|I3\|Ai) resistor r=317.339 c=0 +rg314 (I10\|I3\|Ai \6\:I10\|I3\|Ai) resistor r=91.8988 c=0 +rg315 (I0\|I3\|Bi \5\:I0\|I3\|Bi) resistor r=271.714 c=0 +rg316 (\5\:I0\|I3\|Bi \6\:I0\|I3\|Bi) resistor r=140.208 c=0 +rg317 (\16\:I3\|net3 \17\:I3\|net3) resistor r=158.125 c=0 +rg318 (\17\:I3\|net3 \18\:I3\|net3) resistor r=211.449 c=0 +rg319 (\18\:I3\|net3 \19\:I3\|net3) resistor r=168.536 c=0 +rg320 (\19\:I3\|net3 \13\:I3\|net3) resistor r=6.3083 c=0 +rg321 (\19\:I3\|net3 \20\:I3\|net3) resistor r=38.7601 c=0 +rg322 (\5\:I3\|I3\|Ai I3\|I3\|Ai) resistor r=317.339 c=0 +rg323 (I3\|I3\|Ai \6\:I3\|I3\|Ai) resistor r=91.8988 c=0 +rg324 (\3\:net1 \4\:net1) resistor r=181.923 c=0 +rg325 (\4\:net1 \5\:net1) resistor r=107.843 c=0 +rg326 (\5\:net1 \6\:net1) resistor r=48.8849 c=0 +rg327 (\6\:net1 \7\:net1) resistor r=189.671 c=0 +rg328 (\7\:net1 \8\:net1) resistor r=180.126 c=0 +rg329 (\3\:net1 \9\:net1) resistor r=158.125 c=0 +rg330 (\5\:net1 net1) resistor r=3.4479 c=0 +rg331 (\3\:net26 \4\:net26) resistor r=181.923 c=0 +rg332 (\4\:net26 \5\:net26) resistor r=107.843 c=0 +rg333 (\5\:net26 \6\:net26) resistor r=48.8849 c=0 +rg334 (\6\:net26 \7\:net26) resistor r=189.671 c=0 +rg335 (\7\:net26 \8\:net26) resistor r=180.126 c=0 +rg336 (\3\:net26 \9\:net26) resistor r=158.125 c=0 +rg337 (\5\:net26 net26) resistor r=3.4479 c=0 +rg338 (I10\|I3\|Bi \2\:I10\|I3\|Bi) resistor r=271.714 c=0 +rg339 (\2\:I10\|I3\|Bi \3\:I10\|I3\|Bi) resistor r=140.208 c=0 +rg340 (\5\:I1\|I3\|Bi \3\:I1\|I3\|Bi) resistor r=271.714 c=0 +rg341 (\5\:I1\|I3\|Bi \6\:I1\|I3\|Bi) resistor r=140.208 c=0 +rg342 (I3\|I3\|Bi \2\:I3\|I3\|Bi) resistor r=271.714 c=0 +rg343 (\2\:I3\|I3\|Bi \3\:I3\|I3\|Bi) resistor r=140.208 c=0 +rg344 (\5\:I11\|I3\|Bi \3\:I11\|I3\|Bi) resistor r=271.714 c=0 +rg345 (\5\:I11\|I3\|Bi \6\:I11\|I3\|Bi) resistor r=140.208 c=0 +rg346 (I1\|net3 \2\:I1\|net3) resistor r=38.7601 c=0 +rg347 (\2\:I1\|net3 \3\:I1\|net3) resistor r=168.536 c=0 +rg348 (\2\:I1\|net3 \4\:I1\|net3) resistor r=6.3083 c=0 +rg349 (\3\:I1\|net3 \5\:I1\|net3) resistor r=211.449 c=0 +rg350 (\5\:I1\|net3 \6\:I1\|net3) resistor r=158.125 c=0 +rg351 (\5\:I2\|I3\|Bi \3\:I2\|I3\|Bi) resistor r=271.714 c=0 +rg352 (\5\:I2\|I3\|Bi \6\:I2\|I3\|Bi) resistor r=140.208 c=0 +rg353 (\3\:net35 \4\:net35) resistor r=180.126 c=0 +rg354 (\4\:net35 \5\:net35) resistor r=193.622 c=0 +rg355 (\5\:net35 \6\:net35) resistor r=48.8849 c=0 +rg356 (\6\:net35 \7\:net35) resistor r=107.843 c=0 +rg357 (\7\:net35 \8\:net35) resistor r=181.923 c=0 +rg358 (\8\:net35 \9\:net35) resistor r=158.125 c=0 +rg359 (\6\:net35 net35) resistor r=3.4479 c=0 +rg360 (\5\:I1\|net6 \6\:I1\|net6) resistor r=79.7183 c=0 +rg361 (\6\:I1\|net6 \4\:I1\|net6) resistor r=3.5521 c=0 +rg362 (\6\:I1\|net6 \7\:I1\|net6) resistor r=77.0099 c=0 +rg363 (I1\|I3\|Ai \2\:I1\|I3\|Ai) resistor r=91.8988 c=0 +rg364 (\2\:I1\|I3\|Ai \3\:I1\|I3\|Ai) resistor r=317.339 c=0 +rg365 (I1\|net1 \2\:I1\|net1) resistor r=3.5521 c=0 +rg366 (\2\:I1\|net1 \3\:I1\|net1) resistor r=76.1766 c=0 +rg367 (\2\:I1\|net1 \4\:I1\|net1) resistor r=80.5516 c=0 +rg368 (I11\|net3 \2\:I11\|net3) resistor r=38.7601 c=0 +rg369 (\2\:I11\|net3 \3\:I11\|net3) resistor r=168.536 c=0 +rg370 (\2\:I11\|net3 \4\:I11\|net3) resistor r=6.3083 c=0 +rg371 (\3\:I11\|net3 \5\:I11\|net3) resistor r=211.449 c=0 +rg372 (\5\:I11\|net3 \6\:I11\|net3) resistor r=158.125 c=0 +rg373 (\8\:I1\|net3 \9\:I1\|net3) resistor r=3.7604 c=0 +rg374 (\9\:I1\|net3 \10\:I1\|net3) resistor r=40.9683 c=0 +rg375 (\9\:I1\|net3 \11\:I1\|net3) resistor r=97.8433 c=0 +rg376 (\4\:net5 \5\:net5) resistor r=180.126 c=0 +rg377 (\5\:net5 \6\:net5) resistor r=193.622 c=0 +rg378 (\6\:net5 \7\:net5) resistor r=48.8849 c=0 +rg379 (\7\:net5 \8\:net5) resistor r=107.843 c=0 +rg380 (\8\:net5 \9\:net5) resistor r=181.923 c=0 +rg381 (\9\:net5 \10\:net5) resistor r=158.125 c=0 +rg382 (\7\:net5 net5) resistor r=3.4479 c=0 +rg383 (I2\|net3 \2\:I2\|net3) resistor r=38.7601 c=0 +rg384 (\2\:I2\|net3 \3\:I2\|net3) resistor r=168.536 c=0 +rg385 (\2\:I2\|net3 \4\:I2\|net3) resistor r=6.3083 c=0 +rg386 (\3\:I2\|net3 \5\:I2\|net3) resistor r=211.449 c=0 +rg387 (\5\:I2\|net3 \6\:I2\|net3) resistor r=158.125 c=0 +rg388 (\5\:I11\|net6 \6\:I11\|net6) resistor r=79.7183 c=0 +rg389 (\6\:I11\|net6 \4\:I11\|net6) resistor r=3.5521 c=0 +rg390 (\6\:I11\|net6 \7\:I11\|net6) resistor r=77.0099 c=0 +rg391 (\3\:net45 \4\:net45) resistor r=180.126 c=0 +rg392 (\4\:net45 \5\:net45) resistor r=193.622 c=0 +rg393 (\5\:net45 \6\:net45) resistor r=48.8849 c=0 +rg394 (\6\:net45 \7\:net45) resistor r=107.843 c=0 +rg395 (\7\:net45 \8\:net45) resistor r=181.923 c=0 +rg396 (\8\:net45 \9\:net45) resistor r=158.125 c=0 +rg397 (\6\:net45 net45) resistor r=3.4479 c=0 +rg398 (I11\|I3\|Ai \2\:I11\|I3\|Ai) resistor r=91.8988 c=0 +rg399 (\2\:I11\|I3\|Ai \3\:I11\|I3\|Ai) resistor r=317.339 c=0 +rg400 (\5\:I2\|net6 \6\:I2\|net6) resistor r=79.7183 c=0 +rg401 (\6\:I2\|net6 \4\:I2\|net6) resistor r=3.5521 c=0 +rg402 (\6\:I2\|net6 \7\:I2\|net6) resistor r=77.0099 c=0 +rg403 (I11\|net1 \2\:I11\|net1) resistor r=3.5521 c=0 +rg404 (\2\:I11\|net1 \3\:I11\|net1) resistor r=76.1766 c=0 +rg405 (\2\:I11\|net1 \4\:I11\|net1) resistor r=80.5516 c=0 +rg406 (I2\|I3\|Ai \2\:I2\|I3\|Ai) resistor r=91.8988 c=0 +rg407 (\2\:I2\|I3\|Ai \3\:I2\|I3\|Ai) resistor r=317.339 c=0 +rg408 (\8\:I11\|net3 \9\:I11\|net3) resistor r=3.7604 c=0 +rg409 (\9\:I11\|net3 \10\:I11\|net3) resistor r=40.9683 c=0 +rg410 (\9\:I11\|net3 \11\:I11\|net3) resistor r=97.8433 c=0 +rg411 (I2\|net1 \2\:I2\|net1) resistor r=3.5521 c=0 +rg412 (\2\:I2\|net1 \3\:I2\|net1) resistor r=76.1766 c=0 +rg413 (\2\:I2\|net1 \4\:I2\|net1) resistor r=80.5516 c=0 +rg414 (\5\:I1\|I4\|Ai \6\:I1\|I4\|Ai) resistor r=68.2599 c=0 +rg415 (\6\:I1\|I4\|Ai \4\:I1\|I4\|Ai) resistor r=3.4479 c=0 +rg416 (\6\:I1\|I4\|Ai \7\:I1\|I4\|Ai) resistor r=70.5516 c=0 +rg417 (\8\:I2\|net3 \10\:I2\|net3) resistor r=3.7604 c=0 +rg418 (\10\:I2\|net3 \11\:I2\|net3) resistor r=40.9683 c=0 +rg419 (\10\:I2\|net3 \12\:I2\|net3) resistor r=97.8433 c=0 +rg420 (\5\:net34 \6\:net34) resistor r=106.125 c=0 +rg421 (\6\:net34 \4\:net34) resistor r=42.5281 c=0 +rg422 (\4\:net34 \7\:net34) resistor r=3.7604 c=0 +rg423 (\7\:net34 \8\:net34) resistor r=47.6349 c=0 +rg424 (\6\:net34 \9\:net34) resistor r=51.3337 c=0 +rg425 (\7\:net34 \10\:net34) resistor r=39.0198 c=0 +rg426 (\10\:net34 \11\:net34) resistor r=68.6766 c=0 +rg427 (\10\:net34 net34) resistor r=3.6562 c=0 +rg428 (\22\:X2 \23\:X2) resistor r=91.5933 c=0 +rg429 (\23\:X2 \20\:X2) resistor r=3.7604 c=0 +rg430 (\23\:X2 \24\:X2) resistor r=62.0099 c=0 +rg431 (\5\:I11\|I4\|Bi \6\:I11\|I4\|Bi) resistor r=68.2599 c=0 +rg432 (\6\:I11\|I4\|Bi \4\:I11\|I4\|Bi) resistor r=3.4479 c=0 +rg433 (\6\:I11\|I4\|Bi \7\:I11\|I4\|Bi) resistor r=70.5516 c=0 +rg434 (\5\:net078 \6\:net078) resistor r=106.125 c=0 +rg435 (\6\:net078 \4\:net078) resistor r=42.5281 c=0 +rg436 (\4\:net078 \7\:net078) resistor r=3.7604 c=0 +rg437 (\7\:net078 \8\:net078) resistor r=47.6349 c=0 +rg438 (\6\:net078 \9\:net078) resistor r=51.3337 c=0 +rg439 (\7\:net078 \10\:net078) resistor r=39.0198 c=0 +rg440 (\10\:net078 \11\:net078) resistor r=68.6766 c=0 +rg441 (\10\:net078 net078) resistor r=3.6562 c=0 +rg442 (\14\:net34 \15\:net34) resistor r=83.7878 c=0 +rg443 (\15\:net34 \16\:net34) resistor r=132.954 c=0 +rg444 (\15\:net34 \12\:net34) resistor r=15.5249 c=0 +rg445 (\5\:I2\|I4\|Bi \6\:I2\|I4\|Bi) resistor r=68.2599 c=0 +rg446 (\6\:I2\|I4\|Bi \4\:I2\|I4\|Bi) resistor r=3.4479 c=0 +rg447 (\6\:I2\|I4\|Bi \7\:I2\|I4\|Bi) resistor r=70.5516 c=0 +rg448 (\5\:net28 \6\:net28) resistor r=106.125 c=0 +rg449 (\6\:net28 \4\:net28) resistor r=42.5281 c=0 +rg450 (\4\:net28 \7\:net28) resistor r=3.7604 c=0 +rg451 (\7\:net28 \8\:net28) resistor r=47.6349 c=0 +rg452 (\6\:net28 \9\:net28) resistor r=51.3337 c=0 +rg453 (\7\:net28 \10\:net28) resistor r=39.0198 c=0 +rg454 (\10\:net28 \11\:net28) resistor r=68.6766 c=0 +rg455 (\10\:net28 net28) resistor r=3.6562 c=0 +rg456 (\3\:net095 \4\:net095) resistor r=167.131 c=0 +rg457 (\4\:net095 \5\:net095) resistor r=237.862 c=0 +rg458 (\5\:net095 \6\:net095) resistor r=149.112 c=0 +rg459 (\6\:net095 \7\:net095) resistor r=47.6349 c=0 +rg460 (\7\:net095 net095) resistor r=3.7604 c=0 +rg461 (\5\:net095 \8\:net095) resistor r=54.2235 c=0 +rg462 (\8\:net095 \9\:net095) resistor r=140.208 c=0 +rg463 (\7\:net095 \10\:net095) resistor r=109.093 c=0 +rg464 (\4\:I1\|I4\|Bi \5\:I1\|I4\|Bi) resistor r=426.762 c=0 +rg465 (\5\:I1\|I4\|Bi \3\:I1\|I4\|Bi) resistor r=295.399 c=0 +rg466 (\5\:I13\|net013 \6\:I13\|net013) resistor r=37.6755 c=0 +rg467 (\6\:I13\|net013 I13\|net013) resistor r=19.7812 c=0 +rg468 (\6\:I13\|net013 \7\:I13\|net013) resistor r=115.592 c=0 +rg469 (\17\:net078 \18\:net078) resistor r=83.7878 c=0 +rg470 (\18\:net078 \19\:net078) resistor r=132.954 c=0 +rg471 (\18\:net078 \12\:net078) resistor r=15.5249 c=0 +rg472 (\17\:net28 \18\:net28) resistor r=83.7878 c=0 +rg473 (\18\:net28 \19\:net28) resistor r=132.954 c=0 +rg474 (\18\:net28 \12\:net28) resistor r=15.5249 c=0 +rg475 (\12\:net0100 \13\:net0100) resistor r=167.131 c=0 +rg476 (\13\:net0100 \14\:net0100) resistor r=237.862 c=0 +rg477 (\14\:net0100 \15\:net0100) resistor r=149.112 c=0 +rg478 (\15\:net0100 \16\:net0100) resistor r=47.6349 c=0 +rg479 (\16\:net0100 \9\:net0100) resistor r=3.7604 c=0 +rg480 (\14\:net0100 \17\:net0100) resistor r=54.2235 c=0 +rg481 (\17\:net0100 \18\:net0100) resistor r=140.208 c=0 +rg482 (\16\:net0100 \19\:net0100) resistor r=109.093 c=0 +rg483 (net0115 \2\:net0115) resistor r=81.8016 c=0 +rg484 (\2\:net0115 \3\:net0115) resistor r=3.7604 c=0 +rg485 (\2\:net0115 \4\:net0115) resistor r=55.3433 c=0 +rg486 (\4\:X1 \5\:X1) resistor r=91.5933 c=0 +rg487 (\5\:X1 \2\:X1) resistor r=3.7604 c=0 +rg488 (\5\:X1 \6\:X1) resistor r=62.0099 c=0 +rg489 (\12\:net29 \13\:net29) resistor r=167.131 c=0 +rg490 (\13\:net29 \14\:net29) resistor r=237.862 c=0 +rg491 (\14\:net29 \15\:net29) resistor r=149.112 c=0 +rg492 (\15\:net29 \16\:net29) resistor r=47.6349 c=0 +rg493 (\16\:net29 \9\:net29) resistor r=3.7604 c=0 +rg494 (\14\:net29 \17\:net29) resistor r=54.2235 c=0 +rg495 (\17\:net29 \18\:net29) resistor r=140.208 c=0 +rg496 (\16\:net29 \19\:net29) resistor r=109.093 c=0 +rg497 (\4\:I11\|I4\|Ai \5\:I11\|I4\|Ai) resistor r=426.762 c=0 +rg498 (\5\:I11\|I4\|Ai \3\:I11\|I4\|Ai) resistor r=295.399 c=0 +rg499 (I24\|net013 \2\:I24\|net013) resistor r=19.7812 c=0 +rg500 (\2\:I24\|net013 \3\:I24\|net013) resistor r=115.592 c=0 +rg501 (\2\:I24\|net013 \4\:I24\|net013) resistor r=37.6755 c=0 +rg502 (I23\|net013 \2\:I23\|net013) resistor r=19.7812 c=0 +rg503 (\2\:I23\|net013 \3\:I23\|net013) resistor r=115.592 c=0 +rg504 (\2\:I23\|net013 \4\:I23\|net013) resistor r=37.6755 c=0 +rg505 (\10\:X1 \11\:X1) resistor r=91.5933 c=0 +rg506 (\11\:X1 \7\:X1) resistor r=3.7604 c=0 +rg507 (\11\:X1 \12\:X1) resistor r=62.0099 c=0 +rg508 (\4\:I2\|I4\|Ai \5\:I2\|I4\|Ai) resistor r=426.762 c=0 +rg509 (\5\:I2\|I4\|Ai \3\:I2\|I4\|Ai) resistor r=295.399 c=0 +rg510 (\15\:X1 \16\:X1) resistor r=91.5933 c=0 +rg511 (\16\:X1 \13\:X1) resistor r=3.7604 c=0 +rg512 (\16\:X1 \17\:X1) resistor r=62.0099 c=0 +rg514 (\15\:Y1 \16\:Y1) resistor r=62.0099 c=0 +rg515 (\15\:Y1 \17\:Y1) resistor r=91.5933 c=0 +rg516 (\17\:Y1 \18\:Y1) resistor r=135.482 c=0 +rg517 (\11\:Y3 \12\:Y3) resistor r=3.7604 c=0 +rg518 (\12\:Y3 \13\:Y3) resistor r=62.0099 c=0 +rg519 (\12\:Y3 \14\:Y3) resistor r=91.5933 c=0 +rg520 (\11\:Y2 \12\:Y2) resistor r=3.7604 c=0 +rg521 (\12\:Y2 \13\:Y2) resistor r=62.0099 c=0 +rg522 (\12\:Y2 \14\:Y2) resistor r=91.5933 c=0 +rg523 (\5\:I16\|net013 \6\:I16\|net013) resistor r=37.6755 c=0 +rg524 (\6\:I16\|net013 I16\|net013) resistor r=19.7812 c=0 +rg525 (\6\:I16\|net013 \7\:I16\|net013) resistor r=115.592 c=0 +rg526 (\12\:net0115 \13\:net0115) resistor r=79.5099 c=0 +rg527 (\13\:net0115 \14\:net0115) resistor r=73.0516 c=0 +rg528 (\14\:net0115 \8\:net0115) resistor r=77.3221 c=0 +rg529 (\13\:net0115 \15\:net0115) resistor r=3.7604 c=0 +rg530 (\16\:net0115 \17\:net0115) resistor r=41.6577 c=0 +rg531 (\17\:net0115 \18\:net0115) resistor r=120.434 c=0 +rg532 (\18\:net0115 \7\:net0115) resistor r=7.4762 c=0 +rg533 (\17\:net0115 \11\:net0115) resistor r=32.1097 c=0 +rg534 (\18\:net0115 \19\:net0115) resistor r=47.3355 c=0 +rg535 (\5\:I6\|I1\|Ai I6\|I1\|Ai) resistor r=333.423 c=0 +rg536 (I6\|I1\|Ai \6\:I6\|I1\|Ai) resistor r=76.0655 c=0 +rg537 (I8\|I3\|net013 \2\:I8\|I3\|net013) resistor r=3.7604 c=0 +rg538 (\2\:I8\|I3\|net013 \3\:I8\|I3\|net013) resistor r=109.302 c=0 +rg539 (\2\:I8\|I3\|net013 \4\:I8\|I3\|net013) resistor r=43.2599 c=0 +rg540 (I7\|I3\|net013 \2\:I7\|I3\|net013) resistor r=3.7604 c=0 +rg541 (\2\:I7\|I3\|net013 \3\:I7\|I3\|net013) resistor r=109.302 c=0 +rg542 (\2\:I7\|I3\|net013 \4\:I7\|I3\|net013) resistor r=43.2599 c=0 +rg543 (I6\|I1\|Bi \2\:I6\|I1\|Bi) resistor r=3.6562 c=0 +rg544 (\2\:I6\|I1\|Bi \3\:I6\|I1\|Bi) resistor r=84.0933 c=0 +rg545 (\2\:I6\|I1\|Bi \4\:I6\|I1\|Bi) resistor r=53.0516 c=0 +rg546 (\5\:I8\|I1\|Bi \6\:I8\|I1\|Bi) resistor r=53.0516 c=0 +rg547 (\6\:I8\|I1\|Bi \4\:I8\|I1\|Bi) resistor r=3.6562 c=0 +rg548 (\6\:I8\|I1\|Bi \7\:I8\|I1\|Bi) resistor r=84.0933 c=0 +rg549 (\5\:I7\|I1\|Bi \6\:I7\|I1\|Bi) resistor r=53.0516 c=0 +rg550 (\6\:I7\|I1\|Bi \4\:I7\|I1\|Bi) resistor r=3.6562 c=0 +rg551 (\6\:I7\|I1\|Bi \7\:I7\|I1\|Bi) resistor r=84.0933 c=0 +rg552 (I6\|I3\|net013 \2\:I6\|I3\|net013) resistor r=43.2599 c=0 +rg553 (\2\:I6\|I3\|net013 \3\:I6\|I3\|net013) resistor r=3.7604 c=0 +rg554 (\2\:I6\|I3\|net013 \4\:I6\|I3\|net013) resistor r=109.302 c=0 +rg555 (\3\:net0127 \4\:net0127) resistor r=116.403 c=0 +rg556 (\4\:net0127 \5\:net0127) resistor r=165.153 c=0 +rg557 (\5\:net0127 \6\:net0127) resistor r=174.262 c=0 +rg558 (\3\:net0127 \7\:net0127) resistor r=138.542 c=0 +rg559 (\4\:net0127 \8\:net0127) resistor r=135.474 c=0 +rg560 (\8\:net0127 \9\:net0127) resistor r=72.4266 c=0 +rg561 (\9\:net0127 \10\:net0127) resistor r=80.1349 c=0 +rg562 (\9\:net0127 \2\:net0127) resistor r=3.7604 c=0 +rg563 (\2\:net075 \7\:net075) resistor r=3.7604 c=0 +rg564 (\7\:net075 \8\:net075) resistor r=73.0516 c=0 +rg565 (\7\:net075 \9\:net075) resistor r=79.5099 c=0 +rg566 (\8\:net075 \5\:net075) resistor r=77.3221 c=0 +rg567 (\2\:net47 \7\:net47) resistor r=3.7604 c=0 +rg568 (\7\:net47 \8\:net47) resistor r=73.0516 c=0 +rg569 (\7\:net47 \9\:net47) resistor r=79.5099 c=0 +rg570 (\8\:net47 \5\:net47) resistor r=77.3221 c=0 +rg571 (\19\:X1 \20\:X1) resistor r=91.5933 c=0 +rg572 (\20\:X1 \21\:X1) resistor r=3.7604 c=0 +rg573 (\20\:X1 \22\:X1) resistor r=62.0099 c=0 +rg574 (\13\:net075 \14\:net075) resistor r=47.3355 c=0 +rg575 (\14\:net075 \15\:net075) resistor r=120.434 c=0 +rg576 (\15\:net075 \16\:net075) resistor r=41.6577 c=0 +rg577 (\14\:net075 \17\:net075) resistor r=7.4762 c=0 +rg578 (\15\:net075 \3\:net075) resistor r=32.1097 c=0 +rg579 (\13\:net47 \14\:net47) resistor r=47.3355 c=0 +rg580 (\14\:net47 \15\:net47) resistor r=120.434 c=0 +rg581 (\15\:net47 \16\:net47) resistor r=41.6577 c=0 +rg582 (\14\:net47 \17\:net47) resistor r=7.4762 c=0 +rg583 (\15\:net47 \3\:net47) resistor r=32.1097 c=0 +rg584 (\7\:X0 \8\:X0) resistor r=3.7604 c=0 +rg585 (\8\:X0 \9\:X0) resistor r=91.5933 c=0 +rg586 (\8\:X0 \10\:X0) resistor r=62.0099 c=0 +rg587 (\12\:net44 \13\:net44) resistor r=174.262 c=0 +rg588 (\13\:net44 \14\:net44) resistor r=165.153 c=0 +rg589 (\14\:net44 \15\:net44) resistor r=116.403 c=0 +rg590 (\15\:net44 \16\:net44) resistor r=138.542 c=0 +rg591 (\14\:net44 \17\:net44) resistor r=135.474 c=0 +rg592 (\17\:net44 \18\:net44) resistor r=72.4266 c=0 +rg593 (\18\:net44 \9\:net44) resistor r=3.7604 c=0 +rg594 (\18\:net44 \19\:net44) resistor r=80.1349 c=0 +rg595 (\12\:net32 \13\:net32) resistor r=174.262 c=0 +rg596 (\13\:net32 \14\:net32) resistor r=165.153 c=0 +rg597 (\14\:net32 \15\:net32) resistor r=116.403 c=0 +rg598 (\15\:net32 \16\:net32) resistor r=138.542 c=0 +rg599 (\14\:net32 \17\:net32) resistor r=135.474 c=0 +rg600 (\17\:net32 \18\:net32) resistor r=72.4266 c=0 +rg601 (\18\:net32 \9\:net32) resistor r=3.7604 c=0 +rg602 (\18\:net32 \19\:net32) resistor r=80.1349 c=0 +rg603 (I25\|net013 \2\:I25\|net013) resistor r=19.7812 c=0 +rg604 (\2\:I25\|net013 \3\:I25\|net013) resistor r=115.592 c=0 +rg605 (\2\:I25\|net013 \4\:I25\|net013) resistor r=37.6755 c=0 +rg606 (I22\|net013 \2\:I22\|net013) resistor r=19.7812 c=0 +rg607 (\2\:I22\|net013 \3\:I22\|net013) resistor r=115.592 c=0 +rg608 (\2\:I22\|net013 \4\:I22\|net013) resistor r=37.6755 c=0 +rg609 (\18\:Y3 \19\:Y3) resistor r=91.5933 c=0 +rg610 (\19\:Y3 \16\:Y3) resistor r=3.7604 c=0 +rg611 (\19\:Y3 \20\:Y3) resistor r=62.0099 c=0 +rg612 (\18\:Y2 \19\:Y2) resistor r=91.5933 c=0 +rg613 (\19\:Y2 \16\:Y2) resistor r=3.7604 c=0 +rg614 (\19\:Y2 \20\:Y2) resistor r=62.0099 c=0 +rg615 (I8\|I1\|Ai \2\:I8\|I1\|Ai) resistor r=77.852 c=0 +rg616 (\2\:I8\|I1\|Ai \3\:I8\|I1\|Ai) resistor r=333.882 c=0 +rg617 (I7\|I1\|Ai \2\:I7\|I1\|Ai) resistor r=77.852 c=0 +rg618 (\2\:I7\|I1\|Ai \3\:I7\|I1\|Ai) resistor r=333.882 c=0 +rg619 (\5\:I14\|net013 \6\:I14\|net013) resistor r=37.6755 c=0 +rg620 (\6\:I14\|net013 I14\|net013) resistor r=19.7812 c=0 +rg621 (\6\:I14\|net013 \7\:I14\|net013) resistor r=115.592 c=0 +rg622 (\5\:I17\|net013 \6\:I17\|net013) resistor r=115.592 c=0 +rg623 (\6\:I17\|net013 I17\|net013) resistor r=19.7812 c=0 +rg624 (\6\:I17\|net013 \7\:I17\|net013) resistor r=37.6755 c=0 +rg625 (\12\:X0 \13\:X0) resistor r=3.7604 c=0 +rg626 (\13\:X0 \14\:X0) resistor r=62.0099 c=0 +rg627 (\13\:X0 \15\:X0) resistor r=91.5933 c=0 +rg628 (\16\:X0 \17\:X0) resistor r=3.7604 c=0 +rg629 (\17\:X0 \18\:X0) resistor r=62.0099 c=0 +rg630 (\17\:X0 \19\:X0) resistor r=91.5933 c=0 +rg631 (\19\:net075 \20\:net075) resistor r=3.7604 c=0 +rg632 (\20\:net075 \21\:net075) resistor r=55.3433 c=0 +rg633 (\20\:net075 \22\:net075) resistor r=81.8016 c=0 +rg634 (\19\:net47 \20\:net47) resistor r=3.7604 c=0 +rg635 (\20\:net47 \21\:net47) resistor r=55.3433 c=0 +rg636 (\20\:net47 \22\:net47) resistor r=81.8016 c=0 +rg637 (\21\:Y1 \22\:Y1) resistor r=627.236 c=0 +rg638 (\22\:Y1 \23\:Y1) resistor r=62.0099 c=0 +rg640 (\23\:Y1 \24\:Y1) resistor r=91.5933 c=0 +rg641 (Y0 \9\:Y0) resistor r=129.31 c=0 +rg642 (\9\:Y0 \10\:Y0) resistor r=455.086 c=0 +rg643 (\10\:Y0 \11\:Y0) resistor r=1019.75 c=0 +rg644 (\11\:Y0 \12\:Y0) resistor r=948.15 c=0 +rg645 (\12\:Y0 \13\:Y0) resistor r=62.0099 c=0 +rg647 (\9\:Y0 \14\:Y0) resistor r=165.202 c=0 +rg648 (\14\:Y0 \15\:Y0) resistor r=91.5933 c=0 +rg649 (\15\:Y0 \16\:Y0) resistor r=62.0099 c=0 +rg650 (\10\:Y0 \17\:Y0) resistor r=165.41 c=0 +rg651 (\17\:Y0 \18\:Y0) resistor r=91.5933 c=0 +rg652 (\18\:Y0 \19\:Y0) resistor r=62.0099 c=0 +rg653 (\11\:Y0 \20\:Y0) resistor r=165.618 c=0 +rg654 (\20\:Y0 \21\:Y0) resistor r=91.5933 c=0 +rg655 (\21\:Y0 \22\:Y0) resistor r=62.0099 c=0 +rg656 (\13\:Y0 \23\:Y0) resistor r=91.5933 c=0 +I25\|MP0 (\7\:I25\|net013 \20\:Y3 \66\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP0 (\7\:I22\|net013 \20\:Y2 \137\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP2 (\13\:net0127 \7\:I14\|net013 \125\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP2 (\21\:net0115 \5\:I17\|net013 \60\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MP1 (\64\:vdd! \14\:X0 \7\:I25\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP1 (\129\:vdd! \18\:X0 \7\:I22\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP4 (\63\:vdd! \22\:net075 \4\:I8\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP4 (\62\:vdd! \22\:net47 \4\:I7\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP1 (\4\:I14\|net013 \22\:X1 \141\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP0 (\4\:I17\|net013 \22\:Y1 \131\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MP2 (\67\:vdd! \3\:I25\|net013 \12\:net075 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MP2 (\142\:vdd! \3\:I22\|net013 \12\:net47 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP1 (I8\|I1\|net8 \13\:net44 \1\:Z3 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP1 (I7\|I1\|net8 \13\:net32 \1\:Z2 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MP0 (\132\:vdd! \16\:Y0 \4\:I14\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MP1 (\124\:vdd! \10\:X0 \4\:I17\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP0 (\65\:vdd! I8\|I1\|Ai I8\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP0 (\128\:vdd! I7\|I1\|Ai I7\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP1 (\7\:I8\|I3\|net013 \17\:net44 \70\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP2 (I8\|I1\|net022 \5\:I8\|I1\|Bi \69\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP1 (\7\:I7\|I3\|net013 \17\:net32 \147\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP2 (I7\|I1\|net022 \5\:I7\|I1\|Bi \136\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP2 (\12\:net35 \4\:I6\|I3\|net013 \158\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP5 (\140\:vdd! \3\:net0127 \5\:I6\|I1\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP0 (\68\:vdd! \8\:net075 \7\:I8\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP3 (\7\:Z3 \16\:net075 I8\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP0 (\143\:vdd! \8\:net47 \7\:I7\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP3 (\7\:Z2 \16\:net47 I7\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP1 (\164\:vdd! \8\:net0127 \7\:I6\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP2 (\150\:vdd! \4\:I6\|I1\|Bi I6\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP0 (\73\:vdd! \13\:Y3 \7\:I24\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP0 (I6\|I1\|net8 \6\:I6\|I1\|Ai \163\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP0 (\165\:vdd! \13\:Y2 \7\:I23\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP1 (\5\:Z1 \5\:net0127 I6\|I1\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP2 (\13\:net095 \7\:I16\|net013 \172\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MP0 (\7\:I6\|I3\|net013 \14\:net0115 \171\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP3 (I6\|I1\|net022 \16\:net0115 \6\:Z1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MP5 (I8\|I1\|Bi \15\:net44 \72\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MP2 (\71\:vdd! \3\:I8\|I3\|net013 \13\:net5 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MP5 (I7\|I1\|Bi \15\:net32 \146\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MP2 (\151\:vdd! \3\:I7\|I3\|net013 \13\:net45 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MP4 (\4\:I6\|I1\|Ai net0115 \174\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP1 (\4\:I16\|net013 \6\:X1 \185\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP0 (\157\:vdd! \5\:I2\|I4\|Ai I2\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP1 (\7\:I24\|net013 \12\:X1 \74\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MP0 (\175\:vdd! \16\:Y1 \4\:I16\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP1 (\7\:I23\|net013 \17\:X1 \166\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP2 (\19\:net34 \7\:I13\|net013 \190\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP1 (I11\|I4\|net8 \13\:net0100 \15\:I11\|net3 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MP2 (\76\:vdd! \3\:I24\|net013 \16\:net078 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MP2 (\176\:vdd! \3\:I23\|net013 \16\:net28 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP1 (I2\|I4\|net8 \13\:net29 \15\:I2\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP0 (\75\:vdd! \5\:I11\|I4\|Ai I11\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MP0 (\7\:I1\|net1 \6\:net095 \225\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP4 (I1\|I4\|Ai \8\:net095 \206\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MP1 (\215\:vdd! \8\:net34 \7\:I1\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP0 (I1\|I4\|net8 \5\:I1\|I4\|Ai \195\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP5 (\203\:vdd! \9\:net34 \2\:I1\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP1 (\20\:I1\|net3 \16\:net34 I1\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP1 (\4\:I13\|net013 \24\:X2 \202\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MP0 (\201\:vdd! \19\:Y0 \4\:I13\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP3 (I1\|I4\|net022 \4\:net095 \15\:I1\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MP2 (\184\:vdd! \5\:I1\|I4\|Bi I1\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MP1 (\12\:net26 \7\:I2\|net6 \214\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MP0 (\207\:vdd! \3\:I2\|net1 \12\:net26 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MP1 (\7\:I2\|net1 \15\:net29 \196\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MP0 (\186\:vdd! \8\:net28 \7\:I2\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP4 (\177\:vdd! \9\:net28 \2\:I2\|I4\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP5 (\251\:vdd! \9\:net35 I1\|I3\|Bi vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP2 (I1\|I3\|net022 \5\:I1\|I3\|Bi \239\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP3 (\6\:net32 \3\:I1\|net3 I1\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MP0 (I1\|net6 \5\:I1\|net3 \250\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MP1 (\249\:vdd! \5\:net35 I1\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP1 (I1\|I3\|net8 \4\:net35 \7\:net32 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP0 (\228\:vdd! I1\|I3\|Ai I1\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MP1 (\12\:net31 \7\:I1\|net6 \240\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MP0 (\234\:vdd! \3\:I1\|net1 \12\:net31 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MP4 (\218\:vdd! \11\:I1\|net3 \6\:I1\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP5 (\5\:I3\|I3\|Bi \9\:net26 \241\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP5 (\221\:vdd! \9\:net45 I2\|I3\|Bi vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MP0 (I2\|net6 \5\:I2\|net3 \220\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MP1 (\219\:vdd! \5\:net45 I2\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP2 (\224\:vdd! \2\:I3\|I3\|Bi I3\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP2 (I2\|I3\|net022 \5\:I2\|I3\|Bi \213\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP3 (\6\:net44 \3\:I2\|net3 I2\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP1 (I2\|I3\|net8 \4\:net45 \7\:net44 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP0 (\200\:vdd! I2\|I3\|Ai I2\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MP4 (\189\:vdd! \12\:I2\|net3 \6\:I2\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP5 (I2\|I4\|Bi \17\:net29 \180\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP2 (I2\|I4\|net022 \5\:I2\|I4\|Bi \170\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MP3 (\20\:I2\|net3 \19\:net28 I2\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP0 (\84\:vdd! I11\|I3\|Ai I11\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MP1 (\12\:net1 \7\:I11\|net6 \85\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MP0 (\83\:vdd! \3\:I11\|net1 \12\:net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP4 (\82\:vdd! \11\:I11\|net3 \6\:I11\|I3\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MP1 (\7\:I11\|net1 \15\:net0100 \81\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP5 (I11\|I4\|Bi \17\:net0100 \80\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MP0 (\79\:vdd! \8\:net078 \7\:I11\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP2 (I11\|I4\|net022 \5\:I11\|I4\|Bi \78\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP4 (\77\:vdd! \9\:net078 \2\:I11\|I4\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MP3 (\20\:I11\|net3 \19\:net078 I11\|I4\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP2 (\90\:vdd! \2\:I10\|I3\|Bi I10\|I3\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP5 (\5\:I10\|I3\|Bi \9\:net1 \91\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP5 (\88\:vdd! \10\:net5 I11\|I3\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP2 (I11\|I3\|net022 \5\:I11\|I3\|Bi \89\:vdd! vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP3 (\6\:Z4 \3\:I11\|net3 I11\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MP0 (I11\|net6 \5\:I11\|net3 \87\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MP1 (\86\:vdd! \6\:net5 I11\|net6 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MP1 (I11\|I3\|net8 \5\:net5 \7\:Z4 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP4 (\4\:I0\|I3\|Ai \10\:I0\|net3 \275\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MP1 (\23\:net55 \7\:I0\|net1 \282\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MP0 (\276\:vdd! \3\:I0\|net6 \23\:net55 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP0 (I0\|I3\|net8 \6\:I0\|I3\|Ai \263\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP1 (\6\:net29 \7\:net31 I0\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MP1 (\5\:I0\|net6 \6\:net31 \271\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MP0 (\270\:vdd! \17\:I0\|net3 \5\:I0\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP3 (I0\|I3\|net022 \18\:I0\|net3 \7\:net29 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP2 (\254\:vdd! \5\:I0\|I3\|Bi I0\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MP5 (\3\:I0\|I3\|Bi \9\:net31 \269\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MP0 (\3\:I3\|net1 \18\:net087 \277\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MP1 (\264\:vdd! \12\:net54 \3\:I3\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MP1 (\13\:net21 \7\:I3\|net1 \255\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MP0 (\248\:vdd! \3\:I3\|net6 \13\:net21 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MP1 (\5\:I3\|net6 \6\:net26 \243\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MP0 (\242\:vdd! \17\:I3\|net3 \5\:I3\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP3 (I0\|I4\|net022 \6\:net38 I0\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP2 (\3\:net087 \7\:I21\|net013 \287\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP4 (I0\|I4\|Ai \17\:net38 \315\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP2 (\294\:vdd! \4\:I0\|I4\|Bi I0\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MP0 (\3\:I0\|net1 \18\:net38 \301\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP4 (I3\|I4\|Ai \17\:net087 \286\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP5 (\284\:vdd! \11\:net39 \7\:I0\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MP1 (\285\:vdd! \6\:net39 \3\:I0\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP1 (\317\:vdd! \3\:X2 \4\:I18\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP0 (I0\|I4\|net8 \5\:I0\|I4\|Ai \306\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP0 (\4\:I21\|net013 \10\:Y2 \295\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MP1 (\4\:I0\|net3 \8\:net39 I0\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MP1 (\291\:vdd! \17\:X2 \4\:I21\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP2 (\5\:net38 \7\:I18\|net013 \316\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP0 (I10\|I3\|net8 \6\:I10\|I3\|Ai \94\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP0 (I3\|I3\|net8 \6\:I3\|I3\|Ai \233\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP1 (\6\:Z5 \7\:net1 I10\|I3\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MP1 (\5\:I10\|net6 \6\:net1 \93\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP1 (\6\:net0100 \7\:net26 I3\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MP0 (\92\:vdd! \17\:I10\|net3 \5\:I10\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP3 (I10\|I3\|net022 \18\:I10\|net3 \7\:Z5 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP3 (I3\|I3\|net022 \18\:I3\|net3 \7\:net0100 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP5 (\99\:vdd! \17\:net17 \7\:I10\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP5 (\258\:vdd! \17\:net54 \7\:I3\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MP1 (\98\:vdd! \12\:net17 \3\:I10\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MP4 (\4\:I10\|I3\|Ai \10\:I10\|net3 \97\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MP4 (\4\:I3\|I3\|Ai \10\:I3\|net3 \247\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MP1 (\14\:net15 \7\:I10\|net1 \96\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MP0 (\95\:vdd! \3\:I10\|net6 \14\:net15 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP3 (I10\|I4\|net022 \6\:net8 I10\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP3 (I3\|I4\|net022 \6\:net087 I3\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP4 (\4\:I10\|I4\|Ai \17\:net8 \102\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP2 (\101\:vdd! \4\:I10\|I4\|Bi I10\|I4\|net022 vdd!) pmos1 \ + w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP2 (\268\:vdd! \4\:I3\|I4\|Bi I3\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MP0 (\3\:I10\|net1 \18\:net8 \100\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP0 (\4\:I26\|net013 \10\:Y3 \106\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP1 (\104\:vdd! \9\:X2 \4\:I26\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP0 (I10\|I4\|net8 \2\:I10\|I4\|Ai \105\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP0 (I3\|I4\|net8 \5\:I3\|I4\|Ai \281\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MP1 (\4\:I10\|net3 \14\:net17 I10\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MP1 (\4\:I3\|net3 \14\:net54 I3\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MP2 (\3\:net8 \7\:I26\|net013 \103\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MP1 (\5\:I4\|net6 \7\:net21 \309\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MP0 (\308\:vdd! \17\:I4\|net3 \5\:I4\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP4 (\320\:vdd! \19\:net55 \4\:I5\|I1\|Ai vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP2 (\3\:net39 \7\:I12\|net013 \335\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP5 (\5\:I4\|I3\|Bi \10\:net21 \307\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MP0 (\4\:I18\|net013 \9\:Y1 \325\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP0 (\348\:vdd! \8\:net55 \7\:I5\|I3\|net013 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP3 (\7\:net54 \13\:net55 I5\|I1\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MP1 (\15\:net16 \7\:I4\|net1 \321\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP1 (I5\|I1\|net8 \7\:net093 net54 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MP0 (\314\:vdd! \3\:I4\|net6 \15\:net16 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP1 (\4\:I12\|net013 \23\:X3 \347\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP0 (\330\:vdd! I5\|I1\|Ai I5\|I1\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MP0 (\336\:vdd! \22\:Y0 \4\:I12\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP4 (I4\|I4\|Ai \14\:net090 \353\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP5 (I5\|I1\|Bi \9\:net093 \351\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP2 (\357\:vdd! \3\:I5\|I3\|net013 \2\:net19 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MP0 (\3\:I4\|net1 \16\:net090 \341\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MP1 (\7\:I5\|I3\|net013 \11\:net093 \352\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MP2 (I5\|I1\|net022 \5\:I5\|I1\|Bi \340\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MP1 (\331\:vdd! \10\:net19 \3\:I4\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP1 (\4\:I20\|net013 \12\:X3 \360\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP0 (\4\:I15\|net013 \12\:Y0 \367\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP1 (\4\:I19\|net013 \15\:X3 \369\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP0 (\355\:vdd! \3\:Y2 \4\:I20\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP1 (\363\:vdd! \4\:X0 \4\:I15\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP0 (\368\:vdd! \3\:Y1 \4\:I19\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MP2 (\5\:net090 \7\:I20\|net013 \354\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MP2 (\1\:Z0 \5\:I15\|net013 \359\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MP2 (\3\:net093 \7\:I19\|net013 \364\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP4 (\4\:I4\|I3\|Ai \10\:I4\|net3 \313\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP0 (I4\|I3\|net8 \6\:I4\|I3\|Ai \300\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP1 (\8\:net17 \8\:net21 I4\|I3\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP3 (I4\|I3\|net022 \18\:I4\|net3 \9\:net17 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MP2 (\290\:vdd! \2\:I4\|I3\|Bi I4\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MP1 (\115\:vdd! \5\:net16 \3\:I9\|net1 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP4 (\4\:I9\|I3\|Ai \10\:I9\|net3 \114\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MP1 (\3\:Z7 \7\:I9\|net1 \113\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MP0 (\112\:vdd! \3\:I9\|net6 \3\:Z7 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP0 (I9\|I3\|net8 \6\:I9\|I3\|Ai \111\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP1 (\6\:Z6 \8\:net15 I9\|I3\|net8 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MP1 (\5\:I9\|net6 \7\:net15 \110\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MP0 (\109\:vdd! \17\:I9\|net3 \5\:I9\|net6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP3 (I9\|I3\|net022 \18\:I9\|net3 \7\:Z6 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP2 (\107\:vdd! \2\:I9\|I3\|Bi I9\|I3\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MP5 (\5\:I9\|I3\|Bi \10\:net15 \108\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP3 (I4\|I4\|net022 \6\:net090 I4\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP3 (I9\|I4\|net022 \6\:net13 I9\|net3 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP4 (I9\|I4\|Ai \14\:net13 \119\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP2 (\334\:vdd! \4\:I4\|I4\|Bi I4\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP2 (\118\:vdd! \4\:I9\|I4\|Bi I9\|I4\|net022 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MP0 (\3\:I9\|net1 \16\:net13 \117\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP5 (\324\:vdd! \15\:net19 \7\:I4\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP5 (\116\:vdd! \10\:net16 \7\:I9\|I4\|Bi vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP1 (\4\:I27\|net013 \9\:X3 \58\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP0 (\121\:vdd! \3\:Y3 \4\:I27\|net013 vdd!) pmos1 w=1e-06 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP0 (I4\|I4\|net8 \5\:I4\|I4\|Ai \346\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP0 (I9\|I4\|net8 \5\:I9\|I4\|Ai \122\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MP1 (\4\:I4\|net3 \12\:net19 I4\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MP1 (\4\:I9\|net3 \7\:net16 I9\|I4\|net8 vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MP2 (\5\:net13 \7\:I27\|net013 \120\:vdd! vdd!) pmos1 w=1e-06 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN0 (I25\|net9 \18\:Y3 \21\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN0 (I22\|net9 \18\:Y2 \317\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN2 (\11\:net0127 \5\:I14\|net013 \287\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN2 (\23\:net0115 \7\:I17\|net013 \319\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN1 (\5\:I25\|net013 \15\:X0 I25\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN1 (\5\:I22\|net013 \19\:X0 I22\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN4 (\293\:gnd! \21\:net075 \6\:I8\|I1\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN4 (\1\:gnd! \21\:net47 \6\:I7\|I1\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN1 (I14\|net9 \19\:X1 \3\:I14\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN0 (I17\|net9 \24\:Y1 \3\:I17\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I25\|MN2 (\23\:gnd! \4\:I25\|net013 \10\:net075 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I22\|MN2 (\315\:gnd! \4\:I22\|net013 \10\:net47 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN2 (I8\|I1\|net17 \13\:net075 \6\:Z3 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN2 (I7\|I1\|net17 \13\:net47 \6\:Z2 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I14\|MN0 (\280\:gnd! \14\:Y0 I14\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I17\|MN1 (\318\:gnd! \9\:X0 I17\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN3 (\290\:gnd! \12\:net44 I8\|I1\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN3 (\22\:gnd! \12\:net32 I7\|I1\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN1 (I8\|I3\|net9 \19\:net44 \24\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN1 (I8\|I1\|net32 \7\:I8\|I1\|Bi \282\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN1 (I7\|I3\|net9 \19\:net32 \309\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN1 (I7\|I1\|net32 \7\:I7\|I1\|Bi \25\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN2 (\10\:net35 I6\|I3\|net013 \270\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN5 (\312\:gnd! \7\:net0127 \7\:I6\|I1\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN0 (\5\:I8\|I3\|net013 \9\:net075 I8\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN0 (\5\:Z3 \3\:I8\|I1\|Ai I8\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN0 (\5\:I7\|I3\|net013 \9\:net47 I7\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN0 (\5\:Z2 \3\:I7\|I1\|Ai I7\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN1 (\262\:gnd! \10\:net0127 I6\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN1 (\310\:gnd! \3\:I6\|I1\|Bi I6\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN0 (\5\:I24\|net013 \14\:Y3 I24\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN3 (I6\|I1\|net17 \6\:net0127 \304\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN0 (\5\:I23\|net013 \14\:Y2 I23\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN2 (\7\:Z1 \19\:net0115 I6\|I1\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN2 (\11\:net095 \5\:I16\|net013 \253\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I3\|MN0 (I6\|I3\|net9 \12\:net0115 \5\:I6\|I3\|net013 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN0 (I6\|I1\|net32 \5\:I6\|I1\|Ai \1\:Z1 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I1\|MN5 (\3\:I8\|I1\|Bi \16\:net44 \274\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I8\|I3\|MN2 (\26\:gnd! \4\:I8\|I3\|net013 \14\:net5 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I1\|MN5 (\3\:I7\|I1\|Bi \16\:net32 \27\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I7\|I3\|MN2 (\307\:gnd! \4\:I7\|I3\|net013 \14\:net45 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I6\|I1\|MN4 (\3\:I6\|I1\|Ai \4\:net0115 \300\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN1 (I16\|net9 \4\:X1 \3\:I16\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN3 (\29\:gnd! \12\:net29 I2\|I4\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN1 (I24\|net9 \10\:X1 \28\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I16\|MN0 (\246\:gnd! \17\:Y1 I16\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN1 (I23\|net9 \15\:X1 \302\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN2 (\17\:net34 \5\:I13\|net013 \240\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN2 (I11\|I4\|net17 \17\:net078 \18\:I11\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I24\|MN2 (\30\:gnd! \4\:I24\|net013 \14\:net078 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I23\|MN2 (\299\:gnd! \4\:I23\|net013 \15\:net28 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN2 (I2\|I4\|net17 \17\:net28 \18\:I2\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN3 (\264\:gnd! \12\:net0100 I11\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN1 (\19\:I1\|net3 \4\:I1\|I4\|Bi I1\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MN1 (I2\|I0\|net9 \19\:net29 \292\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I0\|MN0 (\5\:I2\|net1 \11\:net28 I2\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN1 (I13\|net9 \22\:X2 \3\:I13\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I13\|MN0 (\232\:gnd! \17\:Y0 I13\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN3 (I1\|I4\|net17 \14\:net34 \18\:I1\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN4 (\296\:gnd! \5\:net28 I2\|I4\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN2 (\297\:gnd! \3\:net095 I1\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN5 (\3\:I11\|I4\|Bi \18\:net0100 \247\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MN0 (\5\:I11\|net1 \11\:net078 I11\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN5 (\3\:I2\|I4\|Bi \18\:net29 \33\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN1 (I11\|I4\|net32 \7\:I11\|I4\|Bi \249\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN4 (\31\:gnd! \5\:net078 I11\|I4\|Ai 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN1 (I2\|I4\|net32 \7\:I2\|I4\|Bi \32\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I4\|MN0 (\19\:I11\|net3 \4\:I11\|I4\|Ai I11\|I4\|net32 0) nmos1 \ + w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I4\|MN0 (\19\:I2\|net3 \4\:I2\|I4\|Ai I2\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MN0 (I1\|I0\|net9 \10\:net095 \218\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN4 (\3\:I1\|I4\|Ai \9\:net095 \283\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MN1 (I2\|I1\|net9 \5\:I2\|net6 \277\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I0\|MN1 (\5\:I1\|net1 \11\:net34 I1\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I1\|MN0 (\10\:net26 \4\:I2\|net1 I2\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN0 (I1\|I4\|net32 \7\:I1\|I4\|Ai \286\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I4\|MN5 (\227\:gnd! \5\:net34 I1\|I4\|Bi 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN2 (I2\|I3\|net17 I2\|net3 net44 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN3 (\220\:gnd! \4\:net5 I11\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MN1 (I11\|I1\|net9 \5\:I11\|net6 \37\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN3 (\36\:gnd! \3\:net45 I2\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I1\|MN0 (\10\:net1 \4\:I11\|net1 I11\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN4 (\234\:gnd! \10\:I11\|net3 \5\:I11\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN4 (\35\:gnd! \11\:I2\|net3 \5\:I2\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I0\|MN1 (I11\|I0\|net9 \19\:net0100 \34\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MN1 (\203\:gnd! \7\:net35 I1\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN2 (I1\|I3\|net17 I1\|net3 net32 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN5 (\259\:gnd! \8\:net45 \4\:I2\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN3 (\265\:gnd! \3\:net35 I1\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MN1 (I1\|I1\|net9 \5\:I1\|net6 \210\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MN0 (I2\|I2\|net9 \6\:I2\|net3 \3\:I2\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I1\|MN0 (\10\:net31 \4\:I1\|net1 I1\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN4 (\275\:gnd! \10\:I1\|net3 \5\:I1\|I3\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I2\|MN1 (\268\:gnd! \7\:net45 I2\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN5 (\39\:gnd! \9\:net5 \4\:I11\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN1 (I11\|I3\|net32 \6\:I11\|I3\|Bi \206\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN1 (I2\|I3\|net32 \6\:I2\|I3\|Bi \40\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN0 (\4\:Z4 \3\:I11\|I3\|Ai I11\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I2\|I3\|MN0 (\4\:net44 \3\:I2\|I3\|Ai I2\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MN0 (I11\|I2\|net9 \6\:I11\|net3 \3\:I11\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I2\|MN1 (\38\:gnd! \8\:net5 I11\|I2\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I11\|I3\|MN2 (I11\|I3\|net17 I11\|net3 \2\:Z4 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN1 (\198\:gnd! \3\:I10\|I3\|Bi I10\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN5 (\6\:I10\|I3\|Bi \3\:net1 \44\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN1 (\45\:gnd! \3\:I3\|I3\|Bi I3\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN5 (\6\:I3\|I3\|Bi \3\:net26 \243\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN5 (\196\:gnd! \8\:net35 \4\:I1\|I3\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN1 (I1\|I3\|net32 \6\:I1\|I3\|Bi \251\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I3\|MN0 (\4\:net32 \3\:I1\|I3\|Ai I1\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I1\|I2\|MN0 (I1\|I2\|net9 \6\:I1\|net3 \3\:I1\|net6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MN1 (I0\|I2\|net9 \4\:net31 \185\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MN1 (\224\:gnd! \4\:I3\|net6 I3\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I2\|MN0 (\7\:I0\|net6 \16\:I0\|net3 I0\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN0 (I0\|I3\|net32 \5\:I0\|I3\|Ai net29 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MN1 (I3\|I2\|net9 \4\:net26 \230\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN1 (\237\:gnd! \6\:I0\|I3\|Bi I0\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN5 (\4\:I0\|I3\|Bi \3\:net31 \190\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I2\|MN0 (\7\:I3\|net6 \16\:I3\|net3 I3\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MN0 (I3\|I0\|net9 \13\:net087 I3\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN4 (\3\:I0\|I3\|Ai \12\:I0\|net3 \208\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MN0 (I0\|I1\|net9 \5\:I0\|net1 \22\:net55 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I0\|MN1 (\215\:gnd! \16\:net54 I3\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I1\|MN1 (\179\:gnd! \4\:I0\|net6 I0\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN3 (I0\|I3\|net17 \8\:net31 \221\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I1\|MN0 (I3\|I1\|net9 \5\:I3\|net1 \11\:net21 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I3\|MN2 (\4\:net29 \20\:I0\|net3 I0\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN0 (I0\|I4\|net32 \4\:I0\|I4\|Ai \5\:I0\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN2 (net087 \5\:I21\|net013 \183\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN4 (\2\:I0\|I4\|Ai \19\:net38 \165\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN1 (\188\:gnd! \3\:I0\|I4\|Bi I0\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MN0 (I0\|I0\|net9 \13\:net38 I0\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN4 (\2\:I3\|I4\|Ai \19\:net087 \194\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN5 (\201\:gnd! \12\:net39 \5\:I0\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I0\|MN1 (\172\:gnd! \10\:net39 I0\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN1 (\151\:gnd! \4\:X2 I18\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN3 (I0\|I4\|net17 \9\:net39 \169\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN0 (I21\|net9 \8\:Y2 \3\:I21\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I0\|I4\|MN2 (\7\:I0\|net3 \8\:net38 I0\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I21\|MN1 (\176\:gnd! \18\:X2 I21\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN2 (\3\:net38 \5\:I18\|net013 \159\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN3 (I10\|I3\|net17 \8\:net1 \191\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN3 (I3\|I3\|net17 \8\:net26 \55\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN2 (\4\:Z5 \20\:I10\|net3 I10\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MN1 (I10\|I2\|net9 \4\:net1 \48\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN2 (\4\:net0100 \20\:I3\|net3 I3\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I2\|MN0 (\7\:I10\|net6 \16\:I10\|net3 I10\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN0 (I10\|I3\|net32 \5\:I10\|I3\|Ai \1\:Z5 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN0 (I3\|I3\|net32 \5\:I3\|I3\|Ai net0100 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN5 (\167\:gnd! \18\:net17 \5\:I10\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN5 (\61\:gnd! \18\:net54 \5\:I3\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MN1 (\54\:gnd! \16\:net17 I10\|I0\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I3\|MN4 (\3\:I10\|I3\|Ai \12\:I10\|net3 \181\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I3\|MN4 (\3\:I3\|I3\|Ai \12\:I3\|net3 \56\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MN0 (I10\|I1\|net9 \5\:I10\|net1 \13\:net15 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I1\|MN1 (\50\:gnd! \4\:I10\|net6 I10\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN0 (I10\|I4\|net32 I10\|I4\|Ai \5\:I10\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN0 (I3\|I4\|net32 \4\:I3\|I4\|Ai \5\:I3\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN4 (\5\:I10\|I4\|Ai \19\:net8 \60\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN1 (\161\:gnd! \3\:I10\|I4\|Bi I10\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN1 (\62\:gnd! \3\:I3\|I4\|Bi I3\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I0\|MN0 (I10\|I0\|net9 \13\:net8 I10\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN0 (I26\|net9 \8\:Y3 \3\:I26\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN1 (\67\:gnd! \10\:X2 I26\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN3 (I10\|I4\|net17 \15\:net17 \146\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN3 (I3\|I4\|net17 \15\:net54 \72\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I10\|I4\|MN2 (\7\:I10\|net3 \8\:net8 I10\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I3\|I4\|MN2 (\7\:I3\|net3 \8\:net087 I3\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I26\|MN2 (net8 \5\:I26\|net013 \65\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MN1 (I4\|I2\|net9 \5\:net21 \148\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I2\|MN0 (\7\:I4\|net6 \16\:I4\|net3 I4\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN4 (\156\:gnd! \18\:net55 \6\:I5\|I1\|Ai 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN2 (net39 \5\:I12\|net013 \144\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN5 (\6\:I4\|I3\|Bi \4\:net21 \163\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I18\|MN0 (I18\|net9 \11\:Y1 \3\:I18\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN0 (\5\:I5\|I3\|net013 \9\:net55 I5\|I3\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN0 (\5\:net54 \3\:I5\|I1\|Ai I5\|I1\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MN0 (I4\|I1\|net9 \5\:I4\|net1 \14\:net16 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN2 (I5\|I1\|net17 \10\:net55 \6\:net54 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I1\|MN1 (\142\:gnd! \4\:I4\|net6 I4\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN1 (I12\|net9 \21\:X3 \3\:I12\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN3 (\154\:gnd! \6\:net093 I5\|I1\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I12\|MN0 (\139\:gnd! \20\:Y0 I12\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN4 (\2\:I4\|I4\|Ai \17\:net090 \119\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN5 (\3\:I5\|I1\|Bi \10\:net093 \125\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN2 (\122\:gnd! \4\:I5\|I3\|net013 \3\:net19 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MN0 (I4\|I0\|net9 \9\:net090 I4\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I3\|MN1 (I5\|I3\|net9 \13\:net093 \130\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I5\|I1\|MN1 (I5\|I1\|net32 \7\:I5\|I1\|Bi \128\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I0\|MN1 (\136\:gnd! \14\:net19 I4\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN1 (I20\|net9 \10\:X3 \3\:I20\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN0 (I15\|net9 \23\:Y0 \3\:I15\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN1 (I19\|net9 \13\:X3 \3\:I19\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN0 (\104\:gnd! \4\:Y2 I20\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN1 (\110\:gnd! \3\:X0 I15\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN0 (\107\:gnd! \4\:Y1 I19\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I20\|MN2 (\3\:net090 \5\:I20\|net013 \112\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I15\|MN2 (\3\:Z0 \7\:I15\|net013 \117\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I19\|MN2 (net093 \5\:I19\|net013 \114\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN2 (\6\:net17 \20\:I4\|net3 I4\|I3\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN2 (\4\:Z6 \20\:I9\|net3 I9\|I3\|net17 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MN1 (I9\|I2\|net9 \5\:net15 \75\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I2\|MN0 (\7\:I9\|net6 \16\:I9\|net3 I9\|I2\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN0 (I4\|I3\|net32 \5\:I4\|I3\|Ai \3\:net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN0 (I9\|I3\|net32 \5\:I9\|I3\|Ai \2\:Z6 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN1 (\73\:gnd! \3\:I4\|I3\|Bi I4\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN1 (\134\:gnd! \3\:I9\|I3\|Bi I9\|I3\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN5 (\6\:I9\|I3\|Bi \4\:net15 \71\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MN1 (\79\:gnd! \9\:net16 I9\|I0\|net9 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN4 (\3\:I4\|I3\|Ai \12\:I4\|net3 \83\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN4 (\3\:I9\|I3\|Ai \12\:I9\|net3 \116\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MN0 (I9\|I1\|net9 \5\:I9\|net1 \2\:Z7 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I1\|MN1 (\77\:gnd! \4\:I9\|net6 I9\|I1\|net9 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I3\|MN3 (I4\|I3\|net17 \9\:net21 \80\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I3\|MN3 (I9\|I3\|net17 \9\:net15 \124\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN0 (I4\|I4\|net32 \4\:I4\|I4\|Ai \5\:I4\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN0 (I9\|I4\|net32 \4\:I9\|I4\|Ai \5\:I9\|net3 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN4 (\2\:I9\|I4\|Ai \17\:net13 \86\:gnd! 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN1 (\87\:gnd! \3\:I4\|I4\|Bi I4\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN1 (\101\:gnd! \3\:I9\|I4\|Bi I9\|I4\|net32 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I0\|MN0 (I9\|I0\|net9 \9\:net13 I9\|net1 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN5 (\84\:gnd! \16\:net19 \5\:I4\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN5 (\109\:gnd! \11\:net16 \5\:I9\|I4\|Bi 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN1 (I27\|net9 \7\:X3 \3\:I27\|net013 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN0 (\92\:gnd! \4\:Y3 I27\|net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN3 (I4\|I4\|net17 \13\:net19 \96\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN3 (I9\|I4\|net17 \8\:net16 \95\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I4\|I4\|MN2 (\7\:I4\|net3 \8\:net090 I4\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I9\|I4\|MN2 (\7\:I9\|net3 \8\:net13 I9\|I4\|net17 0) nmos1 w=8e-07 \ + l=1.8e-07 as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +I27\|MN2 (\3\:net13 \5\:I27\|net013 \90\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 \ + as=1.2e-12 ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..14162bb60927f1870054c7d1cff577a3178b0cc0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 02:13:04 2021 +// Design library name: multiplier_low +// Design cell name: 4X4_multiplier +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..ab5f63b72efb5457fae5cd919d5343de61ee2714 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre1_6429_1 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..3517b2e1bbafee4ed6ccc6c7ee683185fed32ed2 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "4X4_multiplier" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..977c49a7af51b2d093b657fb59440224595ba786 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,393 @@ +si: simSetDef().... simHost is initialized to "localhost" . +si: simSetDef().... simLoginName is initialized to "VLSI_57" . +si: simSetDef().... simHostDiffers is initialized to "nil". +si: simSetDef().... simInteractiveSimulatorList is initialized to ("verilog") . +si: simSetDef().... simPostAnalysisProcessingFunc is initialized to "nil". +si: simSetDef().... simNotifyKillActionFunc is initialized to "nil". +si: simSetDef().... simDoNotDisplayDialogBox is initialized to "nil". +si: simSetDef().... simNetlistFileName is initialized to "netlist" . +si: simSetDef().... simMaxNetlistErrors is initialized to 25 . +si: simSetDef().... simUserDefineDefaultRunDirFunc is initialized to "nil". +si: simSetDef().... simNlpGlobalLibName is initialized to "basic" . +si: simSetDef().... simNlpGlobalCellName is initialized to "nlpglobals" . +si: simSetDef().... simCommand is initialized to "" . +si: simSetDef().... simSedFile is initialized to "" . +si: simSetDef().... simDefaultSimulator is already set to "spice". Redefinition +to nil is ignored. +si: simSetDef().... simDefaultRunDir is already set to "spice.run1". +Redefinition to nil is ignored. +si: simSetDef().... simSymbolModifiedAction is initialized to "ignore" . +si: simSetDef().... simOtherInfo is initialized to "nil". +si: simSetDef().... simIsFlattenP is initialized to "nil". +si: simSetDef().... simStlInputFile is initialized to "input.stl" . +si: simSetDef().... simDiffInputFile is initialized to "simdiff.stl" . +si: simSetDef().... simNoSimdiff is initialized to "nil". +si: simSetDef().... simDefaultControl is initialized to "nil". +si: simSetDef().... simControlFile is initialized to "nil". +si: simSetDef().... simLogFile is initialized to "si.log" . +si: simSetDef().... simTimeUnit is initialized to 1e-09 . +si: simSetDef().... simCapUnit is initialized to 1e-15 . +si: simSetDef().... simDoNetlist is initialized to t . +si: simSetDef().... simDoSimulate is initialized to t . +si: simSetDef().... simNetlistHier is already set to t. Redefinition to nil is +ignored. +si: simSetDef().... simGlobalPrefix is initialized to "nil". +si: simSetDef().... simHierarchyPrefix is initialized to "nil". +si: simSetDef().... simNoLeadingHierarchyDelim is initialized to "nil". +si: simSetDef().... simPrefixHierarchyWithCV is initialized to "nil". +si: simSetDef().... simHierarchyDelimiter is initialized to "/" . +si: simSetDef().... simNetNamePrefix is initialized to "nil". +si: simSetDef().... simInstNamePrefix is initialized to "nil". +si: simSetDef().... simModelNamePrefix is initialized to "nil". +si: simSetDef().... simTermNamePrefix is initialized to "nil". +si: simSetDef().... simCheckTermMismatchAction is initialized to "error" . +si: simSetDef().... hnlEmptySwitchMasterAction is initialized to "ignore" . +si: simSetDef().... simLoadNetlister is initialized to t . +si: simSetDef().... simCleanFileList is initialized to "nil". +si: simSetDef().... simSimulatorSaveVars is initialized to "nil". +si: simSetDef().... simApplicationOptionsForm is initialized to "nil". +si: simSetDef().... simSimulatorSaveFiles is initialized to "nil". +si: simSetDef().... simDontCopyFileNetlistToRemoteRunDir is initialized to +"nil". +si: simSetDef().... simRsh is initialized to "nil". +si: simSetDef().... simMustSaveFiles is initialized to (("si.env" "text")) . +si: simSetDef().... simKnownSaveFiles is initialized to (("netlist" "netlist") +("control" "text") ("si.out" "text") ("si.log" "text") ("map/current" +"stranger") ("raw/waves" "stranger")) . +si: simSetDef().... simNotIncremental is already set to t. Redefinition to nil +is ignored. +si: simSetDef().... simReNetlistAll is initialized to "nil". +si: simSetDef().... simUnbindVars is initialized to (interactiveTAP +SilosTimeScale simActions simApplicationOptionsForm simCapFileDir simCapUnit +simCellName simCheckTermMismatchAction simCleanFileList simControlFile +simDefaultControl simDefaultSimulator simDiffInputFile simDoNetlist +simDoNotDisplayDialogBox simDoPostLayout simExceptionTerms simFlattenSchType +simHierarchyPrefix simNoLeadingHierarchyDelim simPrefixHierarchyWithCV +simGlobalPrefix simHost simHostDiffers simInitRunActions simInstNamePrefix +simInstStopListTable simInstViewListTable simInteractiveSimulatorList +simIsFlattenP simLibName simLoadNetlister simLoginName simModelNamePrefix +simNetNamePrefix simNetlistFileName simNetlistHier simNlpGlobalLibName +simNlpGlobalCellName simNlpGlobalViewName simNoSimdiff simNotIncremental +simNowRunningRemoteSimulation simOtherInfo SIMPASSWORD +simPostAnalysisProcessingFunc simPrintSilosCap simReNetlistAll simRetainFterms +simStlInputFile simSimulatorSaveFiles simSimulatorSaveVars +simSymbolModifiedAction simTermNamePrefix simTimeUnit simViewList simViewName) +. +si: simSetDef().... simUnbindFuncs is initialized to (STLsimin cat netlist +runsim sim simCatErrorFile simCheckExist simCheckHeader simCheckVariables +simCreateRemoteCommands simDateStamp simDeleteRunDirFile simDoHiloTranslation +simDoSilosTranslation simDoTaTranslation simErrHandler simExecuteWithStatus +simExecute simGetSiFileLocation simGetTermList simIfNoProcedure simin +simInitControl simInitEqivRemoteSim simInitRaw simInitRunDir simInitSimulator +simInitSpiceIncludes simIoHandler simLoadNetlisterFiles simLoadSimulatorFiles +simNoNetlist simout simout1 simPostFunc simPrintEnvironment simPrintTermList +simPrintTermListWithOption simRunDirInfile simRunDirLoad simRunDirOutfile +simRunSimdiff simRunEqivRemoteSim simRunStl simSetDef simSetDefWithNoWarn +simGetSiFileLocation) . +si: simSetDef().... simSaveVars is already set to (simLibName simCellName +simViewName simSimulator simNotIncremental simReNetlistAll simViewList +simStopList simNetlistHier nlFormatterClass nlCreateAmap nlDesignVarNameList). +Redefinition to (simLibName simCellName simViewName simSimulator +simNotIncremental simReNetlistAll) is ignored. +si: simSetDef().... simDoNotForkNetlist is initialized to "nil". +si: simSetDef().... interactiveTAP is initialized to "nil". +si: simSetDef().... simPrintSilosCap is initialized to "nil". +si: simSetDef().... simDoPostLayout is initialized to "nil". +si: simSetDef().... simDefaultControl is initialized to "control.spectre" . +si: simSetDef().... spectreBinary is initialized to "spectre" . +si: simSetDef().... simInitRunActions is initialized to (simInitControl() +(simInitSpectreIncludes) simInitRaw()) . +si: simSetDef().... simSimulatorUnbindFuncs is initialized to (spectre) . +si: simSetDef().... simSimulatorUnbindVars is initialized to (simDefaultControl +spectreBinary) . +si: simSetDef().... simNlpGlobalViewName is initialized to "spectre" . +si: simSetDef().... hnlDriverUnbindFuncs is initialized to +(hnlCellInAllStopCells hnlCloseCellFiles hnlCloseMasterList hnlDoNetBased +hnlFindAllCells hnlGenIncludeFile hnlIfNoProcedure hnlIgnoreTerm +hnlIsAStoppingCell hnlIsCellNetlistable hnlLibName hnlGetPropVal hnlGetRoundProp +hnlGetScaleCapacitance hnlGetScaleMarginalDelay hnlGetScaleTimeUnit +hnlGetSymbolPropVal hnlNetNameOnTerm hnlPrintDevices hnlPrintMacroCell +hnlPrintMessage hnlPrintNetlist hnlPrintNotNumber hnlPrintSignal hnlPrintTopCell +hnlProcInst hnlRoundProp hnlRunNetlister hnlScaleCapacitance +hnlScaleMarginalDelay hnlScaleTimeUnit hnlSetCellFiles hnlSetDef hnlSetDefNoWarn +hnlSetUpCellList hnlSetVars hnlSortTermsToNets hnlStartNetlist hnlStopNetlist +hnlStringToList hnlSubTreeInsts hnlWriteRlist hnlEMHSetupDigitalNetlistFile +hnlEMHProcTopInst hnlEMHPrintModuleHeader hnlEMHPrintInst +hnlEMHPrintModuleFooter hnlEMHPrintNetlistFooter hnlEMHProcStandardCell) . +si: simSetDef().... hnlDriverUnbindVars is initialized to (hnlAllGlobals +hnlAllSignalInCell hnlAllTermNames hnlAllTerms hnlBusCapability hnlCapability +hnlCellInputs hnlCellInTerms hnlCellNetsOnTerms hnlCellOtherTerms hnlCellOthers +hnlCellOutputs hnlModCellInputs hnlModCellOutputs hnlModCellOthers +hnlCellOutTerms hnlCellSeenList hnlCommentStr hnlCurrentCell +hnlCurrentCellViewList hnlCurrentCellPath hnlCurrentCellConfigLibname +hnlCurrentCellConfigCellname hnlCurrentCellConfigViewname hnlIsTopConfigCell +hnlCurrentInputs hnlCurrentInst hnlCurrentInstName hnlCurrentInstPort +hnlCurrentInstPortIndex hnlCurrentInstPortName hnlCurrentInTerms +hnlCurrentInTermsSize hnlCurrentIteration hnlCurrentMaster +hnlCurrentMasterViewList hnlCurrentOthers hnlCurrentOtherTerms +hnlCurrentOtherTermsSize hnlCurrentOutputs hnlCurrentOutTerms +hnlCurrentOutTermsSize hnlCurrentSignal hnlCurrentSignalName +hnlCurrentSignalTerms hnlCurrentTermsOnInst hnlCurrentType hnlDefaultSwitchViews +hnlDefaultStopViews hnlDefaultTarget hnlDriverWillPrint hnlDrvIlLoaded hnlError +hnlFormatFuncsLoaded hnlFullNetlistName hnlGlobalNetPrefix hnlGlobalParamPrefix +hnlHierarchyDelimeter hnlHierarchyDelimiter hnlIncludeFile hnlIncludeFileName +hnlIncremental hnlIncrementalDirectory hnlIncrementalMode hnlIncrementalOnly +simSupportNewConfig hnlInstBased hnlInstMasterPort hnlInstNameDifferentFrom +hnlInvalidInstNames hnlInvalidModelNames hnlInvalidNames hnlInvalidNetNames +hnlInvalidTermNames hnlInvalidParamNames hnlInvalidFunctionNames hnlLastTarget +hnlLinePostfix hnlLinePrefix hnlListOfAllCells hnlListOfAllStopCells +hnlListOfInstOnSignal hnlMacroCellFuncs hnlMapBusFirstChar hnlMapBusInName +hnlMapDirName hnlMapFileName hnlMapIfFirstChar hnlMapIfInName +hnlMapInstFirstChar hnlMapInstInName hnlMapModelFirstChar hnlMapModelInName +hnlMapNetFirstChar hnlMapNetInName hnlMapTermFirstChar hnlMapTermInName +hnlMaxInstNameLength hnlMaxLineLength hnlMaxModelNameLength hnlMaxNameLength +hnlMaxNetNameLength hnlMaxTermNameLength hnlModelNameDifferentFrom +hnlModulePrefix hnlNamePrefix hnlNetlistConfig hnlNetlistDirectory +hnlNetlistFile hnlNetlistFileList hnlNetlistFileName hnlNetNameDifferentFrom +hnlOverrideViewList hnlPreviousError hnlReNetlistAll hnlRlistString +hnlslistString hnlSoftLineLength hnlStopList hnlTarget hnlTermNameDifferentFrom +hnlParamNameDifferentFrom hnlTopCell hnlTopCellFuncs hnlViewList +hnlInvalidLineBreakChars hnlHonorLxRemoveDevice hnlCurrentSourceFilePath +hnlCurrentSourceFileModel hnlStoppingPropName hnlVerilogViewName +hnlCurrentInstHdbProps hnlCurrentInstOverCellHdbProps hnlLastInvalidInstNames +hnlLastInvalidModelNames hnlLastInvalidNames hnlLastInvalidNetNames +hnlLastInvalidTermNames hnlLastInvalidParamNames hnlLastInvalidFunctionNames +hnlLastMapBusFirstChar hnlLastMapBusInName hnlLastMapIfFirstChar +hnlLastMapIfInName hnlLastMapInstFirstChar hnlLastMapInstInName +hnlLastMapModelFirstChar hnlLastMapModelInName hnlLastMapNetFirstChar +hnlLastMapNetInName hnlLastMapTermFirstChar hnlLastMapTermInName +hnlLastTermNameDifferentFrom hnlLastParamNameDifferentFrom +hnlLastMapParamFirstChar hnlLastMapParamInName hnlEMH) . +si: simSetDef().... simTermNamePrefix is initialized to "nil". +si: simSetDef().... simParamNamePrefix is already set to "_par". Redefinition to +nil is ignored. +si: simSetDef().... hnlCellOutputs is initialized to "nil". +si: simSetDef().... hnlModCellOutputs is initialized to "nil". +si: simSetDef().... hnlCellInputs is initialized to "nil". +si: simSetDef().... hnlModCellInputs is initialized to "nil". +si: simSetDef().... hnlCellOthers is initialized to "nil". +si: simSetDef().... hnlModCellOthers is initialized to "nil". +si: simSetDef().... hnlCellOutTerms is initialized to "nil". +si: simSetDef().... hnlCellInTerms is initialized to "nil". +si: simSetDef().... hnlCellOtherTerms is initialized to "nil". +si: simSetDef().... hnlCellNetsOnTerms is initialized to "nil". +si: simSetDef().... hnlCurrentOutputs is initialized to "nil". +si: simSetDef().... hnlCurrentInputs is initialized to "nil". +si: simSetDef().... hnlCurrentOthers is initialized to "nil". +si: simSetDef().... hnlCurrentType is initialized to "nil". +si: simSetDef().... hnlCurrentInst is initialized to "nil". +si: simSetDef().... hnlCurrentInstName is initialized to "nil". +si: simSetDef().... hnlCurrentMaster is initialized to "nil". +si: simSetDef().... hnlCurrentIteration is initialized to "nil". +si: simSetDef().... hnlCurrentCell is initialized to "nil". +si: simSetDef().... hnlCurrentCellViewList is initialized to "nil". +si: simSetDef().... hnlCurrentCellPath is initialized to "nil". +si: simSetDef().... hnlCurrentCellConfigLibname is initialized to "nil". +si: simSetDef().... hnlCurrentCellConfigCellname is initialized to "nil". +si: simSetDef().... hnlCurrentCellConfigViewname is initialized to "nil". +si: simSetDef().... hnlIsTopConfigCell is initialized to "nil". +si: simSetDef().... hnlCurrentMasterViewList is initialized to "nil". +si: simSetDef().... hnlCurrentMasterPathString is initialized to "nil". +si: simSetDef().... hnlCurrentMasterConfigLibName is initialized to "nil". +si: simSetDef().... hnlCurrentMasterConfigCellName is initialized to "nil". +si: simSetDef().... hnlCurrentMasterConfigViewName is initialized to "nil". +si: simSetDef().... hnlCurrentMasterIsTopCellConfig is initialized to "nil". +si: simSetDef().... hnlOverrideViewList is initialized to "" . +si: simSetDef().... hnlCurrentTermsOnInst is initialized to "nil". +si: simSetDef().... hnlCurrentOutTerms is initialized to "nil". +si: simSetDef().... hnlCurrentInTerms is initialized to "nil". +si: simSetDef().... hnlCurrentOtherTerms is initialized to "nil". +si: simSetDef().... hnlCurrentOutTermsSize is initialized to "nil". +si: simSetDef().... hnlCurrentInTermsSize is initialized to "nil". +si: simSetDef().... hnlCurrentOtherTermsSize is initialized to "nil". +si: simSetDef().... hnlTopCell is initialized to "nil". +si: simSetDef().... hnlAllGlobals is initialized to "nil". +si: simSetDef().... hnlInvalidNames is initialized to "nil". +si: simSetDef().... hnlInvalidNetNames is already set to (("gnd!" "0") ("0" +"_0") "M_1_PI" "M_2_PI" "M_2_SQRTPI" "M_DEGPERRAD" "M_E" "M_LN10" "M_LN2" +"M_LOG10E" "M_LOG2E" "M_PI" "M_PI_2" "M_PI_4" "M_SQRT1_2" "M_SQRT2" "M_TWO_PI" +"P_C" "P_CELSIUS0" "P_EPS0" "P_H" "P_K" "P_Q" "P_U0" "abs" "acos" "acosh" "asin" +"asinh" "atan" "atan2" "atanh" "cos" "cosh" "exp" "hypot" "log" "log10" "max" +"min" "pow" "sin" "sinh" "sqrt" "tan" "tanh" "ceil" "floor" "fmod" "altergroup" +"calculate" "correlate" "else" "end" "ends" "for" "global" "ic" "if" "inline" +"local" "march" "mismatch" "model" "nodeset" "output" "parameters" "paramset" +"plot" "print" "process" "save" "sens" "statistics" "subckt" "to" "truncate" +"vary" "temp" "tnom" "scalem" "scale" "export" "int" "library" "function" +"endfunction" "real" "integer" "input" "return" "FUNCTION" "montecarlo" "pwr" +"analogmodel" "protect" "PROTECT" "prot" "PROT" "0"). Redefinition to nil is +ignored. +si: simSetDef().... hnlInvalidInstNames is already set to ("M_1_PI" "M_2_PI" +"M_2_SQRTPI" "M_DEGPERRAD" "M_E" "M_LN10" "M_LN2" "M_LOG10E" "M_LOG2E" "M_PI" +"M_PI_2" "M_PI_4" "M_SQRT1_2" "M_SQRT2" "M_TWO_PI" "P_C" "P_CELSIUS0" "P_EPS0" +"P_H" "P_K" "P_Q" "P_U0" "abs" "acos" "acosh" "asin" "asinh" "atan" "atan2" +"atanh" "cos" "cosh" "exp" "hypot" "log" "log10" "max" "min" "pow" "sin" "sinh" +"sqrt" "tan" "tanh" "ceil" "floor" "fmod" "altergroup" "calculate" "correlate" +"else" "end" "ends" "for" "global" "ic" "if" "inline" "local" "march" "mismatch" +"model" "nodeset" "output" "parameters" "paramset" "plot" "print" "process" +"save" "sens" "statistics" "subckt" "to" "truncate" "vary" "temp" "tnom" +"scalem" "scale" "export" "int" "library" "function" "endfunction" "real" +"integer" "input" "return" "FUNCTION" "montecarlo" "pwr" "analogmodel" "protect" +"PROTECT" "prot" "PROT"). Redefinition to nil is ignored. +si: simSetDef().... hnlInvalidModelNames is already set to ("M_1_PI" "M_2_PI" +"M_2_SQRTPI" "M_DEGPERRAD" "M_E" "M_LN10" "M_LN2" "M_LOG10E" "M_LOG2E" "M_PI" +"M_PI_2" "M_PI_4" "M_SQRT1_2" "M_SQRT2" "M_TWO_PI" "P_C" "P_CELSIUS0" "P_EPS0" +"P_H" "P_K" "P_Q" "P_U0" "abs" "acos" "acosh" "asin" "asinh" "atan" "atan2" +"atanh" "cos" "cosh" "exp" "hypot" "log" "log10" "max" "min" "pow" "sin" "sinh" +"sqrt" "tan" "tanh" "ceil" "floor" "fmod" "altergroup" "calculate" "correlate" +"else" "end" "ends" "for" "global" "ic" "if" "inline" "local" "march" "mismatch" +"model" "nodeset" "output" "parameters" "paramset" "plot" "print" "process" +"save" "sens" "statistics" "subckt" "to" "truncate" "vary" "temp" "tnom" +"scalem" "scale" "export" "int" "library" "function" "endfunction" "real" +"integer" "input" "return" "FUNCTION" "montecarlo" "pwr" "analogmodel" "protect" +"PROTECT" "prot" "PROT"). Redefinition to nil is ignored. +si: simSetDef().... hnlInvalidTermNames is initialized to "nil". +si: simSetDef().... hnlInvalidParamNames is already set to ("altergroup" +"calculate" "correlate" "else" "end" "ends" "for" "global" "ic" "if" "inline" +"local" "march" "mismatch" "model" "nodeset" "output" "parameters" "paramset" +"plot" "print" "process" "save" "sens" "statistics" "subckt" "to" "truncate" +"vary" "temp" "tnom" "scalem" "scale" "export" "int" "library" "function" +"endfunction" "real" "integer" "input" "return" "FUNCTION" "montecarlo" "pwr" +"analogmodel" "protect" "PROTECT" "prot" "PROT" "abs" "acos" "acosh" "asin" +"asinh" "atan" "atan2" "atanh" "cos" "cosh" "exp" "hypot" "log" "log10" "max" +"min" "pow" "sin" "sinh" "sqrt" "tan" "tanh" "ceil" "floor" "fmod" "absin" +"absolute" "absout" "all" "allglobal" "alllocal" "allpub" "autodc" "awb" +"backward" "bert" "bilinear" "both" "breakdown" "brief" "brk" "bsim" "bulk" +"cdsspice" "child" "continue" "correlations" "conservative" "dc" "debug" "delta" +"detailed" "dev" "diff" "dptran" "eng" "error" "euler" "exp" "fatal" "file" +"finish" "float" "forward" "full" "fwd" "gear2" "gear2only" "gmin" "gnd" +"hspice" "in" "indifferent" "input" "insist" "inst" "inversez" "isdb" "lateral" +"liberal" "list" "log" "logfile" "lvl" "lvlpub" "max_only" "max_v_only" "meyer" +"min" "mismatch" "models" "moderate" "n" "no" "node" "nodes" +"nodes_and_terminals" "none" "nonlinear" "normal" "nowhere" "npn" "npnv" +"nutascii" "nutbin" "off" "on" "only" "oppoint" "out" "output" "overlap" +"override" "p" "parent" "pnp" "pnpl" "pnpv" "pointlocal" "poly" "process" +"psfascii" "psfbin" "ptran" "pulse" "pwl" "quit" "rampup" "rawfile" "relative" +"rev" "sat" "sci" "screen" "selected" "sigglobal" "sine" "source" "sources" +"spectre" "spice" "spice2" "spice3" "spiceplus" "status" "std" "steps" "subth" +"subthresh" "suggest" "sum" "sweep" "tabular" "tc" "terminals" "timedomain" +"title" "trap" "trapgear2" "traponly" "triode" "turbo" "vertical" "vt" "warning" +"waveless" "wsfascii" "wsfbin" "yang" "yes" "z"). Redefinition to nil is +ignored. +si: simSetDef().... hnlInvalidFunctionNames is initialized to "nil". +si: simSetDef().... hnlInvalidLineBreakChars is already set to ("*" "+"). +Redefinition to nil is ignored. +si: simSetDef().... hnlMapIfFirstChar is initialized to "nil". +si: simSetDef().... hnlMapIfInName is initialized to "nil". +si: simSetDef().... hnlMapNetFirstChar is already set to (("." "_") ("0" "_0") +("1" "_1") ("2" "_2") ("3" "_3") ("4" "_4") ("5" "_5") ("6" "_6") ("7" "_7") +("8" "_8") ("9" "_9") ("!" "\\!") ("@" "\\@") ("#" "\\#") ("$" "\\$") ("%" +"\\%") ("^" "\\^") ("&" "\\&") ("*" "\\*") ("(" "\\(") (")" "\\)") ("\\" "\\\\") +("|" "\\|") ("+" "\\+") ("-" "\\-") ("=" "\\=") ("{" "\\{") ("}" "\\}") ("[" +"\\[") ("]" "\\]") ("\"" "\\\"") ("'" "\\'") (":" "\\:") (";" "\\;") ("~" "\\~") +("`" "\\`") ("<" "\\<") ("," "\\,") (">" "\\>") ("?" "\\?") ("/" "\\/")). +Redefinition to nil is ignored. +si: simSetDef().... hnlMapNetInName is already set to ((">" "") ("<" "_") ("." +"_") ("#" "\\#") ("$" "\\$") ("%" "\\%") ("^" "\\^") ("&" "\\&") ("*" "\\*") +("(" "\\(") (")" "\\)") ("\\" "\\\\") ("|" "\\|") ("+" "\\+") ("-" "\\-") ("=" +"\\=") ("{" "\\{") ("}" "\\}") ("[" "\\[") ("]" "\\]") ("\"" "\\\"") ("'" "\\'") +(":" "\\:") (";" "\\;") ("~" "\\~") ("`" "\\`") ("," "\\,") ("?" "\\?") ("/" +"\\/") ("@" "\\@")). Redefinition to nil is ignored. +si: simSetDef().... hnlMapInstFirstChar is already set to (("." "_") ("0" "_0") +("1" "_1") ("2" "_2") ("3" "_3") ("4" "_4") ("5" "_5") ("6" "_6") ("7" "_7") +("8" "_8") ("9" "_9") ("!" "\\!") ("@" "\\@") ("#" "\\#") ("$" "\\$") ("%" +"\\%") ("^" "\\^") ("&" "\\&") ("*" "\\*") ("(" "\\(") (")" "\\)") ("\\" "\\\\") +("|" "\\|") ("+" "\\+") ("-" "\\-") ("=" "\\=") ("{" "\\{") ("}" "\\}") ("[" +"\\[") ("]" "\\]") ("\"" "\\\"") ("'" "\\'") (":" "\\:") (";" "\\;") ("~" "\\~") +("`" "\\`") ("<" "\\<") ("," "\\,") (">" "\\>") ("?" "\\?") ("/" "\\/")). +Redefinition to nil is ignored. +si: simSetDef().... hnlMapInstInName is already set to ((">" "") ("<" "_") ("." +"_") ("#" "\\#") ("$" "\\$") ("%" "\\%") ("^" "\\^") ("&" "\\&") ("*" "\\*") +("(" "\\(") (")" "\\)") ("\\" "\\\\") ("|" "\\|") ("+" "\\+") ("-" "\\-") ("=" +"\\=") ("{" "\\{") ("}" "\\}") ("[" "\\[") ("]" "\\]") ("\"" "\\\"") ("'" "\\'") +(":" "\\:") (";" "\\;") ("~" "\\~") ("`" "\\`") ("," "\\,") ("?" "\\?") ("/" +"\\/") ("@" "\\@")). Redefinition to nil is ignored. +si: simSetDef().... hnlMapModelFirstChar is already set to ("." "0" "1" "2" "3" +"4" "5" "6" "7" "8" "9" "!" "@" "#" "$" "%" "^" "&" "*" "(" ")" "\\" "|" "+" "-" +"=" "{" "}" "[" "]" "\"" "'" ":" ";" "~" "`" "<" "," ">" "?" "/"). Redefinition +to nil is ignored. +si: simSetDef().... hnlMapModelInName is already set to ((">" "") ("<" "_") "." +"#" "$" "%" "^" "&" "*" "(" ")" "\\" "|" "+" "-" "=" "{" "}" "[" "]" "\"" "'" +":" ";" "~" "`" "," "?" "/" "@"). Redefinition to nil is ignored. +si: simSetDef().... hnlMapTermInName is initialized to "nil". +si: simSetDef().... hnlMapTermFirstChar is initialized to "nil". +si: simSetDef().... hnlMapParamInName is initialized to "nil". +si: simSetDef().... hnlMapParamFirstChar is initialized to "nil". +si: simSetDef().... hnlMapBusInName is initialized to "nil". +si: simSetDef().... hnlMapBusFirstChar is initialized to "nil". +si: simSetDef().... hnlViewList is initialized to "nil". +si: simSetDef().... hnlStopList is initialized to "nil". +si: simSetDef().... hnlError is initialized to "nil". +si: simSetDef().... hnlPreviousError is initialized to "nil". +si: simSetDef().... hnlListOfAllStopCells is initialized to "nil". +si: simSetDef().... hnlListOfAllCells is initialized to "nil". +si: simSetDef().... hnlNetlistFile is initialized to "nil". +si: simSetDef().... hnlNetlistFileName is initialized to "netlist" . +si: simSetDef().... hnlMapDirName is initialized to "map" . +si: simSetDef().... hnlMapFileName is initialized to "current" . +si: simSetDef().... hnlNamePrefix is initialized to "hnl_" . +si: simSetDef().... hnlBusNamePrefix is initialized to "BUS" . +si: simSetDef().... hnlDriverWillPrint is initialized to "nil". +si: simSetDef().... hnlLinePrefix is already set to " ". Redefinition to +nil is ignored. +si: simSetDef().... hnlLinePostfix is already set to " \\". Redefinition to nil +is ignored. +si: simSetDef().... hnlCommentStr is already set to "//". Redefinition to nil is +ignored. +si: simSetDef().... hnlSoftLineLength is already set to 75. Redefinition to nil +is ignored. +si: simSetDef().... hnlFormatFuncsLoaded is initialized to "nil". +si: simSetDef().... hnlDrvIlLoaded is initialized to "nil". +si: simSetDef().... hnlInstBased is initialized to t . +si: simSetDef().... hnlLastTarget is initialized to "nil". +si: simSetDef().... hnlFullNetlistName is initialized to "netlist" . +si: simSetDef().... hnlNetlistDirectory is initialized to "nil". +si: simSetDef().... hnlFullMasterName is initialized to "nil". +si: simSetDef().... hnlIncremental is initialized to "nil". +si: simSetDef().... hnlIncrementalOnly is initialized to "nil". +si: simSetDef().... simSupportNewConfig is already set to t. Redefinition to nil +is ignored. +si: simSetDef().... hnlIncrementalMode is initialized to "nil". +si: simSetDef().... hnlReNetlistAll is initialized to "nil". +si: simSetDef().... hnlModulePrefix is already set to "_sub". Redefinition to +nil is ignored. +si: simSetDef().... hnlGlobalNetPrefix is already set to "_gnet". Redefinition +to nil is ignored. +si: simSetDef().... hnlGlobalParamPrefix is already set to "_gpar". Redefinition +to nil is ignored. +si: simSetDef().... hnlIncludeFileName is initialized to "netlist" . +si: simSetDef().... hnlIncludeFile is initialized to "nil". +si: simSetDef().... hnlNetlistFileList is initialized to "nil". +si: simSetDef().... hnlIncrementalDirectory is initialized to "ihnl" . +si: simSetDef().... hnlCurrentInstPortName is initialized to "nil". +si: simSetDef().... hnlCurrentInstPortIndex is initialized to 0 . +si: simSetDef().... hnlCurrentInstPort is initialized to "nil". +si: simSetDef().... hnlInstMasterPort is initialized to "nil". +si: simSetDef().... hnlAllTerms is initialized to "nil". +si: simSetDef().... hnlAllTermNames is initialized to "nil". +si: simSetDef().... hnlAllSignalInCell is initialized to "nil". +si: simSetDef().... hnlCurrentSignal is initialized to "nil". +si: simSetDef().... hnlCurrentSignalName is initialized to "nil". +si: simSetDef().... hnlSignalTerms is initialized to "nil". +si: simSetDef().... hnlListOffInstOnSignal is initialized to "nil". +si: simSetDef().... hnlNetBased is initialized to "nil". +si: simSetDef().... hnlRlistString is initialized to "nil". +si: simSetDef().... hnlNetlistConfig is initialized to "nil". +si: simSetDef().... hnlTopCellFuncs is initialized to ("hnlSetCellFiles()" +"hnlPrintTopCellHeader()" "hnlPrintDevices()" "hnlPrintTopCellFooter()" +"hnlCloseCellFiles()") . +si: simSetDef().... hnlMacroCellFuncs is initialized to ("hnlSetCellFiles()" +"hnlPrintDeviceHeader()" "hnlPrintPorts()" "hnlPrintDevices()" +"hnlPrintDeviceFooter()" "hnlCloseCellFiles()") . +si: simSetDef().... hnlTopCellNetFuncs is initialized to +("hnlPrintTopCellHeader()" "hnlPrintSignal()" "hnlPrintTopCellFooter()") . +si: simSetDef().... hnlMacroCellNetFuncs is initialized to +("hnlPrintDeviceHeader()" "hnlPrintPorts()" "hnlPrintSignal()" +"hnlPrintDeviceFooter()") . +si: simSetDef().... hnlFormatterUnbindFuncs is initialized to +(hnlPrintNetlistHeader hnlPrintNetlistFooter hnlSetOutputVars +hnlPrintTopCellHeader hnlPrintTopCellFooter hnlPrintPorts hnlPrintDeviceHeader +hnlPrintDeviceFooter hnlPrintInst) . +Loading the file +'/home/eda_tools/Cadence/IC616ISR9/tools.lnx86/dfII/etc/skill/hnl/spectre.ile'.Loading the file +'/home/eda_tools/Cadence/IC616ISR9/tools.lnx86/dfII/etc/skill/hnl/driver.ile'.Begin Incremental Netlisting May 27 02:13:04 2021 +End netlisting May 27 02:13:05 2021 diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..6cf3f30fa189adfe5eced07a7db28fa8e4729e39 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,3187 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:13:06 AM, Thur May 27, 2021 +# Number of equations = 2262 +1\:gnd! 3.53287619624928e-06 +1\:vdd! 1.79999750675444 +1\:X0 1.80000036265425 +1\:X1 1.80000012982349 +1\:X2 1.79999990660507 +1\:X3 1.79999983276205 +1\:Y2 8.4879459392545e-08 +1\:Y3 -1.1349571518175e-06 +1\:Z0 6.34936389098127e-06 +1\:Z1 4.16677564982639e-05 +1\:Z2 4.41166236043092e-05 +1\:Z3 4.1965229827176e-05 +1\:Z4 4.24266478736812e-05 +1\:Z5 5.7565329179302e-05 +1\:Z6 5.4993283742779e-05 +1\:Z7 5.53809092457756e-06 +2\:gnd! 5.79462736546004e-06 +2\:I0|I3|Ai 1.79999598223338 +2\:I0|I3|Bi 1.80000019814743 +2\:I0|I4|Ai 1.79999340958829 +2\:I0|I4|Bi 1.79999592949779 +2\:I0|net1 1.79999425295971 +2\:I0|net3 4.20815478137186e-05 +2\:I0|net6 1.79999825781516 +2\:I1|I3|Ai 1.79999666586459 +2\:I1|I3|Bi 1.79999620735487 +2\:I1|I4|Ai 1.80000070108005 +2\:I1|I4|Bi 1.79999834260394 +2\:I1|net1 1.79999247618588 +2\:I1|net3 4.25618756494125e-05 +2\:I1|net6 1.80000184867704 +2\:I2|I3|Ai 1.80001101104686 +2\:I2|I3|Bi 1.79999545441425 +2\:I2|I4|Ai 1.79999533547808 +2\:I2|I4|Bi 1.80003917294541 +2\:I2|net1 1.79999809736597 +2\:I2|net3 5.60025351062618e-05 +2\:I2|net6 1.7999977930094 +2\:I3|I3|Ai 1.79998546470956 +2\:I3|I3|Bi 1.79999030095465 +2\:I3|I4|Ai 1.79999576222085 +2\:I3|I4|Bi 1.79999668776646 +2\:I3|net1 1.79999728414606 +2\:I3|net3 4.09739328056919e-05 +2\:I3|net6 1.79999332048463 +2\:I4|I3|Ai 1.7999981133702 +2\:I4|I3|Bi 1.79994068985926 +2\:I4|I4|Ai 1.79999495965484 +2\:I4|I4|Bi 1.79998651154378 +2\:I4|net1 1.79999772639266 +2\:I4|net3 4.98221610764297e-05 +2\:I4|net6 1.79999892736744 +2\:I5|I1|Ai 1.79999402462341 +2\:I5|I1|Bi 1.79998841642208 +2\:I5|I3|net013 1.80000263244432 +2\:I6|I1|Ai 1.79999864065645 +2\:I6|I1|Bi 1.7999952449899 +2\:I6|I3|net013 1.80000207021128 +2\:I7|I1|Ai 1.79999339255923 +2\:I7|I1|Bi 1.79999141654681 +2\:I7|I3|net013 1.79999732500425 +2\:I8|I1|Ai 1.80005551264158 +2\:I8|I1|Bi 1.79995840121024 +2\:I8|I3|net013 1.80000347710163 +2\:I9|I3|Ai 1.79997696428556 +2\:I9|I3|Bi 1.79994544191022 +2\:I9|I4|Ai 1.7999931008988 +2\:I9|I4|Bi 1.79998509574464 +2\:I9|net1 1.7999966640749 +2\:I9|net3 5.17889388124498e-05 +2\:I9|net6 1.79999672869149 +2\:I10|I3|Ai 1.79997289621193 +2\:I10|I3|Bi 1.79996034218227 +2\:I10|I4|Ai 1.7999834905451 +2\:I10|I4|Bi 1.79999251890708 +2\:I10|net1 1.79999275843965 +2\:I10|net3 2.22523159481056e-05 +2\:I10|net6 1.79999539251618 +2\:I11|I3|Ai 1.7999957410036 +2\:I11|I3|Bi 1.79999957625757 +2\:I11|I4|Ai 1.79999508985084 +2\:I11|I4|Bi 1.79999673778273 +2\:I11|net1 1.79999913967203 +2\:I11|net3 5.24945264054153e-05 +2\:I11|net6 1.79999870977353 +2\:I12|net013 1.79996590363653 +2\:I13|net013 1.79996562596003 +2\:I14|net013 1.79996810329913 +2\:I15|net013 1.79999984599209 +2\:I16|net013 1.79996846451143 +2\:I17|net013 1.79999932428725 +2\:I18|net013 1.79999939494978 +2\:I19|net013 1.79996914921805 +2\:I20|net013 1.79996795120626 +2\:I21|net013 1.79999866589867 +2\:I22|net013 1.79996490218055 +2\:I23|net013 1.79999716841405 +2\:I24|net013 1.79999824728325 +2\:I25|net013 1.79996555698658 +2\:I26|net013 1.79999866546694 +2\:I27|net013 1.79996785195509 +2\:net1 -4.73210186472122e-06 +2\:net5 8.06127557557039e-06 +2\:net8 2.77130598369111e-06 +2\:net13 3.51661560566765e-06 +2\:net15 8.17671082615217e-06 +2\:net16 2.53621903668636e-06 +2\:net17 6.37041323437581e-05 +2\:net19 -5.28843345300713e-07 +2\:net21 2.92696860142502e-06 +2\:net26 1.98140772243495e-06 +2\:net28 8.09339363950094e-08 +2\:net29 4.40221423604452e-05 +2\:net31 1.41424666637185e-07 +2\:net32 4.58254310004671e-05 +2\:net34 2.2699632768514e-06 +2\:net35 1.41529020234098e-05 +2\:net38 -1.26668953680569e-06 +2\:net39 7.26818705155646e-07 +2\:net44 2.96180225697625e-05 +2\:net45 1.36937022602391e-06 +2\:net47 -4.70730630904236e-06 +2\:net54 4.1292710299106e-05 +2\:net55 -1.83354008556992e-06 +2\:net075 -3.06511877851792e-06 +2\:net078 3.58527056139233e-06 +2\:net087 9.31288188089861e-07 +2\:net090 5.43901093971169e-07 +2\:net093 -7.3637711992823e-06 +2\:net095 -4.868559630522e-06 +2\:net0100 4.65625327720425e-05 +2\:net0115 5.34928444245237e-06 +2\:net0127 -2.83585199378705e-06 +2\:vdd! 1.79999681606739 +2\:X0 1.80000040977036 +2\:X1 1.8000001299501 +2\:X2 1.79999985546447 +2\:X3 1.79999983255116 +2\:Y1 4.6660882294964e-07 +2\:Y2 7.55974540801154e-08 +2\:Y3 -1.28277219702168e-06 +2\:Z0 5.01247560347506e-06 +2\:Z1 4.21975352713535e-05 +2\:Z2 4.32455437753264e-05 +2\:Z3 4.01417626893194e-05 +2\:Z4 4.15832948116645e-05 +2\:Z5 5.70410209932381e-05 +2\:Z6 5.53853244080963e-05 +2\:Z7 5.38828658570261e-06 +3\:gnd! 6.12881134256057e-06 +3\:I0|I3|Ai 1.79999588913853 +3\:I0|I3|Bi 1.79999890148396 +3\:I0|I4|Ai 1.79999650759952 +3\:I0|I4|Bi 1.80000010230872 +3\:I0|net1 1.79999874237457 +3\:I0|net3 4.21609623619096e-05 +3\:I0|net6 1.79999592636461 +3\:I1|I3|Ai 1.79999915344009 +3\:I1|I3|Bi 1.79999620855802 +3\:I1|I4|Ai 1.8000010057914 +3\:I1|I4|Bi 1.79999833869804 +3\:I1|net1 1.80001063232326 +3\:I1|net3 5.08053820551761e-05 +3\:I1|net6 1.80000233723441 +3\:I2|I3|Ai 1.79999337140932 +3\:I2|I3|Bi 1.79999546871599 +3\:I2|I4|Ai 1.79999535928594 +3\:I2|I4|Bi 1.80003946268994 +3\:I2|net1 1.80000897787886 +3\:I2|net3 4.94435087053974e-05 +3\:I2|net6 1.79999748866226 +3\:I3|I3|Ai 1.7999829478465 +3\:I3|I3|Bi 1.8000063696509 +3\:I3|I4|Ai 1.79999511342055 +3\:I3|I4|Bi 1.79999714142948 +3\:I3|net1 1.79999751868245 +3\:I3|net3 4.20151048691346e-05 +3\:I3|net6 1.80007507048786 +3\:I4|I3|Ai 1.79999759320314 +3\:I4|I3|Bi 1.80003641111971 +3\:I4|I4|Ai 1.79999457466235 +3\:I4|I4|Bi 1.80000959617899 +3\:I4|net1 1.7999980904261 +3\:I4|net3 4.9947017777245e-05 +3\:I4|net6 1.79999329064878 +3\:I5|I1|Ai 1.79999858943775 +3\:I5|I1|Bi 1.79998793731426 +3\:I5|I3|net013 1.80000772046181 +3\:I6|I1|Ai 1.7999969792191 +3\:I6|I1|Bi 1.79999846285615 +3\:I6|I3|net013 1.80000249600642 +3\:I7|I1|Ai 1.7999884170381 +3\:I7|I1|Bi 1.7999929403434 +3\:I7|I3|net013 1.79999340614087 +3\:I8|I1|Ai 1.79970562284857 +3\:I8|I1|Bi 1.79995701621126 +3\:I8|I3|net013 1.80001135006716 +3\:I9|I3|Ai 1.79997329351149 +3\:I9|I3|Bi 1.80002979892422 +3\:I9|I4|Ai 1.79999420117365 +3\:I9|I4|Bi 1.79999275284841 +3\:I9|net1 1.79999822455033 +3\:I9|net3 5.22080526160697e-05 +3\:I9|net6 1.79999782294826 +3\:I10|I3|Ai 1.79997442273814 +3\:I10|I3|Bi 1.80000083872725 +3\:I10|I4|Ai 1.79999600409159 +3\:I10|I4|Bi 1.80008699311673 +3\:I10|net1 1.79999505102246 +3\:I10|net3 2.30047475385647e-05 +3\:I10|net6 1.80008761588546 +3\:I11|I3|Ai 1.79999250740555 +3\:I11|I3|Bi 1.79999956295925 +3\:I11|I4|Ai 1.79999508914883 +3\:I11|I4|Bi 1.79999674581522 +3\:I11|net1 1.79999955321331 +3\:I11|net3 3.06042774572675e-05 +3\:I11|net6 1.79999753882379 +3\:I12|net013 1.79996532304942 +3\:I13|net013 1.79996519684379 +3\:I14|net013 1.79996840703199 +3\:I15|net013 1.79999990857233 +3\:I16|net013 1.79996875454791 +3\:I17|net013 1.79999932117085 +3\:I18|net013 1.79999925707236 +3\:I19|net013 1.79996954687093 +3\:I20|net013 1.79996827791651 +3\:I21|net013 1.79999849000871 +3\:I22|net013 1.79996235039538 +3\:I23|net013 1.79999694606136 +3\:I24|net013 1.79999545749582 +3\:I25|net013 1.79996198706947 +3\:I26|net013 1.799998523494 +3\:I27|net013 1.79996828496226 +3\:net1 3.95726983300072e-05 +3\:net5 8.15215267973281e-06 +3\:net8 2.67107364910568e-06 +3\:net13 -3.10663260028162e-06 +3\:net15 7.2856220393315e-06 +3\:net16 3.05397733512411e-06 +3\:net17 6.72266556922647e-05 +3\:net19 8.43622928657621e-07 +3\:net21 2.89269928300039e-06 +3\:net26 1.32422828554985e-05 +3\:net28 5.3850375599606e-06 +3\:net29 4.38776894563777e-05 +3\:net31 -1.24035199953761e-07 +3\:net32 4.56799011885975e-05 +3\:net34 2.08531699639015e-06 +3\:net35 -3.75209079846224e-06 +3\:net38 -4.28496566021269e-06 +3\:net39 2.69632405564091e-06 +3\:net44 3.0014616408596e-05 +3\:net45 -4.36632310870939e-06 +3\:net47 7.60623648226303e-06 +3\:net54 4.09182895837588e-05 +3\:net55 6.3029562413521e-07 +3\:net075 2.66651654642605e-05 +3\:net078 3.02883547778033e-06 +3\:net087 9.55876181872529e-08 +3\:net090 -6.15070002916367e-06 +3\:net093 -1.07084119599173e-05 +3\:net095 -6.91793545492979e-09 +3\:net0100 4.66254991726375e-05 +3\:net0115 4.54531020045667e-06 +3\:net0127 -1.48087995498553e-06 +3\:vdd! 1.79999492622072 +3\:X0 1.80000141194484 +3\:X1 1.80000007799839 +3\:X2 1.79999999872376 +3\:X3 1.80000014129319 +3\:Y1 1.09528446201714e-06 +3\:Y2 -6.78886898947171e-08 +3\:Y3 -4.21668319244204e-06 +3\:Z0 4.58249046699281e-06 +3\:Z1 4.24809706412381e-05 +3\:Z2 4.31690574866719e-05 +3\:Z3 3.98028482141648e-05 +3\:Z4 4.22451838695941e-05 +3\:Z5 5.69464629228514e-05 +3\:Z6 5.51001142488706e-05 +3\:Z7 6.44243268437664e-06 +4\:gnd! 6.82862666895292e-06 +4\:I0|I3|Ai 1.79999602289348 +4\:I0|I3|Bi 1.80000292470995 +4\:I0|I4|Ai 1.79999901873193 +4\:I0|I4|Bi 1.79996936069167 +4\:I0|net1 1.79999423928402 +4\:I0|net3 4.23721592547804e-05 +4\:I0|net6 1.79999779124789 +4\:I1|I3|Ai 1.79999666610647 +4\:I1|I3|Bi 1.79999737917191 +4\:I1|I4|Ai 1.80000062668165 +4\:I1|I4|Bi 1.79999848829715 +4\:I1|net1 1.80000807949325 +4\:I1|net3 4.23598545878062e-05 +4\:I1|net6 1.80000183624445 +4\:I2|I3|Ai 1.80001113235846 +4\:I2|I3|Bi 1.79999577412885 +4\:I2|I4|Ai 1.80000539265303 +4\:I2|I4|Bi 1.80003808760529 +4\:I2|net1 1.8000013479315 +4\:I2|net3 5.87891246994796e-05 +4\:I2|net6 1.7999978862494 +4\:I3|I3|Ai 1.79998663722818 +4\:I3|I3|Bi 1.79999826021449 +4\:I3|I4|Ai 1.79999543098377 +4\:I3|I4|Bi 1.79999400719612 +4\:I3|net1 1.79999735179111 +4\:I3|net3 4.26054264153765e-05 +4\:I3|net6 1.8000026014894 +4\:I4|I3|Ai 1.79999849873813 +4\:I4|I3|Bi 1.79999337309037 +4\:I4|I4|Ai 1.79999659445217 +4\:I4|I4|Bi 1.80001023242085 +4\:I4|net1 1.79999780359386 +4\:I4|net3 5.20442808692627e-05 +4\:I4|net6 1.79999696399699 +4\:I5|I1|Ai 1.79999530785061 +4\:I5|I1|Bi 1.79998866702416 +4\:I5|I3|net013 1.79998953320635 +4\:I6|I1|Ai 1.79999927538615 +4\:I6|I1|Bi 1.79997695015101 +4\:I6|I3|net013 1.80000710980638 +4\:I7|I1|Ai 1.79999396740103 +4\:I7|I1|Bi 1.79999190987337 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1.27396631099627 +I14|MN1:int_s 1.79997001809553 +I14|MN2:int_d 8.15753487509069e-07 +I14|MN2:int_s -7.36825524442288e-06 +I14|MP0:int_d 1.79999896787622 +I14|MP0:int_s 1.79996597461065 +I14|MP1:int_d 1.79996807468079 +I14|MP1:int_s 1.79999752047266 +I14|MP2:int_d -8.46345782122883e-06 +I14|MP2:int_s 1.79999787155003 +I14|net9 1.27396553525372 +I14|net013 1.799968080638 +I15|MN0:int_d 3.80315240980092e-06 +I15|MN0:int_s 1.8000002405112 +I15|MN1:int_d 5.69655308472046e-06 +I15|MN1:int_s 3.2731752622761e-06 +I15|MN2:int_d 1.04437462952997e-06 +I15|MN2:int_s 5.07739739317537e-06 +I15|MP0:int_d 1.79999914860911 +I15|MP0:int_s 1.80000107087325 +I15|MP1:int_d 1.80000041616474 +I15|MP1:int_s 1.80000001295531 +I15|MP2:int_d 9.48882757984125e-06 +I15|MP2:int_s 1.79999958329969 +I15|net9 3.53816383603851e-06 +I15|net013 1.79999984960877 +I16|MN0:int_d -6.00143299330932e-07 +I16|MN0:int_s 1.27397348318449 +I16|MN1:int_d 1.27397183719536 +I16|MN1:int_s 1.79997029296298 +I16|MN2:int_d 4.79329860138471e-06 +I16|MN2:int_s -7.60108591873226e-06 +I16|MP0:int_d 1.79999925132764 +I16|MP0:int_s 1.79996703203887 +I16|MP1:int_d 1.79996793066113 +I16|MP1:int_s 1.79999892649637 +I16|MP2:int_d -1.7521919663805e-05 +I16|MP2:int_s 1.80000044834624 +I16|net9 1.27397266018993 +I16|net013 1.79996843383737 +I17|MN0:int_d 3.62625140855475e-06 +I17|MN0:int_s 1.79999930464078 +I17|MN1:int_d 4.28457701474096e-06 +I17|MN1:int_s 3.28756415813406e-06 +I17|MN2:int_d 1.49383259879723e-06 +I17|MN2:int_s 4.57858543195256e-06 +I17|MP0:int_d 1.79999893156046 +I17|MP0:int_s 1.79999808148843 +I17|MP1:int_d 1.7999975944451 +I17|MP1:int_s 1.79999973056523 +I17|MP2:int_d 6.42832247116395e-06 +I17|MP2:int_s 1.79999280686965 +I17|net9 3.4569077833444e-06 +I17|net013 1.79999932534737 +I18|MN0:int_d 4.58959811130725e-08 +I18|MN0:int_s 1.79999852574129 +I18|MN1:int_d -1.65867681180996e-06 +I18|MN1:int_s -2.3233854640709e-07 +I18|MN2:int_d -1.99611481519735e-06 +I18|MN2:int_s -6.92720911429489e-06 +I18|MP0:int_d 1.80000083097881 +I18|MP0:int_s 1.79999902379747 +I18|MP1:int_d 1.80000023441382 +I18|MP1:int_s 1.79999939943204 +I18|MP2:int_d -7.59658259512426e-06 +I18|MP2:int_s 1.79999122305815 +I18|net9 -9.32212826470084e-08 +I18|net013 1.79999936076659 +I19|MN0:int_d -1.67112369777518e-06 +I19|MN0:int_s 1.27397135097205 +I19|MN1:int_d 1.27396991416946 +I19|MN1:int_s 1.79997165610619 +I19|MN2:int_d 2.50144544678872e-06 +I19|MN2:int_s -8.52392099125821e-06 +I19|MP0:int_d 1.80000136931248 +I19|MP0:int_s 1.79996712934508 +I19|MP1:int_d 1.79996848693196 +I19|MP1:int_s 1.80000050618653 +I19|MP2:int_d -1.85627542549507e-05 +I19|MP2:int_s 1.80000205681155 +I19|net9 1.27397063257075 +I19|net013 1.79996910583615 +I20|MN0:int_d 4.99613533735663e-06 +I20|MN0:int_s 1.27396189168443 +I20|MN1:int_d 1.2739604683515 +I20|MN1:int_s 1.79997001085701 +I20|MN2:int_d 2.41443932079668e-06 +I20|MN2:int_s -2.98875485887697e-06 +I20|MP0:int_d 1.79999526073238 +I20|MP0:int_s 1.79996662917391 +I20|MP1:int_d 1.79996721101498 +I20|MP1:int_s 1.79999480141471 +I20|MP2:int_d -1.8483815990976e-05 +I20|MP2:int_s 1.79999476965931 +I20|net9 1.27396118001797 +I20|net013 1.79996790192739 +I21|MN0:int_d 4.12104417226144e-06 +I21|MN0:int_s 1.79999755705108 +I21|MN1:int_d 7.64495370131446e-06 +I21|MN1:int_s 3.70194330368145e-06 +I21|MN2:int_d 3.57997554522791e-06 +I21|MN2:int_s 2.82476539109931e-06 +I21|MP0:int_d 1.80000040137425 +I21|MP0:int_s 1.79999632998058 +I21|MP1:int_d 1.79999735822229 +I21|MP1:int_s 1.79999843591023 +I21|MP2:int_d -1.8669186125038e-06 +I21|MP2:int_s 1.79998834192754 +I21|net9 3.91149373797144e-06 +I21|net013 1.79999865431876 +I22|MN0:int_d 1.27396452801555 +I22|MN0:int_s 3.81577211553856e-06 +I22|MN1:int_d 1.79996996960799 +I22|MN1:int_s 1.27396298880158 +I22|MN2:int_d -3.39157133545292e-06 +I22|MN2:int_s 3.56121844362444e-06 +I22|MP0:int_d 1.79996681466996 +I22|MP0:int_s 1.79999934100148 +I22|MP1:int_d 1.79999848785502 +I22|MP1:int_s 1.79996793777409 +I22|MP2:int_d 1.79999876272353 +I22|MP2:int_s -1.72560747861545e-05 +I22|net9 1.27396375840856 +I22|net013 1.79996824331809 +I23|MN0:int_d 1.79999833909627 +I23|MN0:int_s 3.68777576744036e-06 +I23|MN1:int_d 3.2842268210842e-06 +I23|MN1:int_s 4.44091183047873e-06 +I23|MN2:int_d 1.55205605319162e-07 +I23|MN2:int_s 7.08809054987165e-07 +I23|MP0:int_d 1.79999971775104 +I23|MP0:int_s 1.80000089518375 +I23|MP1:int_d 1.7999991464124 +I23|MP1:int_s 1.80000175449629 +I23|MP2:int_d 1.79999465568149 +I23|MP2:int_s -4.33532997018786e-06 +I23|net9 3.48600129426228e-06 +I23|net013 1.79999924275939 +I24|MN0:int_d 1.79999741031918 +I24|MN0:int_s 6.37712872344768e-06 +I24|MN1:int_d 6.17253274244993e-06 +I24|MN1:int_s 1.09605216671157e-05 +I24|MN2:int_d 5.91071843220081e-06 +I24|MN2:int_s 6.69341990034269e-06 +I24|MP0:int_d 1.7999961822364 +I24|MP0:int_s 1.79999925009436 +I24|MP1:int_d 1.79999816373899 +I24|MP1:int_s 1.79999696800717 +I24|MP2:int_d 1.79998841032952 +I24|MP2:int_s 3.45778751995514e-07 +I24|net9 6.2748307329488e-06 +I24|net013 1.79999819126436 +I25|MN0:int_d 1.27395834544881 +I25|MN0:int_s 8.05623801373011e-06 +I25|MN1:int_d 1.79997014920341 +I25|MN1:int_s 1.27395696685632 +I25|MN2:int_d 1.33067228766159e-06 +I25|MN2:int_s 4.53179018185852e-06 +I25|MP0:int_d 1.79996565401421 +I25|MP0:int_s 1.79999817421783 +I25|MP1:int_d 1.79999738718351 +I25|MP1:int_s 1.79996713040244 +I25|MP2:int_d 1.79999628710009 +I25|MP2:int_s -1.42043391275164e-05 +I25|net9 1.27395765615256 +I25|net013 1.79996778143834 +I26|MN0:int_d 6.01194350670414e-06 +I26|MN0:int_s 1.79999777043935 +I26|MN1:int_d 9.45406320331468e-06 +I26|MN1:int_s 5.8473662802648e-06 +I26|MN2:int_d 3.02247246809342e-06 +I26|MN2:int_s 6.6453808993223e-06 +I26|MP0:int_d 1.79999998347347 +I26|MP0:int_s 1.79999856889949 +I26|MP1:int_d 1.80000006648857 +I26|MP1:int_s 1.79999858209208 +I26|MP2:int_d 2.43569438980524e-06 +I26|MP2:int_s 1.79999197726025 +I26|net9 5.92965489348447e-06 +I26|net013 1.79999865424476 +I27|MN0:int_d 2.94514192513858e-06 +I27|MN0:int_s 1.27395509508337 +I27|MN1:int_d 1.27395398556593 +I27|MN1:int_s 1.79997058172414 +I27|MN2:int_d 3.60184496046785e-06 +I27|MN2:int_s -3.62806086281528e-06 +I27|MP0:int_d 1.79999778727062 +I27|MP0:int_s 1.79996559923254 +I27|MP1:int_d 1.79996721429241 +I27|MP1:int_s 1.79999660128325 +I27|MP2:int_d -1.28929907987618e-05 +I27|MP2:int_s 1.79999502377012 +I27|net9 1.27395454032465 +I27|net013 1.79996780180074 +net1 -5.80914802252802e-06 +net5 7.98248039855096e-06 +net8 2.79852249249082e-06 +net13 3.83353330497166e-06 +net15 8.17717207068135e-06 +net16 2.79659742388819e-06 +net17 6.36984888931638e-05 +net19 -1.95397026130458e-07 +net21 4.29774133841028e-06 +net26 1.29625794060735e-06 +net28 8.74251298306659e-08 +net29 4.45500470873495e-05 +net31 -1.01850542838193e-08 +net32 4.65181906904231e-05 +net34 2.26699675421561e-06 +net35 1.34907527845306e-05 +net38 -1.29511162522577e-06 +net39 7.52841654428187e-08 +net44 3.01003361831935e-05 +net45 1.10409687350608e-06 +net47 -5.3348588721507e-06 +net54 3.98945105905648e-05 +net55 -2.38994074371393e-06 +net075 -3.57418877756887e-06 +net078 3.58508817675275e-06 +net087 1.21830109482684e-06 +net090 7.4182722718886e-07 +net093 -6.29477205993568e-06 +net095 -4.60933848064931e-06 +net0100 4.63460938802795e-05 +net0115 7.61603819176554e-06 +net0127 -3.02457655026684e-06 +v0:p -6.22020988282698e-05 +v1:p 0 +v2:p 1.12904652293171e-08 +v3:p 3.85496632498722e-08 +v4:p 1.01090398883078e-08 +v5:p 5.65873418087675e-09 +v6:p 6.94451217198955e-10 +v7:p -3.03564878417021e-09 +v8:p 2.65538869544364e-08 +v9:p -7.81421780996913e-08 +vdd! 1.8 +X0 1.8 +X1 1.8 +X2 1.8 +X3 1.8 +Y0 0 +Y1 0 +Y2 0 +Y3 0 +Z0 2.93897184319827e-06 +Z1 4.39473548203603e-05 +Z2 4.81529985396533e-05 +Z3 4.73604681994524e-05 +Z4 4.92300011434095e-05 +Z5 5.49603713100641e-05 +Z6 4.69884295223791e-05 +Z7 5.01982633488951e-06 diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..96932c3c2d4f679d4bb34a4d2e2a9e07ae319bad --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,3187 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:13:06 AM, Thur May 27, 2021 +# Number of equations = 2262 +1\:gnd! 9.43097045021573e-09 +1\:vdd! 1.79999999724034 +1\:X0 1.79999999999997 +1\:X1 1.8 +1\:X2 1.8 +1\:X3 1.79999999999991 +1\:Y2 0 +1\:Y3 0 +1\:Z0 8.78409889983755e-09 +1\:Z1 1.6371288110839e-08 +1\:Z2 1.91501017115961e-08 +1\:Z3 1.95086683993735e-08 +1\:Z4 1.94287556532383e-08 +1\:Z5 1.94099849110879e-08 +1\:Z6 1.92817640657803e-08 +1\:Z7 2.06193646775419e-08 +2\:gnd! 9.42103114587753e-09 +2\:I0|I3|Ai 1.79999994945801 +2\:I0|I3|Bi 1.79999994952964 +2\:I0|I4|Ai 1.79999994941415 +2\:I0|I4|Bi 1.79999994945542 +2\:I0|net1 1.79999999007712 +2\:I0|net3 1.59918034192585e-08 +2\:I0|net6 1.79999999013742 +2\:I1|I3|Ai 1.79999994968034 +2\:I1|I3|Bi 1.79999994958269 +2\:I1|I4|Ai 1.79999994970085 +2\:I1|I4|Bi 1.79999994976268 +2\:I1|net1 1.79999999033252 +2\:I1|net3 1.62803787266586e-08 +2\:I1|net6 1.799999990241 +2\:I2|I3|Ai 1.79999994571908 +2\:I2|I3|Bi 1.79999994561616 +2\:I2|I4|Ai 1.79999994580565 +2\:I2|I4|Bi 1.79999994574047 +2\:I2|net1 1.79999998637248 +2\:I2|net3 1.90935711616233e-08 +2\:I2|net6 1.79999998627619 +2\:I3|I3|Ai 1.79999994546555 +2\:I3|I3|Bi 1.79999994553852 +2\:I3|I4|Ai 1.79999994541494 +2\:I3|I4|Bi 1.79999994545883 +2\:I3|net1 1.79999998607875 +2\:I3|net3 1.88277151438802e-08 +2\:I3|net6 1.79999998614492 +2\:I4|I3|Ai 1.7999999453238 +2\:I4|I3|Bi 1.79999994535234 +2\:I4|I4|Ai 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1.90964122334764e-08 +20\:I3|net3 1.88277151438802e-08 +20\:I4|net3 1.84702407123787e-08 +20\:I9|net3 1.91903549256677e-08 +20\:I10|net3 1.93495794603587e-08 +20\:I11|net3 1.94765150741836e-08 +20\:net17 1.86772813904471e-08 +20\:net47 9.59375608762581e-09 +20\:net54 1.56628725163533e-08 +20\:net55 1.27584749767607e-08 +20\:net075 1.23632023635422e-08 +20\:net0115 9.59744558244099e-09 +20\:vdd! 1.79999999058987 +20\:X0 1.79999999999991 +20\:X1 1.8 +20\:X2 1.8 +20\:X3 1.79999999999998 +20\:Y0 0 +20\:Y2 0 +20\:Y3 0 +21\:gnd! 9.42751392842144e-09 +21\:net47 9.59375608762581e-09 +21\:net55 1.27584749766758e-08 +21\:net075 1.23632023635422e-08 +21\:net0115 9.60029453740089e-09 +21\:vdd! 1.79999999055954 +21\:X0 1.79999999999995 +21\:X1 1.8 +21\:X2 1.8 +21\:X3 1.79999999999998 +21\:Y0 0 +21\:Y1 0 +21\:Y2 0 +21\:Y3 0 +22\:gnd! 9.42103114632907e-09 +22\:net47 9.59375608762581e-09 +22\:net55 1.27566574451407e-08 +22\:net075 1.23632023635422e-08 +22\:net0115 9.59744558243829e-09 +22\:vdd! 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1.79999999039006 +30\:gnd! 9.37999590005646e-09 +30\:vdd! 1.79999999037735 +31\:gnd! 9.36560615919689e-09 +31\:vdd! 1.79999999035419 +32\:gnd! 9.36191134455532e-09 +32\:vdd! 1.79999999034658 +33\:gnd! 9.35066664333731e-09 +33\:vdd! 1.79999999034035 +34\:gnd! 9.3365553528861e-09 +34\:vdd! 1.79999999033523 +35\:gnd! 9.34340396587684e-09 +35\:vdd! 1.79999999032224 +36\:gnd! 9.31906879949677e-09 +36\:vdd! 1.79999999031642 +37\:gnd! 9.30936122113198e-09 +37\:vdd! 1.79999999030328 +38\:gnd! 9.299182161885e-09 +38\:vdd! 1.79999999028384 +39\:gnd! 9.27484360208562e-09 +39\:vdd! 1.79999999027378 +40\:gnd! 9.27053790845957e-09 +40\:vdd! 1.79999999026937 +41\:gnd! 9.23610577799954e-09 +41\:vdd! 1.79999999025721 +42\:gnd! 9.22825353443029e-09 +42\:vdd! 1.79999999024792 +43\:gnd! 9.21235711403484e-09 +43\:vdd! 1.7999999902416 +44\:gnd! 9.21816937976358e-09 +44\:vdd! 1.79999999023629 +45\:gnd! 9.23122213896464e-09 +45\:vdd! 1.79999999022536 +46\:gnd! 9.1911522256e-09 +46\:vdd! 1.7999999902199 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9.02503542486357e-09 +64\:vdd! 1.79999999109494 +65\:gnd! 9.02643992425253e-09 +65\:vdd! 1.79999999104171 +66\:gnd! 9.00346785890902e-09 +66\:vdd! 1.79999999103543 +67\:gnd! 9.01056207207204e-09 +67\:vdd! 1.79999999101168 +68\:gnd! 8.98860493626088e-09 +68\:vdd! 1.79999999096234 +69\:gnd! 8.9426699136023e-09 +69\:vdd! 1.79999999091672 +70\:gnd! 8.92832041875014e-09 +70\:vdd! 1.79999999091747 +71\:gnd! 8.93647275968657e-09 +71\:vdd! 1.79999999089453 +72\:gnd! 9.00346785936484e-09 +72\:vdd! 1.79999999086695 +73\:gnd! 8.94561470168952e-09 +73\:vdd! 1.79999999080593 +74\:gnd! 8.87405585439351e-09 +74\:vdd! 1.79999999077341 +75\:gnd! 8.8760520225553e-09 +75\:vdd! 1.7999999907554 +76\:gnd! 8.84643778739307e-09 +76\:vdd! 1.79999999074441 +77\:gnd! 8.85001338086605e-09 +77\:vdd! 1.79999999067035 +78\:gnd! 8.79520431507703e-09 +78\:vdd! 1.79999999064955 +79\:gnd! 8.7971145732616e-09 +79\:vdd! 1.79999999063858 +80\:gnd! 8.84643778784457e-09 +80\:vdd! 1.79999999060811 +81\:gnd! 8.77964297993361e-09 +81\:vdd! 1.79999999060622 +82\:gnd! 8.73476492866304e-09 +82\:vdd! 1.79999999059032 +83\:gnd! 8.80343989931037e-09 +83\:vdd! 1.7999999905881 +84\:gnd! 8.78665950262215e-09 +84\:vdd! 1.79999999055754 +85\:gnd! 8.70452814765959e-09 +85\:vdd! 1.79999999055721 +86\:gnd! 8.71030341482983e-09 +86\:vdd! 1.7999999905429 +87\:gnd! 8.73858093766186e-09 +87\:vdd! 1.79999999051237 +88\:gnd! 8.67500481750559e-09 +88\:vdd! 1.79999999049197 +89\:gnd! 8.65407756592549e-09 +89\:vdd! 1.79999999048384 +90\:gnd! 8.6554992555137e-09 +90\:vdd! 1.79999999043886 +91\:gnd! 8.61162982163906e-09 +91\:vdd! 1.79999999042024 +92\:gnd! 8.61738447152436e-09 +92\:vdd! 1.79999999041422 +93\:gnd! 8.45031952308948e-09 +93\:vdd! 1.79999999038912 +94\:gnd! 9.39996065571043e-09 +94\:vdd! 1.79999999037536 +95\:gnd! 9.39996065616362e-09 +95\:vdd! 1.79999999037502 +96\:gnd! 8.61162982206583e-09 +96\:vdd! 1.79999999035242 +97\:gnd! 5.59739219357834e-09 +97\:vdd! 1.79999999033923 +98\:gnd! 5.73964562145151e-10 +98\:vdd! 1.7999999903394 +99\:gnd! 9.42653349737448e-09 +99\:vdd! 1.79999999032787 +100\:gnd! 9.45470030600244e-09 +100\:vdd! 1.79999999032095 +101\:gnd! 9.45869532239147e-09 +101\:vdd! 1.79999999031489 +102\:gnd! 5.76580136363966e-09 +102\:vdd! 1.79999999029636 +103\:gnd! 5.79308688782748e-09 +103\:vdd! 1.79999999028198 +104\:gnd! 5.79940644139479e-09 +104\:vdd! 1.79999999027378 +105\:gnd! 6.66545014720156e-10 +105\:vdd! 1.79999999026775 +106\:gnd! 6.91356060241719e-10 +106\:vdd! 1.79999999024976 +107\:gnd! 6.96150536274625e-10 +107\:vdd! 1.7999999902464 +108\:gnd! 9.47575855522482e-09 +108\:vdd! 1.79999999023462 +109\:gnd! 9.48293046868758e-09 +109\:vdd! 1.79999999023534 +110\:gnd! 5.80042158364158e-09 +110\:vdd! 1.79999999022442 +111\:gnd! 5.83656718976237e-09 +111\:vdd! 1.79999999021792 +112\:gnd! 5.83826253140093e-09 +112\:vdd! 1.79999999021756 +113\:gnd! 7.09102894524574e-10 +113\:vdd! 1.79999999020871 +114\:gnd! 7.10535270101895e-10 +114\:vdd! 1.7999999902007 +115\:gnd! 9.4825871192728e-09 +115\:vdd! 1.79999999020518 +116\:gnd! 9.49160889466861e-09 +116\:vdd! 1.79999999019714 +117\:gnd! 5.83840423602689e-09 +117\:vdd! 1.79999999019965 +118\:gnd! 5.87921840272105e-09 +118\:vdd! 1.79999999019791 +119\:gnd! 5.88656420237779e-09 +119\:vdd! 1.79999999018925 +120\:gnd! 7.17301746503452e-10 +120\:vdd! 1.79999999019175 +121\:gnd! 7.50111388536984e-10 +121\:vdd! 1.7999999901858 +122\:gnd! 7.52186775387173e-10 +122\:vdd! 1.79999999019051 +123\:gnd! 9.50288289060707e-09 +123\:vdd! 1.79999999705148 +124\:gnd! 9.50288289097926e-09 +124\:vdd! 1.79999999705148 +125\:gnd! 5.8879682460341e-09 +125\:vdd! 1.79999999709426 +126\:gnd! 5.90708479477544e-09 +126\:vdd! 1.79999999303798 +127\:gnd! 5.92664612599017e-09 +127\:vdd! 1.79999999302754 +128\:gnd! 5.92963931537702e-09 +128\:vdd! 1.79999999302559 +129\:gnd! 7.60603489990793e-10 +129\:vdd! 1.79999999307801 +130\:gnd! 7.62371058940452e-10 +130\:vdd! 1.7999999970113 +131\:gnd! 9.51674433682771e-09 +131\:vdd! 1.79999999700209 +132\:gnd! 9.54043320910867e-09 +132\:vdd! 1.79999999704371 +133\:gnd! 9.54708745731704e-09 +133\:vdd! 1.79999999299203 +134\:gnd! 9.55009754850709e-09 +134\:vdd! 1.79999999294665 +135\:gnd! 5.96898707568483e-09 +135\:vdd! 1.79999999290303 +136\:gnd! 5.97094473195753e-09 +136\:vdd! 1.79999999290112 +137\:gnd! 7.83250302507818e-10 +137\:vdd! 1.79999999301929 +138\:gnd! 8.33015011155e-10 +138\:vdd! 1.79999999699898 +139\:gnd! 8.39113725464224e-10 +139\:vdd! 1.7999999969782 +140\:gnd! 9.56758586292118e-09 +140\:vdd! 1.79999999697084 +141\:gnd! 6.03088101528906e-09 +141\:vdd! 1.7999999970113 +142\:gnd! 6.03385076502254e-09 +142\:vdd! 1.79999999298979 +143\:gnd! 8.48721482791968e-10 +143\:vdd! 1.79999999294547 +144\:gnd! 8.50164079667662e-10 +144\:vdd! 1.79999999287604 +145\:gnd! 9.57139569778201e-09 +145\:vdd! 1.79999999285876 +146\:gnd! 9.57139569814972e-09 +146\:vdd! 1.79999999285146 +147\:gnd! 6.05808590579801e-09 +147\:vdd! 1.79999999290186 +148\:gnd! 6.05987174317506e-09 +148\:vdd! 1.79999999695063 +149\:gnd! 8.64563418288531e-10 +149\:vdd! 1.79999999693319 +150\:gnd! 8.92446715183697e-10 +150\:vdd! 1.79999999693127 +151\:gnd! 8.98066591536713e-10 +151\:vdd! 1.79999999287393 +152\:gnd! 9.5895633807676e-09 +152\:vdd! 1.79999999283515 +153\:gnd! 9.61167536334875e-09 +153\:vdd! 1.79999999280709 +154\:gnd! 6.05808590624952e-09 +154\:vdd! 1.79999999279265 +155\:gnd! 6.09534397789171e-09 +155\:vdd! 1.79999999276961 +156\:gnd! 6.10255103864616e-09 +156\:vdd! 1.7999999927587 +157\:gnd! 9.0117446617223e-10 +157\:vdd! 1.79999999275712 +158\:gnd! 9.06305554334387e-10 +158\:vdd! 1.79999999694849 +159\:gnd! 9.07699367904989e-10 +159\:vdd! 1.79999999688951 +160\:gnd! 9.61494435104386e-09 +160\:vdd! 1.79999999686288 +161\:gnd! 9.61791986998051e-09 +161\:vdd! 1.7999999968402 +162\:gnd! 6.11667526294494e-09 +162\:vdd! 1.7999999968171 +163\:gnd! 6.12396556847555e-09 +163\:vdd! 1.79999999681511 +164\:gnd! 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1.91472694750073e-08 +Z3 1.95058361628301e-08 +Z4 1.94287556532383e-08 +Z5 1.94122167424268e-08 +Z6 1.92817640657803e-08 +Z7 2.06193646775419e-08 diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..b8c25d9e0c9968eea45656eca1d13d8e863dd288 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:13:04 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..b786a836e8776424e3d83794c164790fad9dd95e --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:13:06 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..27359cb322250790f3d2e77bd6ec1b308483c24f Binary files /dev/null and b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..4d1d14238df6a480758e3a684c18d63d0a13cfb0 Binary files /dev/null and b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..b3fe591e850994fae2b33e2cd0c508ed55f12384 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:13:06 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:13:06 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..7023f0bb31bc14ae84a79bd21eb2424f1983f57e Binary files /dev/null and b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..7890bfe0aaf645ad72f83018d3861157208fcba5 Binary files /dev/null and b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..13b41c73bb1a4bab29a0d75718f20087f6cf379f --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:13:06 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm 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lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg 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pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..08f27b422f283b8b7534287215b9d7e53f222c16 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 02:13:06 2021" +"simulator" "spectre" +"date" "May 27 02:13:07 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..a3a57b0ac87f71894aa276ed7b2e4d2e1e1bee20 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"4X4_multiplier\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 02:13:04 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..3109123856fb8bb4d5e6be23416d519f1bc04f18 --- /dev/null +++ b/involution/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,271 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 98043 +Memory available: 1.9681 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 1200.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 1200.0 30.6 + 3 0 3 2201.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 2201.0 41.9 + 12 1 2 1200.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 2201.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1600.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 2201.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 2:13:06 AM, Thur May 27, 2021 (process id: 98043). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre1_6429_1 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 98043 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/4x4_multiplier_11100001/4X4_multiplier/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/4x4_mul_11100001.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 94.985 ms, elapsed = 141.74 ms. +Time accumulated: CPU = 127.979 ms, elapsed = 141.744 ms. +Peak resident memory used = 40.4 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 50.993 ms, elapsed = 51.0039 ms. +Time accumulated: CPU = 179.972 ms, elapsed = 192.979 ms. +Peak resident memory used = 48.1 Mbytes. + +Time for EDB Visiting: CPU = 23.996 ms, elapsed = 24.5211 ms. +Time accumulated: CPU = 203.968 ms, elapsed = 217.721 ms. +Peak resident memory used = 51.2 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8282): `ca' is not a device or subcircuit instance name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 2261 + bsim3v3 456 + capacitor 8 + resistor 2003 + vsource 10 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 11.999 ms, elapsed = 223.848 ms. +Time accumulated: CPU = 216.966 ms, elapsed = 441.803 ms. +Peak resident memory used = 53.6 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre1_6429_1, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ + +Notice from spectre during IC analysis, during transient analysis `tran'. + GminDC = 1 pS is large enough to noticeably affect the DC solution. + dV(I11|I2|MN0:int_d) = 10.2109 mV + Use the `gmin_check' option to eliminate or expand this report. + Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of convergence. + +DC simulation time: CPU = 99.986 ms, elapsed = 100.075 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 10 (current) + save 2261 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.73 ns (9.1 %), step = 600 ps (2 %) + tran: time = 3.93 ns (13.1 %), step = 600 ps (2 %) + tran: time = 5.73 ns (19.1 %), step = 600 ps (2 %) + tran: time = 6.93 ns (23.1 %), step = 600 ps (2 %) + tran: time = 8.73 ns (29.1 %), step = 600 ps (2 %) + +Notice from spectre at time = 9.93 ns during transient analysis `tran'. + Found trapezoidal ringing on node v5:p. + + tran: time = 9.93 ns (33.1 %), step = 600 ps (2 %) + tran: time = 11.25 ns (37.5 %), step = 13.93 ps (46.4 m%) + tran: time = 12.79 ns (42.6 %), step = 208.8 ps (696 m%) + tran: time = 14.53 ns (48.4 %), step = 445.6 ps (1.49 %) + +Notice from spectre at time = 15.729 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:I9|I3|Bi. +Notice from spectre at time = 16.329 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:I9|I3|Bi. + + tran: time = 16.33 ns (54.4 %), step = 600 ps (2 %) + +Notice from spectre at time = 16.929 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:I9|I3|Bi. +Notice from spectre at time = 17.529 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:I9|I3|Bi. + Further occurrences of this notice will be suppressed. + + tran: time = 17.53 ns (58.4 %), step = 600 ps (2 %) + tran: time = 19.33 ns (64.4 %), step = 600 ps (2 %) + tran: time = 20.25 ns (67.5 %), step = 7.437 ps (24.8 m%) + tran: time = 21.81 ns (72.7 %), step = 131.3 ps (438 m%) + tran: time = 23.33 ns (77.8 %), step = 600 ps (2 %) + tran: time = 25.13 ns (83.8 %), step = 600 ps (2 %) + tran: time = 26.33 ns (87.8 %), step = 600 ps (2 %) + tran: time = 28.13 ns (93.8 %), step = 600 ps (2 %) + tran: time = 29.33 ns (97.8 %), step = 600 ps (2 %) +Number of accepted tran steps = 407 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 99.986 ms, elapsed = 100.124 ms. +Intrinsic tran analysis time: CPU = 1.55776 s, elapsed = 1.64902 s. +Total time required for tran analysis `tran': CPU = 1.66475 s, elapsed = 1.75824 s. +Time accumulated: CPU = 1.9637 s, elapsed = 2.45682 s. +Peak resident memory used = 84.1 Mbytes. + + +Notice from spectre. + 17 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. 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1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1935 V 0 +\311\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1936 V 0 +\311\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1937 V 0 +\312\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1938 V 0 +\312\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1939 V 0 +\313\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1940 V 0 +\313\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1941 V 0 +\314\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1942 V 0 +\314\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1943 V 0 +\315\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1944 V 0 +\315\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1945 V 0 +\316\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1946 V 0 +\316\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1947 V 0 +\317\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1948 V 0 +\317\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1949 V 0 +\318\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1950 V 0 +\318\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1951 V 0 +\319\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1952 V 0 +\319\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1953 V 0 +\31\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1376 V 0 +\31\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1377 V 0 +\320\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1954 V 0 +\321\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1955 V 0 +\322\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1956 V 0 +\323\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1957 V 0 +\324\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1958 V 0 +\325\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1959 V 0 +\326\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1960 V 0 +\327\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1961 V 0 +\328\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1962 V 0 +\329\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1963 V 0 +\32\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1378 V 0 +\32\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1379 V 0 +\330\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1964 V 0 +\331\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1965 V 0 +\332\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1966 V 0 +\333\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1967 V 0 +\334\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1968 V 0 +\335\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1969 V 0 +\336\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1970 V 0 +\337\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1971 V 0 +\338\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1972 V 0 +\339\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1973 V 0 +\33\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1380 V 0 +\33\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1381 V 0 +\340\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1974 V 0 +\341\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1975 V 0 +\342\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1976 V 0 +\343\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1977 V 0 +\344\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1978 V 0 +\345\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1979 V 0 +\346\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1980 V 0 +\347\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1981 V 0 +\348\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1982 V 0 +\349\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1983 V 0 +\34\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1382 V 0 +\34\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1383 V 0 +\350\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1984 V 0 +\351\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1985 V 0 +\352\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1986 V 0 +\353\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1987 V 0 +\354\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1988 V 0 +\355\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1989 V 0 +\356\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1990 V 0 +\357\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1991 V 0 +\358\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1992 V 0 +\359\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1993 V 0 +\35\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1384 V 0 +\35\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1385 V 0 +\360\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1994 V 0 +\361\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 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1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1862 V 0 +­­¨©|140864512|­­¨© 0 0 0 18446744073709551615 134924240 \274\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1863 V 0 +­­¨©|140865424|­­¨© 0 0 0 18446744073709551615 134924240 \275\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1864 V 0 +­­¨©|140866336|­­¨© 0 0 0 18446744073709551615 134924240 \275\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1865 V 0 +­­¨©|140867248|­­¨© 0 0 0 18446744073709551615 134924240 \276\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1866 V 0 +­­¨©|140868160|­­¨© 0 0 0 18446744073709551615 134924240 \276\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1867 V 0 +­­¨©|140869072|­­¨© 0 0 0 18446744073709551615 134924240 \277\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1868 V 0 +­­¨©|140874096|­­¨© 0 0 0 18446744073709551615 134924240 \277\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1869 V 0 +­­¨©|140875024|­­¨© 0 0 0 18446744073709551615 134924240 \278\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1870 V 0 +­­¨©|140875936|­­¨© 0 0 0 18446744073709551615 134924240 \278\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1871 V 0 +­­¨©|140876848|­­¨© 0 0 0 18446744073709551615 134924240 \279\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1872 V 0 +­­¨©|140877760|­­¨© 0 0 0 18446744073709551615 134924240 \279\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1873 V 0 +­­¨©|140878672|­­¨© 0 0 0 18446744073709551615 134924240 \280\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1874 V 0 +­­¨©|140879584|­­¨© 0 0 0 18446744073709551615 134924240 \280\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1875 V 0 +­­¨©|140880496|­­¨© 0 0 0 18446744073709551615 134924240 \281\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1876 V 0 +­­¨©|140881408|­­¨© 0 0 0 18446744073709551615 134924240 \281\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1877 V 0 +­­¨©|140882320|­­¨© 0 0 0 18446744073709551615 134924240 \282\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1878 V 0 +­­¨©|140883232|­­¨© 0 0 0 18446744073709551615 134924240 \282\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1879 V 0 +­­¨©|140884144|­­¨© 0 0 0 18446744073709551615 134924240 \283\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1880 V 0 +­­¨©|140885056|­­¨© 0 0 0 18446744073709551615 134924240 \283\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1881 V 0 +­­¨©|140885968|­­¨© 0 0 0 18446744073709551615 134924240 \284\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1882 V 0 +­­¨©|140886896|­­¨© 0 0 0 18446744073709551615 134924240 \284\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1883 V 0 +­­¨©|140887808|­­¨© 0 0 0 18446744073709551615 134924240 \285\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1884 V 0 +­­¨©|140888720|­­¨© 0 0 0 18446744073709551615 134924240 \285\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1885 V 0 +­­¨©|140889632|­­¨© 0 0 0 18446744073709551615 134924240 \286\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1886 V 0 +­­¨©|140890544|­­¨© 0 0 0 18446744073709551615 134924240 \286\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1887 V 0 +­­¨©|140891456|­­¨© 0 0 0 18446744073709551615 134924240 \287\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1888 V 0 +­­¨©|140892368|­­¨© 0 0 0 18446744073709551615 134924240 \287\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1889 V 0 +­­¨©|140893280|­­¨© 0 0 0 18446744073709551615 134924240 \288\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1890 V 0 +­­¨©|140894192|­­¨© 0 0 0 18446744073709551615 134924240 \288\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1891 V 0 +­­¨©|140895104|­­¨© 0 0 0 18446744073709551615 134924240 \289\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1892 V 0 +­­¨©|140896016|­­¨© 0 0 0 18446744073709551615 134924240 \289\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1893 V 0 +­­¨©|140896928|­­¨© 0 0 0 18446744073709551615 134924240 \290\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1894 V 0 +­­¨©|140897840|­­¨© 0 0 0 18446744073709551615 134924240 \290\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1895 V 0 +­­¨©|140898752|­­¨© 0 0 0 18446744073709551615 134924240 \291\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1896 V 0 +­­¨©|140899664|­­¨© 0 0 0 18446744073709551615 134924240 \291\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1897 V 0 +­­¨©|140900576|­­¨© 0 0 0 18446744073709551615 134924240 \292\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1898 V 0 +­­¨©|140901488|­­¨© 0 0 0 18446744073709551615 134924240 \292\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1899 V 0 +­­¨©|140902400|­­¨© 0 0 0 18446744073709551615 134924240 \293\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1900 V 0 +­­¨©|140903312|­­¨© 0 0 0 18446744073709551615 134924240 \293\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1901 V 0 +­­¨©|140908336|­­¨© 0 0 0 18446744073709551615 134924240 \294\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1902 V 0 +­­¨©|140909264|­­¨© 0 0 0 18446744073709551615 134924240 \294\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1903 V 0 +­­¨©|140910176|­­¨© 0 0 0 18446744073709551615 134924240 \295\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1904 V 0 +­­¨©|140911088|­­¨© 0 0 0 18446744073709551615 134924240 \295\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1905 V 0 +­­¨©|140912000|­­¨© 0 0 0 18446744073709551615 134924240 \296\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1906 V 0 +­­¨©|140912912|­­¨© 0 0 0 18446744073709551615 134924240 \296\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1907 V 0 +­­¨©|140913824|­­¨© 0 0 0 18446744073709551615 134924240 \297\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1908 V 0 +­­¨©|140914736|­­¨© 0 0 0 18446744073709551615 134924240 \297\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1909 V 0 +­­¨©|140915648|­­¨© 0 0 0 18446744073709551615 134924240 \298\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1910 V 0 +­­¨©|140916560|­­¨© 0 0 0 18446744073709551615 134924240 \298\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1911 V 0 +­­¨©|140917472|­­¨© 0 0 0 18446744073709551615 134924240 \299\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1912 V 0 +­­¨©|140918384|­­¨© 0 0 0 18446744073709551615 134924240 \299\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1913 V 0 +­­¨©|140919296|­­¨© 0 0 0 18446744073709551615 134924240 \300\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1914 V 0 +­­¨©|140920208|­­¨© 0 0 0 18446744073709551615 134924240 \300\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1915 V 0 +­­¨©|140921120|­­¨© 0 0 0 18446744073709551615 134924240 \301\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1916 V 0 +­­¨©|140922032|­­¨© 0 0 0 18446744073709551615 134924240 \301\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1917 V 0 +­­¨©|140922944|­­¨© 0 0 0 18446744073709551615 134924240 \302\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1918 V 0 +­­¨©|140923856|­­¨© 0 0 0 18446744073709551615 134924240 \302\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1919 V 0 +­­¨©|140924768|­­¨© 0 0 0 18446744073709551615 134924240 \303\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1920 V 0 +­­¨©|140925680|­­¨© 0 0 0 18446744073709551615 134924240 \303\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1921 V 0 +­­¨©|140926592|­­¨© 0 0 0 18446744073709551615 134924240 \304\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1922 V 0 +­­¨©|140927504|­­¨© 0 0 0 18446744073709551615 134924240 \304\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1923 V 0 +­­¨©|140928416|­­¨© 0 0 0 18446744073709551615 134924240 \305\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1924 V 0 +­­¨©|140929328|­­¨© 0 0 0 18446744073709551615 134924240 \305\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1925 V 0 +­­¨©|140930240|­­¨© 0 0 0 18446744073709551615 134924240 \306\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1926 V 0 +­­¨©|140931152|­­¨© 0 0 0 18446744073709551615 134924240 \306\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1927 V 0 +­­¨©|140932064|­­¨© 0 0 0 18446744073709551615 134924240 \307\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1928 V 0 +­­¨©|140932976|­­¨© 0 0 0 18446744073709551615 134924240 \307\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1929 V 0 +­­¨©|140933888|­­¨© 0 0 0 18446744073709551615 134924240 \308\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1930 V 0 +­­¨©|140934800|­­¨© 0 0 0 18446744073709551615 134924240 \308\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1931 V 0 +­­¨©|140935712|­­¨© 0 0 0 18446744073709551615 134924240 \309\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1932 V 0 +­­¨©|140936624|­­¨© 0 0 0 18446744073709551615 134924240 \309\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1933 V 0 +­­¨©|140937536|­­¨© 0 0 0 18446744073709551615 134924240 \310\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1934 V 0 +­­¨©|140938448|­­¨© 0 0 0 18446744073709551615 134924240 \310\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1935 V 0 +­­¨©|140939360|­­¨© 0 0 0 18446744073709551615 134924240 \311\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1936 V 0 +­­¨©|140940272|­­¨© 0 0 0 18446744073709551615 134924240 \311\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1937 V 0 +­­¨©|140941184|­­¨© 0 0 0 18446744073709551615 134924240 \312\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1938 V 0 +­­¨©|140942096|­­¨© 0 0 0 18446744073709551615 134924240 \312\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1939 V 0 +­­¨©|140943008|­­¨© 0 0 0 18446744073709551615 134924240 \313\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1940 V 0 +­­¨©|140943920|­­¨© 0 0 0 18446744073709551615 134924240 \313\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1941 V 0 +­­¨©|140944832|­­¨© 0 0 0 18446744073709551615 134924240 \314\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1942 V 0 +­­¨©|140945744|­­¨© 0 0 0 18446744073709551615 134924240 \314\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1943 V 0 +­­¨©|140946656|­­¨© 0 0 0 18446744073709551615 134924240 \315\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1944 V 0 +­­¨©|140947568|­­¨© 0 0 0 18446744073709551615 134924240 \315\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1945 V 0 +­­¨©|140948480|­­¨© 0 0 0 18446744073709551615 134924240 \316\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1946 V 0 +­­¨©|140949392|­­¨© 0 0 0 18446744073709551615 134924240 \316\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1947 V 0 +­­¨©|140950304|­­¨© 0 0 0 18446744073709551615 134924240 \317\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1948 V 0 +­­¨©|140951216|­­¨© 0 0 0 18446744073709551615 134924240 \317\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1949 V 0 +­­¨©|140952128|­­¨© 0 0 0 18446744073709551615 134924240 \318\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1950 V 0 +­­¨©|140953040|­­¨© 0 0 0 18446744073709551615 134924240 \318\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1951 V 0 +­­¨©|140953952|­­¨© 0 0 0 18446744073709551615 134924240 \319\:gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1952 V 0 +­­¨©|140954864|­­¨© 0 0 0 18446744073709551615 134924240 \319\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1953 V 0 +­­¨©|140959888|­­¨© 0 0 0 18446744073709551615 134924240 \320\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1954 V 0 +­­¨©|140960816|­­¨© 0 0 0 18446744073709551615 134924240 \321\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1955 V 0 +­­¨©|140961728|­­¨© 0 0 0 18446744073709551615 134924240 \322\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1956 V 0 +­­¨©|140962640|­­¨© 0 0 0 18446744073709551615 134924240 \323\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1957 V 0 +­­¨©|140963552|­­¨© 0 0 0 18446744073709551615 134924240 \324\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1958 V 0 +­­¨©|140964464|­­¨© 0 0 0 18446744073709551615 134924240 \325\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1959 V 0 +­­¨©|140965376|­­¨© 0 0 0 18446744073709551615 134924240 \326\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1960 V 0 +­­¨©|140966288|­­¨© 0 0 0 18446744073709551615 134924240 \327\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1961 V 0 +­­¨©|140967200|­­¨© 0 0 0 18446744073709551615 134924240 \328\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1962 V 0 +­­¨©|140968112|­­¨© 0 0 0 18446744073709551615 134924240 \329\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1963 V 0 +­­¨©|140969024|­­¨© 0 0 0 18446744073709551615 134924240 \330\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1964 V 0 +­­¨©|140969936|­­¨© 0 0 0 18446744073709551615 134924240 \331\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1965 V 0 +­­¨©|140970848|­­¨© 0 0 0 18446744073709551615 134924240 \332\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1966 V 0 +­­¨©|140971760|­­¨© 0 0 0 18446744073709551615 134924240 \333\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1967 V 0 +­­¨©|140972672|­­¨© 0 0 0 18446744073709551615 134924240 \334\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1968 V 0 +­­¨©|140973584|­­¨© 0 0 0 18446744073709551615 134924240 \335\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1969 V 0 +­­¨©|140974496|­­¨© 0 0 0 18446744073709551615 134924240 \336\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1970 V 0 +­­¨©|140975408|­­¨© 0 0 0 18446744073709551615 134924240 \337\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1971 V 0 +­­¨©|140976320|­­¨© 0 0 0 18446744073709551615 134924240 \338\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1972 V 0 +­­¨©|140977232|­­¨© 0 0 0 18446744073709551615 134924240 \339\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1973 V 0 +­­¨©|140978144|­­¨© 0 0 0 18446744073709551615 134924240 \340\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1974 V 0 +­­¨©|140979056|­­¨© 0 0 0 18446744073709551615 134924240 \341\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1975 V 0 +­­¨©|140979968|­­¨© 0 0 0 18446744073709551615 134924240 \342\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1976 V 0 +­­¨©|140980880|­­¨© 0 0 0 18446744073709551615 134924240 \343\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1977 V 0 +­­¨©|140981792|­­¨© 0 0 0 18446744073709551615 134924240 \344\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1978 V 0 +­­¨©|140982704|­­¨© 0 0 0 18446744073709551615 134924240 \345\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1979 V 0 +­­¨©|140983616|­­¨© 0 0 0 18446744073709551615 134924240 \346\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1980 V 0 +­­¨©|140984528|­­¨© 0 0 0 18446744073709551615 134924240 \347\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1981 V 0 +­­¨©|140985440|­­¨© 0 0 0 18446744073709551615 134924240 \348\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1982 V 0 +­­¨©|140986352|­­¨© 0 0 0 18446744073709551615 134924240 \349\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1983 V 0 +­­¨©|140987264|­­¨© 0 0 0 18446744073709551615 134924240 \350\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1984 V 0 +­­¨©|140988176|­­¨© 0 0 0 18446744073709551615 134924240 \351\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1985 V 0 +­­¨©|140989088|­­¨© 0 0 0 18446744073709551615 134924240 \352\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1986 V 0 +­­¨©|140990000|­­¨© 0 0 0 18446744073709551615 134924240 \353\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1987 V 0 +­­¨©|140990912|­­¨© 0 0 0 18446744073709551615 134924240 \354\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1988 V 0 +­­¨©|140991824|­­¨© 0 0 0 18446744073709551615 134924240 \355\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1989 V 0 +­­¨©|140992736|­­¨© 0 0 0 18446744073709551615 134924240 \356\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1990 V 0 +­­¨©|140993648|­­¨© 0 0 0 18446744073709551615 134924240 \357\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1991 V 0 +­­¨©|140994560|­­¨© 0 0 0 18446744073709551615 134924240 \358\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1992 V 0 +­­¨©|140995472|­­¨© 0 0 0 18446744073709551615 134924240 \359\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1993 V 0 +­­¨©|140996384|­­¨© 0 0 0 18446744073709551615 134924240 \360\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1994 V 0 +­­¨©|140997296|­­¨© 0 0 0 18446744073709551615 134924240 \361\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1995 V 0 +­­¨©|140998208|­­¨© 0 0 0 18446744073709551615 134924240 \362\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1996 V 0 +­­¨©|140999120|­­¨© 0 0 0 18446744073709551615 134924240 \363\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1997 V 0 +­­¨©|141000032|­­¨© 0 0 0 18446744073709551615 134924240 \364\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1998 V 0 +­­¨©|141000944|­­¨© 0 0 0 18446744073709551615 134924240 \365\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1999 V 0 +­­¨©|141001856|­­¨© 0 0 0 18446744073709551615 134924240 \366\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2000 V 0 +­­¨©|141002768|­­¨© 0 0 0 18446744073709551615 134924240 \367\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2001 V 0 +­­¨©|141003680|­­¨© 0 0 0 18446744073709551615 134924240 \368\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2002 V 0 +­­¨©|141004592|­­¨© 0 0 0 18446744073709551615 134924240 \369\:vdd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2003 V 0 +­­¨©|141005504|­­¨© 0 0 0 18446744073709551615 134924240 gnd! 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2004 V 0 +­­¨©|141006416|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I0\|net9 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2005 V 0 +­­¨©|141007328|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I1\|net9 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2006 V 0 +­­¨©|141008240|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I2\|net9 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2007 V 0 +­­¨©|141009152|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I3\|Ai 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2008 V 0 +­­¨©|141010064|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I3\|Bi 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2009 V 0 +­­¨©|141010976|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I3\|net8 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2010 V 0 +­­¨©|141011888|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I3\|net17 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2011 V 0 +­­¨©|141012800|­­¨© 0 0 0 18446744073709551615 134924240 I0\|I3\|net022 0 1 -1 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408 1904 V 0 +­­¨©|140911088|­­¨© 0 0 0 18544 134924240 \295\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737559321710705262 1.8010872009926000015 408 1905 V 0 +­­¨©|140912000|­­¨© 0 0 0 18544 134924240 \296\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00092650832569820716026 0.020811409070592756798 408 1906 V 0 +­­¨©|140912912|­­¨© 0 0 0 18544 134924240 \296\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737137429229585806 1.8010813772525318122 408 1907 V 0 +­­¨©|140913824|­­¨© 0 0 0 18544 134924240 \297\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00092645774781793539376 0.020810295290558038922 408 1908 V 0 +­­¨©|140914736|­­¨© 0 0 0 18544 134924240 \297\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736924135087008825 1.8010820832137655056 408 1909 V 0 +­­¨©|140915648|­­¨© 0 0 0 18544 134924240 \298\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00093248255425733869543 0.020817983914468447121 408 1910 V 0 +­­¨©|140916560|­­¨© 0 0 0 18544 134924240 \298\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736462279618629978 1.8010835744012261284 408 1911 V 0 +­­¨©|140917472|­­¨© 0 0 0 18544 134924240 \299\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00093246535373603530675 0.020818972516528949646 408 1912 V 0 +­­¨©|140918384|­­¨© 0 0 0 18544 134924240 \299\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736225903380511415 1.8010843390473416648 408 1913 V 0 +­­¨©|140919296|­­¨© 0 0 0 18544 134924240 \300\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00093246126066700901671 0.020820314784167050226 408 1914 V 0 +­­¨©|140920208|­­¨© 0 0 0 18544 134924240 \300\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736227590639155327 1.8010843490284089707 408 1915 V 0 +­­¨©|140921120|­­¨© 0 0 0 18544 134924240 \301\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00093695258002610463076 0.020822847552697931056 408 1916 V 0 +­­¨©|140922032|­­¨© 0 0 0 18544 134924240 \301\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7835922619294697355 1.8006625987207316442 408 1917 V 0 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3.0000000000000003936e-08 -0.00094307449203495934305 0.020833491246569909444 408 1924 V 0 +­­¨©|140929328|­­¨© 0 0 0 18544 134924240 \305\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834793256353056456 1.8006816442326643024 408 1925 V 0 +­­¨©|140930240|­­¨© 0 0 0 18544 134924240 \306\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094598674443214603256 0.020838687250590549882 408 1926 V 0 +­­¨©|140931152|­­¨© 0 0 0 18544 134924240 \306\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834897944702841066 1.8006816505945559825 408 1927 V 0 +­­¨©|140932064|­­¨© 0 0 0 18544 134924240 \307\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094598497678408989282 0.020842030417182424995 408 1928 V 0 +­­¨©|140932976|­­¨© 0 0 0 18544 134924240 \307\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737138163449703843 1.8010813531169034274 408 1929 V 0 +­­¨©|140933888|­­¨© 0 0 0 18544 134924240 \308\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094770266659127786347 0.020841232086687602743 408 1930 V 0 +­­¨©|140934800|­­¨© 0 0 0 18544 134924240 \308\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736969015408281525 1.8010820698884679736 408 1931 V 0 +­­¨©|140935712|­­¨© 0 0 0 18544 134924240 \309\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094767101925285004722 0.020834508852251236444 408 1932 V 0 +­­¨©|140936624|­­¨© 0 0 0 18544 134924240 \309\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.773646303893291476 1.8010835616421205785 408 1933 V 0 +­­¨©|140937536|­­¨© 0 0 0 18544 134924240 \310\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094769935199432342628 0.020869344955909079065 408 1934 V 0 +­­¨©|140938448|­­¨© 0 0 0 18544 134924240 \310\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735946457951137223 1.8010852392735956506 408 1935 V 0 +­­¨©|140939360|­­¨© 0 0 0 18544 134924240 \311\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00095053191847579488784 0.020841609231074594011 408 1936 V 0 +­­¨©|140940272|­­¨© 0 0 0 18544 134924240 \311\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735781448736680499 1.8010857708465304317 408 1937 V 0 +­­¨©|140941184|­­¨© 0 0 0 18544 134924240 \312\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.0009505290752486102732 0.020842294634741895254 408 1938 V 0 +­­¨©|140942096|­­¨© 0 0 0 18544 134924240 \312\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735658058830816586 1.8010861415536130181 408 1939 V 0 +­­¨©|140943008|­­¨© 0 0 0 18544 134924240 \313\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00095275950309406170699 0.020841779132532337049 408 1940 V 0 +­­¨©|140943920|­­¨© 0 0 0 18544 134924240 \313\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.77357059748859891 1.80108611837265431 408 1941 V 0 +­­¨©|140944832|­­¨© 0 0 0 18544 134924240 \314\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00095457867121828644461 0.020841917883407900386 408 1942 V 0 +­­¨©|140945744|­­¨© 0 0 0 18544 134924240 \314\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736227510023845344 1.8010843484674088355 408 1943 V 0 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3.0000000000000003936e-08 -0.00096316509962049781657 0.020842547742653351472 408 1950 V 0 +­­¨©|140953040|­­¨© 0 0 0 18544 134924240 \318\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834212519537342434 1.8006874222585547152 408 1951 V 0 +­­¨©|140953952|­­¨© 0 0 0 18544 134924240 \319\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00095739805601973218541 0.020842044364730409611 408 1952 V 0 +­­¨©|140954864|­­¨© 0 0 0 18544 134924240 \319\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833860115789452738 1.8006900954627194089 408 1953 V 0 +­­¨©|140959888|­­¨© 0 0 0 18544 134924240 \320\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833855189155158882 1.8006900791842481713 408 1954 V 0 +­­¨©|140960816|­­¨© 0 0 0 18544 134924240 \321\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735899793508027589 1.8010857779442726034 408 1955 V 0 +­­¨©|140961728|­­¨© 0 0 0 18544 134924240 \322\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735518711628193156 1.8010865515909597612 408 1956 V 0 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1.7833169625456586349 1.8006951229194798625 408 1963 V 0 +­­¨©|140969024|­­¨© 0 0 0 18544 134924240 \330\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832808018320003285 1.8006951293285544669 408 1964 V 0 +­­¨©|140969936|­­¨© 0 0 0 18544 134924240 \331\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.773552048618186161 1.8010865369001021197 408 1965 V 0 +­­¨©|140970848|­­¨© 0 0 0 18544 134924240 \332\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735117066514551887 1.8010877385468897494 408 1966 V 0 +­­¨©|140971760|­­¨© 0 0 0 18544 134924240 \333\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734985476732179066 1.8010883949711649077 408 1967 V 0 +­­¨©|140972672|­­¨© 0 0 0 18544 134924240 \334\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734640812510276131 1.8010884024831199657 408 1968 V 0 +­­¨©|140973584|­­¨© 0 0 0 18544 134924240 \335\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833673201021909005 1.8006914046800563955 408 1969 V 0 +­­¨©|140974496|­­¨© 0 0 0 18544 134924240 \336\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833048120104637579 1.8006998872273676238 408 1970 V 0 +­­¨©|140975408|­­¨© 0 0 0 18544 134924240 \337\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832889165145837662 1.8006971328158678514 408 1971 V 0 +­­¨©|140976320|­­¨© 0 0 0 18544 134924240 \338\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832462035755971552 1.8007001935231674583 408 1972 V 0 +­­¨©|140977232|­­¨© 0 0 0 18544 134924240 \339\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7831974888357813303 1.8007036980432042927 408 1973 V 0 +­­¨©|140978144|­­¨© 0 0 0 18544 134924240 \340\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832163466486081749 1.8007037060728909861 408 1974 V 0 +­­¨©|140979056|­­¨© 0 0 0 18544 134924240 \341\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7733911302308189573 1.8010877114839851654 408 1975 V 0 +­­¨©|140979968|­­¨© 0 0 0 18544 134924240 \342\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734835615392694486 1.8010894635982663825 408 1976 V 0 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1.7831851676970453813 1.8007051935977411716 408 1983 V 0 +­­¨©|140987264|­­¨© 0 0 0 18544 134924240 \350\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7831718842396773184 1.8007066711351478183 408 1984 V 0 +­­¨©|140988176|­­¨© 0 0 0 18544 134924240 \351\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7830891714183989549 1.8007066527928623501 408 1985 V 0 +­­¨©|140989088|­­¨© 0 0 0 18544 134924240 \352\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7831007849002584731 1.8007036848678621421 408 1986 V 0 +­­¨©|140990000|­­¨© 0 0 0 18544 134924240 \353\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734116064715821359 1.8010894376497732505 408 1987 V 0 +­­¨©|140990912|­­¨© 0 0 0 18544 134924240 \354\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734826378365304844 1.8010910426364690196 408 1988 V 0 +­­¨©|140991824|­­¨© 0 0 0 18544 134924240 \355\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.773462578784481769 1.801097778547567474 408 1989 V 0 +­­¨©|140992736|­­¨© 0 0 0 18544 134924240 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3.0000000000000003936e-08 -0.0010063872552055080651 0.033022618587219873532 408 1890 V 0 +­­¨©|140894192|­­¨© 0 0 0 18544 134924240 \288\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737667558510246124 1.801079604848745408 408 1891 V 0 +­­¨©|140895104|­­¨© 0 0 0 18544 134924240 \289\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.0010063247459207603357 0.033021953313922013107 408 1892 V 0 +­­¨©|140896016|­­¨© 0 0 0 18544 134924240 \289\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737353436067864187 1.8010806652351083468 408 1893 V 0 +­­¨©|140896928|­­¨© 0 0 0 18544 134924240 \290\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.0010060872177972365361 0.033018099109899348709 408 1894 V 0 +­­¨©|140897840|­­¨© 0 0 0 18544 134924240 \290\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.773739115452398929 1.8010806726984944781 408 1895 V 0 +­­¨©|140898752|­­¨© 0 0 0 18544 134924240 \291\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00091659845637775104205 0.020797579732944111719 408 1896 V 0 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3.0000000000000003936e-08 1.7836262748298612468 1.80066453666940407 408 1903 V 0 +­­¨©|140910176|­­¨© 0 0 0 18544 134924240 \295\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00092652486360628660226 0.020810501074798998938 408 1904 V 0 +­­¨©|140911088|­­¨© 0 0 0 18544 134924240 \295\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737559321710705262 1.8010872009926000015 408 1905 V 0 +­­¨©|140912000|­­¨© 0 0 0 18544 134924240 \296\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00092650832569820716026 0.020811409070592756798 408 1906 V 0 +­­¨©|140912912|­­¨© 0 0 0 18544 134924240 \296\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737137429229585806 1.8010813772525318122 408 1907 V 0 +­­¨©|140913824|­­¨© 0 0 0 18544 134924240 \297\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00092645774781793539376 0.020810295290558038922 408 1908 V 0 +­­¨©|140914736|­­¨© 0 0 0 18544 134924240 \297\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736924135087008825 1.8010820832137655056 408 1909 V 0 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3.0000000000000003936e-08 -0.00093695258002610463076 0.020822847552697931056 408 1916 V 0 +­­¨©|140922032|­­¨© 0 0 0 18544 134924240 \301\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7835922619294697355 1.8006625987207316442 408 1917 V 0 +­­¨©|140922944|­­¨© 0 0 0 18544 134924240 \302\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094168227737876763345 0.020823236160464646954 408 1918 V 0 +­­¨©|140923856|­­¨© 0 0 0 18544 134924240 \302\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7836019303873256181 1.8006689665244064447 408 1919 V 0 +­­¨©|140924768|­­¨© 0 0 0 18544 134924240 \303\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00093848388713565838396 0.020825300747169175203 408 1920 V 0 +­­¨©|140925680|­­¨© 0 0 0 18544 134924240 \303\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7835350926483051204 1.8006758455841849198 408 1921 V 0 +­­¨©|140926592|­­¨© 0 0 0 18544 134924240 \304\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00093826405923816511446 0.020822053764033558731 408 1922 V 0 +­­¨©|140927504|­­¨© 0 0 0 18544 134924240 \304\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834945464837494988 1.8006800616755969102 408 1923 V 0 +­­¨©|140928416|­­¨© 0 0 0 18544 134924240 \305\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094307449203495934305 0.020833491246569909444 408 1924 V 0 +­­¨©|140929328|­­¨© 0 0 0 18544 134924240 \305\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834793256353056456 1.8006816442326643024 408 1925 V 0 +­­¨©|140930240|­­¨© 0 0 0 18544 134924240 \306\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094598674443214603256 0.020838687250590549882 408 1926 V 0 +­­¨©|140931152|­­¨© 0 0 0 18544 134924240 \306\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834897944702841066 1.8006816505945559825 408 1927 V 0 +­­¨©|140932064|­­¨© 0 0 0 18544 134924240 \307\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094598497678408989282 0.020842030417182424995 408 1928 V 0 +­­¨©|140932976|­­¨© 0 0 0 18544 134924240 \307\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7737138163449703843 1.8010813531169034274 408 1929 V 0 +­­¨©|140933888|­­¨© 0 0 0 18544 134924240 \308\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094770266659127786347 0.020841232086687602743 408 1930 V 0 +­­¨©|140934800|­­¨© 0 0 0 18544 134924240 \308\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736969015408281525 1.8010820698884679736 408 1931 V 0 +­­¨©|140935712|­­¨© 0 0 0 18544 134924240 \309\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094767101925285004722 0.020834508852251236444 408 1932 V 0 +­­¨©|140936624|­­¨© 0 0 0 18544 134924240 \309\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.773646303893291476 1.8010835616421205785 408 1933 V 0 +­­¨©|140937536|­­¨© 0 0 0 18544 134924240 \310\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00094769935199432342628 0.020869344955909079065 408 1934 V 0 +­­¨©|140938448|­­¨© 0 0 0 18544 134924240 \310\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735946457951137223 1.8010852392735956506 408 1935 V 0 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3.0000000000000003936e-08 -0.00095457867121828644461 0.020841917883407900386 408 1942 V 0 +­­¨©|140945744|­­¨© 0 0 0 18544 134924240 \314\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7736227510023845344 1.8010843484674088355 408 1943 V 0 +­­¨©|140946656|­­¨© 0 0 0 18544 134924240 \315\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.0009545599487787934925 0.020842023745449207023 408 1944 V 0 +­­¨©|140947568|­­¨© 0 0 0 18544 134924240 \315\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7835398108887901003 1.8006689502810169223 408 1945 V 0 +­­¨©|140948480|­­¨© 0 0 0 18544 134924240 \316\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00095741851380943198638 0.020842102639027405148 408 1946 V 0 +­­¨©|140949392|­­¨© 0 0 0 18544 134924240 \316\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7835323283553592422 1.8006758825176345518 408 1947 V 0 +­­¨©|140950304|­­¨© 0 0 0 18544 134924240 \317\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00096264658132322788921 0.020842435616677333632 408 1948 V 0 +­­¨©|140951216|­­¨© 0 0 0 18544 134924240 \317\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834945135151194506 1.8006800673397227452 408 1949 V 0 +­­¨©|140952128|­­¨© 0 0 0 18544 134924240 \318\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00096316509962049781657 0.020842547742653351472 408 1950 V 0 +­­¨©|140953040|­­¨© 0 0 0 18544 134924240 \318\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834212519537342434 1.8006874222585547152 408 1951 V 0 +­­¨©|140953952|­­¨© 0 0 0 18544 134924240 \319\:gnd! 0 1 18544 0 3.0000000000000003936e-08 -0.00095739805601973218541 0.020842044364730409611 408 1952 V 0 +­­¨©|140954864|­­¨© 0 0 0 18544 134924240 \319\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833860115789452738 1.8006900954627194089 408 1953 V 0 +­­¨©|140959888|­­¨© 0 0 0 18544 134924240 \320\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833855189155158882 1.8006900791842481713 408 1954 V 0 +­­¨©|140960816|­­¨© 0 0 0 18544 134924240 \321\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735899793508027589 1.8010857779442726034 408 1955 V 0 +­­¨©|140961728|­­¨© 0 0 0 18544 134924240 \322\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735518711628193156 1.8010865515909597612 408 1956 V 0 +­­¨©|140962640|­­¨© 0 0 0 18544 134924240 \323\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735396100736722236 1.8010869130014282025 408 1957 V 0 +­­¨©|140963552|­­¨© 0 0 0 18544 134924240 \324\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7735397927837377452 1.8010868867621272482 408 1958 V 0 +­­¨©|140964464|­­¨© 0 0 0 18544 134924240 \325\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7834096089648334704 1.8006952848933874822 408 1959 V 0 +­­¨©|140965376|­­¨© 0 0 0 18544 134924240 \326\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833693995487411854 1.8006913592700364291 408 1960 V 0 +­­¨©|140966288|­­¨© 0 0 0 18544 134924240 \327\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833475678701085076 1.8006930304606862947 408 1961 V 0 +­­¨©|140967200|­­¨© 0 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1.8010884024831199657 408 1968 V 0 +­­¨©|140973584|­­¨© 0 0 0 18544 134924240 \335\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833673201021909005 1.8006914046800563955 408 1969 V 0 +­­¨©|140974496|­­¨© 0 0 0 18544 134924240 \336\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7833048120104637579 1.8006998872273676238 408 1970 V 0 +­­¨©|140975408|­­¨© 0 0 0 18544 134924240 \337\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832889165145837662 1.8006971328158678514 408 1971 V 0 +­­¨©|140976320|­­¨© 0 0 0 18544 134924240 \338\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832462035755971552 1.8007001935231674583 408 1972 V 0 +­­¨©|140977232|­­¨© 0 0 0 18544 134924240 \339\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7831974888357813303 1.8007036980432042927 408 1973 V 0 +­­¨©|140978144|­­¨© 0 0 0 18544 134924240 \340\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832163466486081749 1.8007037060728909861 408 1974 V 0 +­­¨©|140979056|­­¨© 0 0 0 18544 134924240 \341\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7733911302308189573 1.8010877114839851654 408 1975 V 0 +­­¨©|140979968|­­¨© 0 0 0 18544 134924240 \342\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734835615392694486 1.8010894635982663825 408 1976 V 0 +­­¨©|140980880|­­¨© 0 0 0 18544 134924240 \343\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734825343180100621 1.8010910094651852997 408 1977 V 0 +­­¨©|140981792|­­¨© 0 0 0 18544 134924240 \344\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734818191968311218 1.8010920513588737357 408 1978 V 0 +­­¨©|140982704|­­¨© 0 0 0 18544 134924240 \345\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734830682535931423 1.8010920524735565262 408 1979 V 0 +­­¨©|140983616|­­¨© 0 0 0 18544 134924240 \346\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734981583817321926 1.8010920596459629728 408 1980 V 0 +­­¨©|140984528|­­¨© 0 0 0 18544 134924240 \347\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7832888353268359083 1.8006971400406928119 408 1981 V 0 +­­¨©|140985440|­­¨© 0 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1.8010910426364690196 408 1988 V 0 +­­¨©|140991824|­­¨© 0 0 0 18544 134924240 \355\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.773462578784481769 1.801097778547567474 408 1989 V 0 +­­¨©|140992736|­­¨© 0 0 0 18544 134924240 \356\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734830809071859825 1.8010920534739343069 408 1990 V 0 +­­¨©|140993648|­­¨© 0 0 0 18544 134924240 \357\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7831962407805765913 1.8007052013652875555 408 1991 V 0 +­­¨©|140994560|­­¨© 0 0 0 18544 134924240 \358\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7831630550085750819 1.8007101590821694703 408 1992 V 0 +­­¨©|140995472|­­¨© 0 0 0 18544 134924240 \359\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7831634619167697764 1.8007102286373157796 408 1993 V 0 +­­¨©|140996384|­­¨© 0 0 0 18544 134924240 \360\:vdd! 0 1 18544 0 3.0000000000000003936e-08 1.7734831679789384573 1.8010920603577205146 408 1994 V 0 +­­¨©|140997296|­­¨© 0 0 0 18544 134924240 \361\:vdd! 0 1 18544 0 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a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.includedModels b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/.includedModels similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.includedModels rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/.includedModels diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.modelFiles b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/.modelFiles similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.modelFiles rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/.modelFiles diff --git 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a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__multiplefiles_amap_format__ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__multiplefiles_amap_format__ rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__new_amap_format__ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__new_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__new_amap_format__ rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__new_amap_format__ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__nmp_amap_format__ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__nmp_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__nmp_amap_format__ rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__nmp_amap_format__ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__simulator_information__ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__simulator_information__ similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/__simulator_information__ rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/__simulator_information__ diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/and2.inst b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/and2.inst new file mode 100644 index 0000000000000000000000000000000000000000..4933c454c10e3a11bb2dd86ecb6e5466e9f769f0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/and2.inst @@ -0,0 +1,5 @@ +HEADER +"PSFversion" "1.00" +"re3n rf1n rf2n rf3n rf4n rf5n rf6n rf7n rf8n rf9n rf10n rf11n rf13n rf14n rf15n rf16n rf17n rf18n rg1n rg2n rg3n rg4n rg5n rg6n rg7n rg8n rg9n" "analogLib_presistor_spectre" +"MP2n MP1n MP0n" "gpdk_pmos_spectre" +"MN2n MN1n MN0n" "gpdk_nmos_spectre" diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/multiplier_4X4_multiplier_schematic.net b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/and2.net similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/multiplier_4X4_multiplier_schematic.net rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/and2.net diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/and2.port b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/and2.port similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/and2.port rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/and2.port diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/gpdk_nmos_spectre.inst b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/gpdk_nmos_spectre.inst rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/gpdk_pmos_spectre.inst b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/gpdk_pmos_spectre.inst rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/top_level_map.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/top_level_map.inst rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/top_level_map.inst diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/top_level_map.net similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/top_level_map.net rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/top_level_map.net diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/top_level_map.port similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/top_level_map.port rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/amap/top_level_map.port diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/control b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/control rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/emir.conf b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/emir.conf rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..64ab6011cc8cb49bcc4f83edafea14b0705d3fba --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low and2 av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..c6bf73452231c80d72a56678a55597a7be7f8331 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds0/map b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds0/map rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds0/map.ext b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds0/map.ext rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..410449bb1c12d21fd1be562d4d343693a110494b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,43 @@ + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..69f194be2eb8a18bc3d6adcde50465bbc9cf0f6f --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/and2/av_extracted and2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..bf36114917ed1231e376f839f6a172ee92223219 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 2:48:13 AM, Thur May 27, 2021 (process id: 161291). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre5_6429_5" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x7ee25e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..90a2475b528410b11bb5e1519231929b54de2b99 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,66 @@ +// Generated for: spectre +// Generated on: May 27 02:48:12 2021 +// Design library name: multiplier_low +// Design cell name: and2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_AND_C1.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..cfb39b5b81e775c495d72c14c2a3111791fe10d2 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "and2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/and2_C1/and2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/and2/av_extracted" "and2" ) + ) +( term + ) +( param + ) +( "and2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/map/current.ext b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..410449bb1c12d21fd1be562d4d343693a110494b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,43 @@ + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/netlistFooter b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..d29b355d315539878bb42fb6efb2d1d8b3f5b85d --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 02:48:12 2021 +// Design library name: multiplier_low +// Design cell name: and2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..b72dba651b63cb5211b2a66d697d881a38cbecd4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre5_6429_5 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..af9a891fb7b7b9110c66b73f700e85622217e906 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "and2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..ca0fb6e7bf77e4ca5e920786b097a7f74ba85493 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 02:48:12 2021 +End netlisting May 27 02:48:12 2021 diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..dc1de05102d69631ba75a727123cf7c4dffe5298 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,54 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:48:13 AM, Thur May 27, 2021 +# Number of equations = 35 +1\:A 1.79999999989493 +1\:B 1.80000000006714 +1\:gnd! 8.37356903321995e-12 +1\:Out 1.79999995502691 +1\:vdd! 1.79999999995034 +2\:B 1.80000000018737 +2\:gnd! 9.06922479048175e-13 +2\:net013 1.25202134144994e-08 +2\:Out 1.79999995469434 +2\:vdd! 1.79999999999321 +3\:A 1.79999999446462 +3\:B 1.80000000109786 +3\:gnd! -6.33906703838388e-13 +3\:net013 1.24852653617823e-08 +3\:Out 1.79999995460335 +3\:vdd! 1.7999999999996 +4\:A 1.7999999997068 +4\:B 1.80000000177094 +4\:net013 1.24531694833943e-08 +4\:Out 1.7999999546917 +4\:vdd! 1.79999999999798 +5\:A 1.80000000015338 +5\:gnd! -1.07275432488709e-11 +5\:net013 1.68377239436748e-08 +5\:vdd! 1.79999999999689 +6\:net013 1.71798166478435e-08 +7\:net013 4.51269482934844e-08 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d -1.44424274288925e-08 +MN0:int_s 1.22998934752955e-08 +MN1:int_d -6.76025254383151e-11 +MN1:int_s -1.45729597307874e-08 +MN2:int_d 1.79999995466955 +MN2:int_s 4.37901403002178e-11 +MP0:int_d 1.23656909726193e-08 +MP0:int_s 1.79999999999271 +MP1:int_d 1.79999999998825 +MP1:int_s 1.23625896009723e-08 +MP2:int_d 1.79999995438832 +MP2:int_s 1.79999999981375 +net9 -1.450769357984e-08 +net013 1.25768511214696e-08 +Out 1.7999999550271 +v0:p 9.31696159530506e-12 +v1:p -5.00314217630134e-11 +v2:p 0 +v3:p 3.19721856993733e-11 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..77494e1f7579e4bbe7109369eba14900a210a4ed --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,54 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:48:13 AM, Thur May 27, 2021 +# Number of equations = 35 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 9.39371213007968e-12 +1\:Out 1.79999995310683 +1\:vdd! 1.79999999999031 +2\:B 1.8 +2\:gnd! 2.76380694289141e-12 +2\:net013 1.17747103916187e-08 +2\:Out 1.79999995310683 +2\:vdd! 1.79999999999867 +3\:A 1.8 +3\:B 1.8 +3\:gnd! 1.39564905325848e-12 +3\:net013 1.17717322791172e-08 +3\:Out 1.79999995311812 +3\:vdd! 1.79999999999949 +4\:A 1.8 +4\:B 1.8 +4\:net013 1.1779748558852e-08 +4\:Out 1.79999995310308 +4\:vdd! 1.79999999999744 +5\:A 1.8 +5\:gnd! 4.19907037143905e-12 +5\:net013 1.17747103916187e-08 +5\:vdd! 1.79999999999759 +6\:net013 1.17747103916187e-08 +7\:net013 1.17747103916187e-08 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 5.90376216674455e-09 +MN0:int_s 1.17559357385481e-08 +MN1:int_d 1.99956107788205e-11 +MN1:int_s 5.87216908584883e-09 +MN2:int_d 1.7999999530716 +MN2:int_s 4.08413650827026e-11 +MP0:int_d 1.17864388583871e-08 +MP0:int_s 1.79999999999076 +MP1:int_d 1.79999999999091 +MP1:int_s 1.17864388583872e-08 +MP2:int_d 1.79999995314478 +MP2:int_s 1.79999999996364 +net9 5.88796562629669e-09 +net013 1.17747103916187e-08 +Out 1.79999995310683 +v0:p -2.78130408280359e-11 +v1:p 0 +v2:p 0 +v3:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/spectre.inp b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/spectre.sim b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/.simDone b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/.simDone rename to involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..108eccad9410c65a16b7bee7b755c54ca03ba5f0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:48:12 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..5f76a90618be4f99bdafddee638314097f2fdf86 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:48:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..67e2c63b4d8e91746596bb4c161067eb9d60ea28 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..ea6424cf976ca8f618e0021c5f6c2e051be017cb Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..e24db81f4bc8a5e4f232d45bd4260b9cdab1ee82 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:48:13 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:48:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..045e3fcfb884338378e0ad056065700852970ea0 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..fe8306e0bcaf2a933f307c5a951831472b270a03 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..613105f6820865e254caa6364af270a4f297c2fd --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:48:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod 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pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..5b35a301e9cfa82c36a923a7f8b3dc5c8b5883f4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 02:48:14 2021" +"simulator" "spectre" +"date" "May 27 02:48:14 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..6eb4cfa1e8586b46210983b7d710bc550a40811b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"and2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 02:48:12 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..d97eb04496fdc37b086abcba6de9cdd0ad966c10 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,264 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 161291 +Memory available: 1.7903 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 1200.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 1200.0 30.6 + 3 0 3 2201.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 2201.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 1200.0 41.9 + 12 1 2 1200.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 2201.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 2201.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 2201.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 2:48:13 AM, Thur May 27, 2021 (process id: 161291). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/and2_C1/and2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre5_6429_5 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 161291 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/and2_C1/and2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_AND_C1.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 70.989 ms, elapsed = 117.314 ms. +Time accumulated: CPU = 104.983 ms, elapsed = 117.319 ms. +Peak resident memory used = 38.8 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 26.996 ms, elapsed = 26.947 ms. +Time accumulated: CPU = 131.979 ms, elapsed = 144.441 ms. +Peak resident memory used = 43.6 Mbytes. + +Time for EDB Visiting: CPU = 1 ms, elapsed = 826.12 us. +Time accumulated: CPU = 132.979 ms, elapsed = 145.438 ms. +Peak resident memory used = 44.1 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 34 + bsim3v3 6 + capacitor 1 + resistor 27 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 3 ms, elapsed = 264.682 ms. +Time accumulated: CPU = 135.979 ms, elapsed = 410.328 ms. +Peak resident memory used = 45.1 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre5_6429_5, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 1 ms, elapsed = 1.38593 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 34 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.26 ns (7.53 %), step = 14.5 ps (48.3 m%) + +Notice from spectre at time = 4.17127 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. + + tran: time = 4.171 ns (13.9 %), step = 600 ps (2 %) + tran: time = 5.432 ns (18.1 %), step = 269.5 ps (898 m%) + +Notice from spectre at time = 5.97057 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. +Notice from spectre at time = 6.4 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. + + tran: time = 7 ns (23.3 %), step = 600 ps (2 %) + tran: time = 8.8 ns (29.3 %), step = 600 ps (2 %) + tran: time = 10 ns (33.3 %), step = 600 ps (2 %) + +Notice from spectre at time = 11.2 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. +Notice from spectre at time = 11.8 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. + Further occurrences of this notice will be suppressed. + + tran: time = 11.8 ns (39.3 %), step = 600 ps (2 %) + tran: time = 13 ns (43.3 %), step = 600 ps (2 %) + tran: time = 14.8 ns (49.3 %), step = 600 ps (2 %) + tran: time = 16 ns (53.3 %), step = 600 ps (2 %) + tran: time = 17.8 ns (59.3 %), step = 600 ps (2 %) + tran: time = 19 ns (63.3 %), step = 600 ps (2 %) + tran: time = 20.8 ns (69.3 %), step = 600 ps (2 %) + tran: time = 22 ns (73.3 %), step = 600 ps (2 %) + tran: time = 23.8 ns (79.3 %), step = 600 ps (2 %) + tran: time = 25 ns (83.3 %), step = 600 ps (2 %) + tran: time = 26.8 ns (89.3 %), step = 600 ps (2 %) + tran: time = 28 ns (93.3 %), step = 600 ps (2 %) + tran: time = 29.6 ns (98.7 %), step = 400 ps (1.33 %) +Number of accepted tran steps = 127 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1.999 ms, elapsed = 1.53089 ms. +Intrinsic tran analysis time: CPU = 22.997 ms, elapsed = 88.98 ms. +Total time required for tran analysis `tran': CPU = 27.996 ms, elapsed = 94.4769 ms. +Time accumulated: CPU = 167.974 ms, elapsed = 860.637 ms. +Peak resident memory used = 47 Mbytes. + + +Notice from spectre. + 31 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (2:49:16 AM, Thur May 27, 2021): +Time used: CPU = 244 ms, elapsed = 62.4 s (1m 2.4s), util. = 391e-03%. +Time spent in licensing: elapsed = 59.3 ms. +Peak memory used = 47.4 Mbytes. +Simulation started at: 2:48:13 AM, Thur May 27, 2021, ended at: 2:49:16 AM, Thur May 27, 2021, with elapsed time (wall clock): 62.4 s (1m 2.4s). +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..e65ada7bbaf4d12e32a84c3e43107ed08491085b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:48:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..aa204da90540c957526f435d0f94867f77cfb861 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/and2_C1/and2/spectre/av_extracted/psf/tran.tran.0.sig.tmp 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file mode 100644 index 0000000000000000000000000000000000000000..4933c454c10e3a11bb2dd86ecb6e5466e9f769f0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/and2.inst @@ -0,0 +1,5 @@ +HEADER +"PSFversion" "1.00" +"re3n rf1n rf2n rf3n rf4n rf5n rf6n rf7n rf8n rf9n rf10n rf11n rf13n rf14n rf15n rf16n rf17n rf18n rg1n rg2n rg3n rg4n rg5n rg6n rg7n rg8n rg9n" "analogLib_presistor_spectre" +"MP2n MP1n MP0n" "gpdk_pmos_spectre" +"MN2n MN1n MN0n" "gpdk_nmos_spectre" diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/and2.net b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/and2.net new file mode 100644 index 0000000000000000000000000000000000000000..01741c91f43710b7791fb7f16ba86ec10727a969 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/and2.net @@ -0,0 +1,4 @@ +HEADER +"PSFversion" "1.00" +"gnd!v" "0v" +"vdd!v" "vdd!v" diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/and2.port b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/and2.port similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/and2.port rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/and2.port diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/top_level_map.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/top_level_map.inst rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/top_level_map.inst diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/top_level_map.net similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/top_level_map.net rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/top_level_map.net diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/top_level_map.port similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/top_level_map.port rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/amap/top_level_map.port diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..64ab6011cc8cb49bcc4f83edafea14b0705d3fba --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low and2 av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..c6bf73452231c80d72a56678a55597a7be7f8331 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds1/map b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds1/map rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds1/map.ext b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds1/map.ext rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..410449bb1c12d21fd1be562d4d343693a110494b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,43 @@ + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..69f194be2eb8a18bc3d6adcde50465bbc9cf0f6f --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/and2/av_extracted and2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..3a9dea1104601df3fb5305ebb9dfef9011b31563 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 2:49:31 AM, Thur May 27, 2021 (process id: 170492). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre5_6429_6" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x6fa85e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..a17ef2404ecb411285b52f822cf2266d02d216a3 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,66 @@ +// Generated for: spectre +// Generated on: May 27 02:49:30 2021 +// Design library name: multiplier_low +// Design cell name: and2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_AND_C2.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..3ef483ad8ac3562562a281d41b6461eac268ec0f --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "and2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/and2_C2/and2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/and2/av_extracted" "and2" ) + ) +( term + ) +( param + ) +( "and2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..410449bb1c12d21fd1be562d4d343693a110494b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,43 @@ + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..14f4da00396f7415003ad0b740658900c2978573 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 02:49:30 2021 +// Design library name: multiplier_low +// Design cell name: and2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..2c114d9a754893eeb7416af5607228ffc3e7c525 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre5_6429_6 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..af9a891fb7b7b9110c66b73f700e85622217e906 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "and2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..4cf17988bea66f831da07124d352bb84f06ab74a --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 02:49:30 2021 +End netlisting May 27 02:49:30 2021 diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..69e30efcb3b73ba7fd56ef124e49b5425ef94eda --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,54 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:49:31 AM, Thur May 27, 2021 +# Number of equations = 35 +1\:A 1.80000000072663 +1\:B 1.79999999988314 +1\:gnd! -2.15155621931823e-13 +1\:Out 1.79999995277063 +1\:vdd! 1.7999999996567 +2\:B 1.7999999996739 +2\:gnd! 1.43912470165864e-12 +2\:net013 9.02567022707678e-09 +2\:Out 1.79999995466949 +2\:vdd! 1.79999999995303 +3\:A 1.80000002953209 +3\:B 1.79999999895351 +3\:gnd! 1.78050464789957e-12 +3\:net013 9.0136471070354e-09 +3\:Out 1.79999995528068 +3\:vdd! 1.79999999999752 +4\:A 1.80000000202779 +4\:B 1.79999999564121 +4\:net013 9.09302566454072e-09 +4\:Out 1.79999995465409 +4\:vdd! 1.7999999999876 +5\:A 1.80000000486337 +5\:gnd! 1.38695730981468e-11 +5\:net013 1.00601110566754e-08 +5\:vdd! 1.79999999999781 +6\:net013 7.28928610142845e-09 +7\:net013 -1.12351441826865e-08 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 3.09925255140743e-08 +MN0:int_s 8.94987392740875e-09 +MN1:int_d 8.19882882636098e-11 +MN1:int_s 3.13391143463693e-08 +MN2:int_d 1.799999954525 +MN2:int_s -8.06190938896246e-12 +MP0:int_d 9.17004643075612e-09 +MP0:int_s 1.79999999995529 +MP1:int_d 1.79999999999175 +MP1:int_s 9.19489060461099e-09 +MP2:int_d 1.79999995672489 +MP2:int_s 1.79999999871243 +net9 3.11658199302218e-08 +net013 9.00456439244423e-09 +Out 1.7999999527695 +v0:p -1.0010145973091e-09 +v1:p 3.46015267454556e-10 +v2:p 0 +v3:p -5.56454301946757e-11 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..081628033d7db86d4725eb4e3edbc64d6192484c --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,54 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:49:31 AM, Thur May 27, 2021 +# Number of equations = 35 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 9.39371213007968e-12 +1\:Out 1.79999995310683 +1\:vdd! 1.79999999999031 +2\:B 1.8 +2\:gnd! 2.76380694289141e-12 +2\:net013 1.17747103916187e-08 +2\:Out 1.79999995310683 +2\:vdd! 1.79999999999867 +3\:A 1.8 +3\:B 1.8 +3\:gnd! 1.39564905325848e-12 +3\:net013 1.17717322791172e-08 +3\:Out 1.79999995311812 +3\:vdd! 1.79999999999949 +4\:A 1.8 +4\:B 1.8 +4\:net013 1.1779748558852e-08 +4\:Out 1.79999995310308 +4\:vdd! 1.79999999999744 +5\:A 1.8 +5\:gnd! 4.19907037143905e-12 +5\:net013 1.17747103916187e-08 +5\:vdd! 1.79999999999759 +6\:net013 1.17747103916187e-08 +7\:net013 1.17747103916187e-08 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 5.90376216674455e-09 +MN0:int_s 1.17559357385481e-08 +MN1:int_d 1.99956107788205e-11 +MN1:int_s 5.87216908584883e-09 +MN2:int_d 1.7999999530716 +MN2:int_s 4.08413650827026e-11 +MP0:int_d 1.17864388583871e-08 +MP0:int_s 1.79999999999076 +MP1:int_d 1.79999999999091 +MP1:int_s 1.17864388583872e-08 +MP2:int_d 1.79999995314478 +MP2:int_s 1.79999999996364 +net9 5.88796562629669e-09 +net013 1.17747103916187e-08 +Out 1.79999995310683 +v0:p -2.78130408280359e-11 +v1:p 0 +v2:p 0 +v3:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..fd00c5997fe05260a26d12bd8030a8cb59646a85 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:49:29 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..50aea1e93991617f17a7dd61bd4dc5b9a25cff75 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:49:31 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..6029c44cf682e412e82d441cf4ff7270a441b5df Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..0460dc07b6b4c07fe2817a864741aad52544dc23 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..28d8b1bcede9025391006bcd4149b230dd1d063c --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:49:31 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:49:31 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..d0b75df7b786069dc919a7c0ee5d7f2c51a351be Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..8f9a4f756b823d06472c0d2ffac8c28e21cb8187 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..49f76c0c6b41e41fcbe0c2dc3c3099abb788cf77 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:49:31 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs 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+"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..27e57d7e389644bd3659d6a10ca38a2aaf031dfa --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 02:49:33 2021" +"simulator" "spectre" +"date" "May 27 02:49:33 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..a6bcbdec8e90fb98f268441f32976f552c8035c7 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"and2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 02:49:29 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..f03ed4dac4007ea6aa3192ca127ac06a6e25ff8a --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,262 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 170492 +Memory available: 1.7903 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 1200.0 37.1 + 1 0 1 2201.0 42.5 + 2 0 2 2201.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 2201.0 41.9 + 12 1 2 1200.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 2201.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 2201.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 2:49:31 AM, Thur May 27, 2021 (process id: 170492). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/and2_C2/and2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre5_6429_6 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 170492 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/and2_C2/and2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_AND_C2.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 77.988 ms, elapsed = 124.607 ms. +Time accumulated: CPU = 103.983 ms, elapsed = 124.612 ms. +Peak resident memory used = 38.8 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 28.996 ms, elapsed = 28.8501 ms. +Time accumulated: CPU = 132.979 ms, elapsed = 153.651 ms. +Peak resident memory used = 43.6 Mbytes. + +Time for EDB Visiting: CPU = 0 s, elapsed = 823.975 us. +Time accumulated: CPU = 133.979 ms, elapsed = 154.692 ms. +Peak resident memory used = 44.1 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 34 + bsim3v3 6 + capacitor 1 + resistor 27 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 1.999 ms, elapsed = 114.602 ms. +Time accumulated: CPU = 136.978 ms, elapsed = 269.478 ms. +Peak resident memory used = 45.1 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre5_6429_6, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 1 ms, elapsed = 1.20997 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 34 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.261 ns (7.54 %), step = 14.28 ps (47.6 m%) + +Notice from spectre at time = 3.64411 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. +Notice from spectre at time = 4.00967 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. + + tran: time = 4.01 ns (13.4 %), step = 365.6 ps (1.22 %) + +Notice from spectre at time = 4.10725 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. +Notice from spectre at time = 4.15604 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. +Notice from spectre at time = 4.18044 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. + Further occurrences of this notice will be suppressed. + + tran: time = 5.294 ns (17.6 %), step = 212 ps (707 m%) + tran: time = 7.064 ns (23.5 %), step = 393.3 ps (1.31 %) + tran: time = 8.66 ns (28.9 %), step = 600 ps (2 %) + tran: time = 9.86 ns (32.9 %), step = 600 ps (2 %) + tran: time = 11.66 ns (38.9 %), step = 600 ps (2 %) + tran: time = 12.86 ns (42.9 %), step = 600 ps (2 %) + tran: time = 14.66 ns (48.9 %), step = 600 ps (2 %) + tran: time = 15.86 ns (52.9 %), step = 600 ps (2 %) + tran: time = 17.66 ns (58.9 %), step = 600 ps (2 %) + tran: time = 18.86 ns (62.9 %), step = 600 ps (2 %) + tran: time = 20.66 ns (68.9 %), step = 600 ps (2 %) + tran: time = 21.86 ns (72.9 %), step = 600 ps (2 %) + tran: time = 23.66 ns (78.9 %), step = 600 ps (2 %) + tran: time = 24.86 ns (82.9 %), step = 600 ps (2 %) + tran: time = 26.66 ns (88.9 %), step = 600 ps (2 %) + tran: time = 27.86 ns (92.9 %), step = 600 ps (2 %) + tran: time = 29.53 ns (98.4 %), step = 469.8 ps (1.57 %) +Number of accepted tran steps = 129 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1.999 ms, elapsed = 1.32108 ms. +Intrinsic tran analysis time: CPU = 18.997 ms, elapsed = 69.515 ms. +Total time required for tran analysis `tran': CPU = 23.996 ms, elapsed = 74.929 ms. +Time accumulated: CPU = 164.974 ms, elapsed = 1.79007 s. +Peak resident memory used = 47.1 Mbytes. + + +Notice from spectre. + 32 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (2:50:07 AM, Thur May 27, 2021): +Time used: CPU = 224 ms, elapsed = 36.5 s, util. = 614e-03%. +Time spent in licensing: elapsed = 63.4 ms. +Peak memory used = 47.4 Mbytes. +Simulation started at: 2:49:31 AM, Thur May 27, 2021, ended at: 2:50:07 AM, Thur May 27, 2021, with elapsed time (wall clock): 36.5 s. +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..31f57d07766d0bffff9d744291a3435c42f41ea5 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C2/and2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" 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b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..64ab6011cc8cb49bcc4f83edafea14b0705d3fba --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low and2 av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..c6bf73452231c80d72a56678a55597a7be7f8331 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds2/map b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds2/map rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds2/map.ext b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds2/map.ext rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..410449bb1c12d21fd1be562d4d343693a110494b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,43 @@ + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..69f194be2eb8a18bc3d6adcde50465bbc9cf0f6f --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/and2/av_extracted and2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..f830022e5947903c8106982a67dc7c4db31dfa17 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 2:53:38 AM, Thur May 27, 2021 (process id: 3236). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre5_6429_8" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x78105e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..7c74f92d336620882faf4a8a1d8db6792e7c055c --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,66 @@ +// Generated for: spectre +// Generated on: May 27 02:53:35 2021 +// Design library name: multiplier_low +// Design cell name: and2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_AND_C3.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..0974d894550b33da7b0faf2bc90fa51d9578d5af --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "and2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/and2_C3/and2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/and2/av_extracted" "and2" ) + ) +( term + ) +( param + ) +( "and2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..410449bb1c12d21fd1be562d4d343693a110494b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,43 @@ + +// Library name: multiplier_low +// Cell name: and2 +// View name: av_extracted +re3 (\1\:Out Out) resistor r=0.001222 c=0 +rf1 (\1\:A A) resistor r=2.1 c=0 +rf2 (net013 \2\:net013) resistor r=0.2434 c=0 +rf3 (\2\:net013 \3\:net013) resistor r=0.3205 c=0 +rf4 (\2\:net013 \4\:net013) resistor r=0.5422 c=0 +rf5 (\1\:B B) resistor r=2.1 c=0 +rf6 (\1\:Out \2\:Out) resistor r=2.0484 c=0 +rf7 (\2\:Out \3\:Out) resistor r=0.6094 c=0 +rf8 (\2\:Out \4\:Out) resistor r=0.2028 c=0 +rf9 (\1\:gnd! \2\:gnd!) resistor r=0.3584 c=0 +rf10 (\2\:gnd! \3\:gnd!) resistor r=0.07396 c=0 +rf11 (\3\:gnd! 0) resistor r=0.05022 c=0 +rf13 (\3\:gnd! \5\:gnd!) resistor r=0.3017 c=0 +rf14 (\1\:vdd! \2\:vdd!) resistor r=0.4519 c=0 +rf15 (\2\:vdd! vdd!) resistor r=0.07163 c=0 +rf16 (vdd! \3\:vdd!) resistor r=0.1107 c=0 +rf17 (\3\:vdd! \4\:vdd!) resistor r=0.4419 c=0 +rf18 (vdd! \5\:vdd!) resistor r=0.5193 c=0 +rg1 (\3\:A \4\:A) resistor r=91.5933 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=62.0099 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=62.0099 c=0 +rg6 (\2\:B \4\:B) resistor r=91.5933 c=0 +rg7 (\5\:net013 \6\:net013) resistor r=37.6755 c=0 +rg8 (\6\:net013 net013) resistor r=19.7812 c=0 +rg9 (\6\:net013 \7\:net013) resistor r=115.592 c=0 +MP2 (\3\:Out \7\:net013 \1\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\5\:vdd! \3\:B \4\:net013 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\4\:net013 \5\:A \4\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\4\:Out \5\:net013 \1\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\5\:gnd! \4\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \3\:A \3\:net013 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..d25a838c7893b98e644cca7befba3922c42417bb --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 02:53:35 2021 +// Design library name: multiplier_low +// Design cell name: and2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..f4cd104507e54da314489832ccfb9c722332b23b --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre5_6429_8 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..af9a891fb7b7b9110c66b73f700e85622217e906 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "and2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..b5134e73819d3c3aa6515be6ce25d43d51de0a66 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,54 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:53:38 AM, Thur May 27, 2021 +# Number of equations = 35 +1\:A 1.80000000156194 +1\:B 1.80000000080602 +1\:gnd! 1.11155090588404e-10 +1\:Out 1.79888996253998 +1\:vdd! 1.79999977574479 +2\:B 1.80000000224934 +2\:gnd! 4.03817427201552e-11 +2\:net013 1.1989290474479e-06 +2\:Out 1.79889079658795 +2\:vdd! 1.79999996931713 +3\:A 1.8000000554401 +3\:B 1.80000001439216 +3\:gnd! 2.57768409111828e-11 +3\:net013 1.19766273661145e-06 +3\:Out 1.79889104969002 +3\:vdd! 1.79999999999983 +4\:A 1.80000000435886 +4\:B 1.80000001946892 +4\:net013 1.19754240330791e-06 +4\:Out 1.7988907949332 +4\:vdd! 1.79999999999915 +5\:A 1.80000001589802 +5\:gnd! 1.21056149098951e-10 +5\:net013 1.31082633222773e-06 +5\:vdd! 1.79999999999762 +6\:net013 1.32925891963411e-06 +7\:net013 2.13814100686324e-06 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 1.29366992752148e-07 +MN0:int_s 1.19094595526364e-06 +MN1:int_d 6.57929943991911e-10 +MN1:int_s 1.25345904918053e-07 +MN2:int_d 1.79889078106206 +MN2:int_s 4.46854564293827e-10 +MP0:int_d 1.19570308447238e-06 +MP0:int_s 1.79999999999692 +MP1:int_d 1.79999999999102 +MP1:int_s 1.19569900808666e-06 +MP2:int_d 1.79889164776515 +MP2:int_s 1.79999915891768 +net9 1.273564488351e-07 +net013 1.2005132134682e-06 +Out 1.79888996204242 +v0:p -4.20152143188446e-07 +v1:p 7.4378206029245e-10 +v2:p 0 +v3:p 3.83821029418182e-10 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..81e04fd710ec9f8eac8360bc6a79c28f3bb18acc --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,54 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:53:38 AM, Thur May 27, 2021 +# Number of equations = 35 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 9.39371213007968e-12 +1\:Out 1.79999995310683 +1\:vdd! 1.79999999999031 +2\:B 1.8 +2\:gnd! 2.76380694289141e-12 +2\:net013 1.17747103916187e-08 +2\:Out 1.79999995310683 +2\:vdd! 1.79999999999867 +3\:A 1.8 +3\:B 1.8 +3\:gnd! 1.39564905325848e-12 +3\:net013 1.17717322791172e-08 +3\:Out 1.79999995311812 +3\:vdd! 1.79999999999949 +4\:A 1.8 +4\:B 1.8 +4\:net013 1.1779748558852e-08 +4\:Out 1.79999995310308 +4\:vdd! 1.79999999999744 +5\:A 1.8 +5\:gnd! 4.19907037143905e-12 +5\:net013 1.17747103916187e-08 +5\:vdd! 1.79999999999759 +6\:net013 1.17747103916187e-08 +7\:net013 1.17747103916187e-08 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 5.90376216674455e-09 +MN0:int_s 1.17559357385481e-08 +MN1:int_d 1.99956107788205e-11 +MN1:int_s 5.87216908584883e-09 +MN2:int_d 1.7999999530716 +MN2:int_s 4.08413650827026e-11 +MP0:int_d 1.17864388583871e-08 +MP0:int_s 1.79999999999076 +MP1:int_d 1.79999999999091 +MP1:int_s 1.17864388583872e-08 +MP2:int_d 1.79999995314478 +MP2:int_s 1.79999999996364 +net9 5.88796562629669e-09 +net013 1.17747103916187e-08 +Out 1.79999995310683 +v0:p -2.78130408280359e-11 +v1:p 0 +v2:p 0 +v3:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..210b0a84d51a535ed6a29e421788b845ef02e801 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:53:35 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..0005cfd87a4d17ea516f3bdf7eee07aee4f8b59a --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:53:38 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..4d5cb83ccffd60bbda00766da577c0ebf8294bf9 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..81a304373f76cda942494021bb3654503fd9aab5 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..e7d17ad45b038c61a83558661a8da61c18d5e7cf --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:53:38 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:53:38 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..0d83c5efa7c77306c5b41be30f481408581b2ee8 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..423f9652e43599354d5e4ee644b00de9dbed18ef Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..303c3c77534b4a9b151650729e03d3dda06a9a54 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:53:38 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..55fec53d6761d50b5566c8398ac989278b10750e --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 02:53:39 2021" +"simulator" "spectre" +"date" "May 27 02:53:39 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..a40c3457690cd7237710d5d02683df82dfa1341e --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"and2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 02:53:35 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..03a5cfc93c7ad5067169ce0ab1efc7d102bb9bbe --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,262 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 3236 +Memory available: 1.7527 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 1200.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 1200.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 2100.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 1200.0 41.9 + 12 1 2 2201.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 2201.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 2201.0 2.4 + 27 0 10 2201.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 2201.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 2:53:38 AM, Thur May 27, 2021 (process id: 3236). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/and2_C3/and2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre5_6429_8 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 3236 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/and2_C3/and2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_AND_C3.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 77.988 ms, elapsed = 124.283 ms. +Time accumulated: CPU = 106.983 ms, elapsed = 124.288 ms. +Peak resident memory used = 38.8 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 26.997 ms, elapsed = 27.211 ms. +Time accumulated: CPU = 134.979 ms, elapsed = 151.719 ms. +Peak resident memory used = 43.6 Mbytes. + +Time for EDB Visiting: CPU = 999 us, elapsed = 726.223 us. +Time accumulated: CPU = 135.978 ms, elapsed = 152.621 ms. +Peak resident memory used = 44.1 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 34 + bsim3v3 6 + capacitor 1 + resistor 27 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 2 ms, elapsed = 163.511 ms. +Time accumulated: CPU = 137.978 ms, elapsed = 316.276 ms. +Peak resident memory used = 45.1 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre5_6429_8, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 999 us, elapsed = 1.65606 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 34 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.25 ns (7.5 %), step = 11.8 ps (39.3 m%) + +Notice from spectre at time = 3.03582 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. +Notice from spectre at time = 3.27673 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. +Notice from spectre at time = 3.58825 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. +Notice from spectre at time = 3.99749 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. + + tran: time = 3.997 ns (13.3 %), step = 409.2 ps (1.36 %) + +Notice from spectre at time = 4.5352 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:net013. + Further occurrences of this notice will be suppressed. + + tran: time = 5.735 ns (19.1 %), step = 600 ps (2 %) + tran: time = 6.888 ns (23 %), step = 600 ps (2 %) + tran: time = 8.262 ns (27.5 %), step = 27.56 ps (91.9 m%) + tran: time = 9.867 ns (32.9 %), step = 600 ps (2 %) + tran: time = 11.6 ns (38.7 %), step = 600 ps (2 %) + tran: time = 12.8 ns (42.7 %), step = 600 ps (2 %) + tran: time = 14.6 ns (48.7 %), step = 600 ps (2 %) + tran: time = 15.8 ns (52.7 %), step = 600 ps (2 %) + tran: time = 17.6 ns (58.7 %), step = 600 ps (2 %) + tran: time = 18.8 ns (62.7 %), step = 600 ps (2 %) + tran: time = 20.6 ns (68.7 %), step = 600 ps (2 %) + tran: time = 21.8 ns (72.7 %), step = 600 ps (2 %) + tran: time = 23.6 ns (78.7 %), step = 600 ps (2 %) + tran: time = 24.8 ns (82.7 %), step = 600 ps (2 %) + tran: time = 26.6 ns (88.7 %), step = 600 ps (2 %) + tran: time = 27.8 ns (92.7 %), step = 600 ps (2 %) + tran: time = 29.6 ns (98.7 %), step = 600 ps (2 %) +Number of accepted tran steps = 119 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1.999 ms, elapsed = 1.81484 ms. +Intrinsic tran analysis time: CPU = 22.996 ms, elapsed = 97.7712 ms. +Total time required for tran analysis `tran': CPU = 30.995 ms, elapsed = 105.197 ms. +Time accumulated: CPU = 171.973 ms, elapsed = 582.378 ms. +Peak resident memory used = 47 Mbytes. + + +Notice from spectre. + 2 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (2:54:26 AM, Thur May 27, 2021): +Time used: CPU = 244 ms, elapsed = 48.1 s, util. = 507e-03%. +Time spent in licensing: elapsed = 63.1 ms. +Peak memory used = 47.4 Mbytes. +Simulation started at: 2:53:38 AM, Thur May 27, 2021, ended at: 2:54:26 AM, Thur May 27, 2021, with elapsed time (wall clock): 48.1 s. +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..df72f37fee74f95ae0e68485aa2b1a69958e7843 --- /dev/null +++ b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:53:38 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..ac7e1f1f52c5f6395dd44744db2e16fa3dd00059 Binary files /dev/null and b/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/and2_C3/and2/spectre/av_extracted/psf/tran.tran.0.sig.tmp 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involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.definitionFiles diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.designVariables b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.designVariables similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.designVariables rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.designVariables diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.includedModels b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.includedModels similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.includedModels rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.includedModels diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.inv.parameters b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.inv.parameters similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.inv.parameters rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.inv.parameters diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.modelFiles b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.modelFiles similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.modelFiles rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.modelFiles diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.specialFilesInclude b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.specialFilesInclude similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.specialFilesInclude rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.specialFilesInclude diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.stimulusFile b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.stimulusFile similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/.stimulusFile rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/.stimulusFile diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__new_amap_format__ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__new_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__new_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__new_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__nmp_amap_format__ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__nmp_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__nmp_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__nmp_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__simulator_information__ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__simulator_information__ similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/__simulator_information__ rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/__simulator_information__ diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.inst b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.inst new file mode 100644 index 0000000000000000000000000000000000000000..d679704e20c70d7609ffb64a4e2644e984f39a38 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.inst @@ -0,0 +1,5 @@ +HEADER +"PSFversion" "1.00" +"re2n re3n rf1n rf2n rf3n rf4n rf5n rf6n rf7n rg1n rg2n rg3n" "analogLib_presistor_spectre" +"MP0n" "gpdk_pmos_spectre" +"MN0n" "gpdk_nmos_spectre" diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.net b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.net new file mode 100644 index 0000000000000000000000000000000000000000..01741c91f43710b7791fb7f16ba86ec10727a969 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.net @@ -0,0 +1,4 @@ +HEADER +"PSFversion" "1.00" +"gnd!v" "0v" +"vdd!v" "vdd!v" diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/inv.port b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.port similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/inv.port rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/inv.port diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/top_level_map.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/top_level_map.inst rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/top_level_map.inst diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/top_level_map.net similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/top_level_map.net rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/top_level_map.net diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/top_level_map.port similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/top_level_map.port rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/amap/top_level_map.port diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..98b309896311b15d2fafcd1d54619c9f0ef35f87 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low inv av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..20295e214758d8001df627bc917112254cd4b837 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds3/map b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds3/map rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds3/map.ext b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds3/map.ext rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..a282c44f119dcc941b9b3c06861da61dca168363 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,20 @@ + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..7e55086b6573ce758f5375dd5faecc4129cdc15c --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/inv/av_extracted inv +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..b736e29fa10087ac0b24234c36659d527295d0d8 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 2:38:55 AM, Thur May 27, 2021 (process id: 92883). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre3_6429_2" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x75785e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..18025e9407e89d48e2417df5f016095b7ea14a83 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,43 @@ +// Generated for: spectre +// Generated on: May 27 02:38:54 2021 +// Design library name: multiplier_low +// Design cell name: inv +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/1_input_C1.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..257b98c705ad5a9d969b15767d7505aa3ab2402c --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "inv" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/inv_C1/inv/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/inv/av_extracted" "inv" ) + ) +( term + ) +( param + ) +( "inv" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..a282c44f119dcc941b9b3c06861da61dca168363 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlist @@ -0,0 +1,20 @@ + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..f31b72f5ae7590f9d3a84be846c1dbe491cb8e56 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 02:38:54 2021 +// Design library name: multiplier_low +// Design cell name: inv +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..a2a14b6f7b3f3c37a3614b03b97f5451223fa908 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre3_6429_2 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..d433d614cf54d9dc7d0a8b76041b7a8ebddcee7d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "inv" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..da8860d3f8b0fdf9d43b696b0d8fcf83b2a22ea9 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 02:38:54 2021 +End netlisting May 27 02:38:55 2021 diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..a0586e22f3d808f81b4752689d4b33ab1ccf3af7 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,27 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:38:55 AM, Thur May 27, 2021 +# Number of equations = 17 +1\:A 8.90069945767939e-07 +1\:gnd! 6.40759150051757e-10 +1\:Out 1.79999860252771 +1\:vdd! 1.80000003248181 +2\:gnd! 1.30624311673333e-08 +2\:Out 1.79999948671966 +2\:vdd! 1.80000061009485 +3\:A 3.47081474516179e-05 +3\:Out 1.7999996300643 +4\:A 2.39336208931553e-06 +4\:Out 1.80000400146933 +5\:A -2.98772157966332e-06 +A 0 +gnd! 0 +MN0:int_d 1.80000045193911 +MN0:int_s 5.33617487806514e-08 +MP0:int_d 1.79999465573164 +MP0:int_s 1.80000247880474 +Out 1.80000400417818 +v0:p 2.22625086950439e-06 +v1:p 4.22474817622907e-07 +v2:p 0 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..ad46f17f5fc88bb1e711ceadfcad5240a1fb454a --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,27 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:38:55 AM, Thur May 27, 2021 +# Number of equations = 17 +1\:A 0 +1\:gnd! 5.00017528751802e-13 +1\:Out 1.79999995312089 +1\:vdd! 1.79999999999954 +2\:gnd! 1.01932911160971e-11 +2\:Out 1.79999995311492 +2\:vdd! 1.79999999999129 +3\:A 0 +3\:Out 1.79999995310943 +4\:A 0 +4\:Out 1.79999995311492 +5\:A 0 +A 0 +gnd! 0 +MN0:int_d 1.79999995307795 +MN0:int_s 4.16409344338206e-11 +MP0:int_d 1.79999995314755 +MP0:int_s 1.79999999996463 +Out 1.79999995311492 +v0:p -1.85166559088093e-11 +v1:p 0 +v2:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..29c873024188a531c5048e852a1d542a45e657ce --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:38:54 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..c0f4103ebf60c5ab5ed43e1b426c3f647a4baf33 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:38:55 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..8b3c71512eb4b58f6e7434372a2d42f3be9ef879 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..97db394f491a5ba319bee03f54cea5fc6871ed40 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..8924145e045ef8b2353642d97fd8560160d7a2d4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:38:55 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:38:55 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..89fbbf504ccd710d06edcc23b8cf444c4c593145 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..bf4b43d1bf94c14d4761dc92135962e52b49e488 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..244298ccdbda1f65c66165ddfc55b44f946ef2ab --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:38:55 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..d210060701e5bc086578ad0dbc412d8ef205f0da --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 02:38:56 2021" +"simulator" "spectre" +"date" "May 27 02:38:56 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..c15e258e1473ba64064e91061ef620d87ec1837c --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"inv\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 02:38:54 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..a3c025320b7c54a23e9fcf8d6a3e5685b330bb4f --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,262 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 92883 +Memory available: 1.9048 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 2201.0 37.1 + 1 0 1 2201.0 42.5 + 2 0 2 2100.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 2201.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 2201.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 2201.0 41.9 + 12 1 2 1200.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 2201.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 2201.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 2201.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 2:38:55 AM, Thur May 27, 2021 (process id: 92883). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/inv_C1/inv/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre3_6429_2 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 92883 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/inv_C1/inv/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/1_input_C1.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 69.989 ms, elapsed = 115.265 ms. +Time accumulated: CPU = 99.984 ms, elapsed = 115.271 ms. +Peak resident memory used = 36.9 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 25.995 ms, elapsed = 26.2589 ms. +Time accumulated: CPU = 125.979 ms, elapsed = 141.76 ms. +Peak resident memory used = 41.7 Mbytes. + +Time for EDB Visiting: CPU = 1 ms, elapsed = 544.071 us. +Time accumulated: CPU = 126.979 ms, elapsed = 142.492 ms. +Peak resident memory used = 42.2 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 16 + bsim3v3 2 + capacitor 1 + resistor 12 + vsource 3 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 3 ms, elapsed = 140.892 ms. +Time accumulated: CPU = 129.979 ms, elapsed = 283.549 ms. +Peak resident memory used = 43.1 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre3_6429_2, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 2 ms, elapsed = 1.14202 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 3 (current) + save 16 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.252 ns (7.51 %), step = 12.9 ps (43 m%) + +Notice from spectre at time = 2.67757 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 3.06525 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 3.66525 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 4.26525 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + + tran: time = 4.265 ns (14.2 %), step = 600 ps (2 %) + +Notice from spectre at time = 4.86525 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + Further occurrences of this notice will be suppressed. + + tran: time = 5.465 ns (18.2 %), step = 600 ps (2 %) + tran: time = 7.265 ns (24.2 %), step = 600 ps (2 %) + tran: time = 8.465 ns (28.2 %), step = 600 ps (2 %) + tran: time = 9.806 ns (32.7 %), step = 64.67 ps (216 m%) + tran: time = 11.73 ns (39.1 %), step = 600 ps (2 %) + tran: time = 12.93 ns (43.1 %), step = 600 ps (2 %) + tran: time = 14.73 ns (49.1 %), step = 600 ps (2 %) + tran: time = 15.93 ns (53.1 %), step = 600 ps (2 %) + tran: time = 17.73 ns (59.1 %), step = 600 ps (2 %) + tran: time = 18.93 ns (63.1 %), step = 600 ps (2 %) + tran: time = 20.73 ns (69.1 %), step = 600 ps (2 %) + tran: time = 21.93 ns (73.1 %), step = 600 ps (2 %) + tran: time = 23.73 ns (79.1 %), step = 600 ps (2 %) + tran: time = 24.93 ns (83.1 %), step = 600 ps (2 %) + tran: time = 26.73 ns (89.1 %), step = 600 ps (2 %) + tran: time = 27.93 ns (93.1 %), step = 600 ps (2 %) + tran: time = 29.57 ns (98.6 %), step = 434 ps (1.45 %) +Number of accepted tran steps = 108 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 2 ms, elapsed = 1.27482 ms. +Intrinsic tran analysis time: CPU = 11.998 ms, elapsed = 72.3929 ms. +Total time required for tran analysis `tran': CPU = 18.997 ms, elapsed = 79.325 ms. +Time accumulated: CPU = 151.976 ms, elapsed = 522.134 ms. +Peak resident memory used = 44.8 Mbytes. + + +Notice from spectre. + 42 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (2:41:16 AM, Thur May 27, 2021): +Time used: CPU = 218 ms, elapsed = 140 s (2m 20.5s), util. = 155e-03%. +Time spent in licensing: elapsed = 58.1 ms. +Peak memory used = 45.3 Mbytes. +Simulation started at: 2:38:55 AM, Thur May 27, 2021, ended at: 2:41:16 AM, Thur May 27, 2021, with elapsed time (wall clock): 140 s (2m 20.5s). +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..af66b5c767bcff9abe682f26efcb18d3144abee4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C1/inv/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" 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"variable" ( 27 ) PROP( ) +END diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.control b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.control similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.control rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.control diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.controlStatements b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.controlStatements similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.controlStatements rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.controlStatements diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.definitionFiles b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.definitionFiles similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.definitionFiles rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.definitionFiles diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.designVariables b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.designVariables similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.designVariables rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.designVariables diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.includedModels b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.includedModels similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.includedModels rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.includedModels diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.inv.parameters b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.inv.parameters similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.inv.parameters rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.inv.parameters diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.modelFiles b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.modelFiles similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.modelFiles rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.modelFiles diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.specialFilesInclude b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.specialFilesInclude similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.specialFilesInclude rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.specialFilesInclude diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.stimulusFile b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.stimulusFile similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/.stimulusFile rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/.stimulusFile diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__new_amap_format__ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__new_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__new_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__new_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__nmp_amap_format__ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__nmp_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__nmp_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__nmp_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__simulator_information__ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__simulator_information__ similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/__simulator_information__ rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/__simulator_information__ diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.inst b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.inst new file mode 100644 index 0000000000000000000000000000000000000000..d679704e20c70d7609ffb64a4e2644e984f39a38 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.inst @@ -0,0 +1,5 @@ +HEADER +"PSFversion" "1.00" +"re2n re3n rf1n rf2n rf3n rf4n rf5n rf6n rf7n rg1n rg2n rg3n" "analogLib_presistor_spectre" +"MP0n" "gpdk_pmos_spectre" +"MN0n" "gpdk_nmos_spectre" diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.net b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.net new file mode 100644 index 0000000000000000000000000000000000000000..01741c91f43710b7791fb7f16ba86ec10727a969 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.net @@ -0,0 +1,4 @@ +HEADER +"PSFversion" "1.00" +"gnd!v" "0v" +"vdd!v" "vdd!v" diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/inv.port b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.port similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/inv.port rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/inv.port diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/top_level_map.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/top_level_map.inst rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/top_level_map.inst diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/top_level_map.net similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/top_level_map.net rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/top_level_map.net diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/top_level_map.port similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/top_level_map.port rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/amap/top_level_map.port diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..98b309896311b15d2fafcd1d54619c9f0ef35f87 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low inv av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..20295e214758d8001df627bc917112254cd4b837 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds4/map b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds4/map rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds4/map.ext b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds4/map.ext rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..a282c44f119dcc941b9b3c06861da61dca168363 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,20 @@ + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..7e55086b6573ce758f5375dd5faecc4129cdc15c --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/inv/av_extracted inv +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..3e1fe5bae43908088586f49f7822f471b619111e --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 2:41:26 AM, Thur May 27, 2021 (process id: 110912). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre3_6429_3" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x723d5e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..d27c42dfdaa29a9600a3bf7c1359ea78dfe1c3ef --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,43 @@ +// Generated for: spectre +// Generated on: May 27 02:41:25 2021 +// Design library name: multiplier_low +// Design cell name: inv +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/1_input_C2.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..25a96f81419f509096d4df94a909602c294d1f43 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "inv" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/inv_C2/inv/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/inv/av_extracted" "inv" ) + ) +( term + ) +( param + ) +( "inv" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..a282c44f119dcc941b9b3c06861da61dca168363 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlist @@ -0,0 +1,20 @@ + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..2c2a27d1dd2ef4f2752f07960070f835536f2422 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 02:41:25 2021 +// Design library name: multiplier_low +// Design cell name: inv +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..65d67f1c6141ba6376c7526c1d782d73c82e921b --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre3_6429_3 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..d433d614cf54d9dc7d0a8b76041b7a8ebddcee7d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "inv" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..61dc6a923d9517763f917b6b7290dd387de39596 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 02:41:25 2021 +End netlisting May 27 02:41:25 2021 diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..35d5d0d3b24c7290a8314acc01914ea5ad8731a3 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,27 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:41:26 AM, Thur May 27, 2021 +# Number of equations = 17 +1\:A 9.40679277862587e-07 +1\:gnd! -1.29768437829543e-09 +1\:Out 1.80000011981106 +1\:vdd! 1.79999999247253 +2\:gnd! -2.64544218635639e-08 +2\:Out 1.80000010192003 +2\:vdd! 1.79999985861402 +3\:A 2.22978605769834e-05 +3\:Out 1.80000007998393 +4\:A 2.52944853665243e-06 +4\:Out 1.80000013896934 +5\:A 1.02241061142277e-05 +A 0 +gnd! 0 +MN0:int_d 1.799999954212 +MN0:int_s -1.08069791567679e-07 +MP0:int_d 1.80000019967178 +MP0:int_s 1.79999942555123 +Out 1.80000013899156 +v0:p -3.7025047957112e-07 +v1:p 4.46496714383229e-07 +v2:p 0 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..d21b4944594698e68743c90d51e866280138c457 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,27 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:41:26 AM, Thur May 27, 2021 +# Number of equations = 17 +1\:A 0 +1\:gnd! 5.00017528751802e-13 +1\:Out 1.79999995312089 +1\:vdd! 1.79999999999954 +2\:gnd! 1.01932911160971e-11 +2\:Out 1.79999995311492 +2\:vdd! 1.79999999999129 +3\:A 0 +3\:Out 1.79999995310943 +4\:A 0 +4\:Out 1.79999995311492 +5\:A 0 +A 0 +gnd! 0 +MN0:int_d 1.79999995307795 +MN0:int_s 4.16409344338206e-11 +MP0:int_d 1.79999995314755 +MP0:int_s 1.79999999996463 +Out 1.79999995311492 +v0:p -1.85166559088093e-11 +v1:p 0 +v2:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..755ee01c9029ee4dc889bb8e28b54090bdaf5f9d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:41:25 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..31bc9f054b658a38d532ddeb3dad894a1a09e18e --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:41:26 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..ca4e526b8f2ab611055fba3be4e5fe6b8cf78192 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..19f8d2e7e3fa9c54c2f92ea95ebba79d9af5f948 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..4abaf3b0dac2544025fc46d9eae0be0fe3d9bdd1 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:41:26 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:41:26 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..68fefb5653692e4b7934e894165ca7864af82afc Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..9f906ae49b13795c239ba18ea30311ef8c5b0565 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..f5686cd10d473f23f6f8707e07efeefa7876de6e --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:41:26 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..fd5a0bbf3c7f9b3023979db9416111ce47df652f --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 02:41:27 2021" +"simulator" "spectre" +"date" "May 27 02:41:27 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..fcd217d464af756829d561192c35eb81d3f34de5 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"inv\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 02:41:25 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..89a0e00c997116acf8beff58223d01e58225ab9c --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,264 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 110912 +Memory available: 1.8629 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 1200.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 1200.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 2201.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 1200.0 41.9 + 12 1 2 1200.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 2201.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 2201.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 2201.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 2:41:26 AM, Thur May 27, 2021 (process id: 110912). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/inv_C2/inv/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre3_6429_3 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 110912 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/inv_C2/inv/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/1_input_C2.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 81.988 ms, elapsed = 126.854 ms. +Time accumulated: CPU = 112.982 ms, elapsed = 126.858 ms. +Peak resident memory used = 36.9 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 26.995 ms, elapsed = 26.855 ms. +Time accumulated: CPU = 139.977 ms, elapsed = 153.874 ms. +Peak resident memory used = 41.7 Mbytes. + +Time for EDB Visiting: CPU = 1 ms, elapsed = 567.913 us. +Time accumulated: CPU = 140.977 ms, elapsed = 154.604 ms. +Peak resident memory used = 42.2 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 16 + bsim3v3 2 + capacitor 1 + resistor 12 + vsource 3 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 2 ms, elapsed = 211.57 ms. +Time accumulated: CPU = 142.977 ms, elapsed = 366.32 ms. +Peak resident memory used = 43.1 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre3_6429_3, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 0 s, elapsed = 458.956 us. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 3 (current) + save 16 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.267 ns (7.56 %), step = 31.72 ps (106 m%) + +Notice from spectre at time = 3.87492 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + + tran: time = 3.875 ns (12.9 %), step = 404.5 ps (1.35 %) + +Notice from spectre at time = 4.42188 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 5.02188 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 5.62188 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + + tran: time = 5.622 ns (18.7 %), step = 600 ps (2 %) + +Notice from spectre at time = 6.22188 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + Further occurrences of this notice will be suppressed. + + tran: time = 6.822 ns (22.7 %), step = 600 ps (2 %) + tran: time = 8.622 ns (28.7 %), step = 600 ps (2 %) + tran: time = 10.02 ns (33.4 %), step = 271.4 ps (905 m%) + tran: time = 11.42 ns (38.1 %), step = 243.3 ps (811 m%) + tran: time = 13.18 ns (43.9 %), step = 600 ps (2 %) + tran: time = 14.38 ns (47.9 %), step = 600 ps (2 %) + tran: time = 16.18 ns (53.9 %), step = 600 ps (2 %) + tran: time = 17.38 ns (57.9 %), step = 600 ps (2 %) + tran: time = 19.18 ns (63.9 %), step = 600 ps (2 %) + tran: time = 20.38 ns (67.9 %), step = 600 ps (2 %) + tran: time = 22.18 ns (73.9 %), step = 600 ps (2 %) + tran: time = 23.38 ns (77.9 %), step = 600 ps (2 %) + tran: time = 25.18 ns (83.9 %), step = 600 ps (2 %) + tran: time = 26.38 ns (87.9 %), step = 600 ps (2 %) + tran: time = 28.18 ns (93.9 %), step = 600 ps (2 %) + tran: time = 29.38 ns (97.9 %), step = 600 ps (2 %) +Number of accepted tran steps = 100 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 0 s, elapsed = 534.773 us. +Intrinsic tran analysis time: CPU = 13.998 ms, elapsed = 59.366 ms. +Total time required for tran analysis `tran': CPU = 15.998 ms, elapsed = 62.155 ms. +Time accumulated: CPU = 162.974 ms, elapsed = 632.336 ms. +Peak resident memory used = 44.8 Mbytes. + + +Notice from spectre. + 33 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (2:42:12 AM, Thur May 27, 2021): +Time used: CPU = 229 ms, elapsed = 45.6 s, util. = 502e-03%. +Time spent in licensing: elapsed = 60.7 ms. +Peak memory used = 45.3 Mbytes. +Simulation started at: 2:41:26 AM, Thur May 27, 2021, ended at: 2:42:12 AM, Thur May 27, 2021, with elapsed time (wall clock): 45.6 s. +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..a857d50f0c51fb1da9df1d4def6bdb7091b8a176 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:41:26 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..6e2450442ec43c2f9cb088fff831833e257a214b Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/inv_C2/inv/spectre/av_extracted/psf/tran.tran.0.sig.tmp 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a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/.control b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.control similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/.control rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.control diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.controlStatements b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.controlStatements similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.controlStatements rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.controlStatements diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.definitionFiles b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.definitionFiles similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.definitionFiles rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.definitionFiles diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.designVariables b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.designVariables similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.designVariables rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.designVariables diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.includedModels b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.includedModels similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.includedModels rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.includedModels diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.inv.parameters b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.inv.parameters similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/.inv.parameters rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.inv.parameters diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.modelFiles b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.modelFiles similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.modelFiles rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.modelFiles diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.specialFilesInclude b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.specialFilesInclude similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.specialFilesInclude rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.specialFilesInclude diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.stimulusFile b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.stimulusFile similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.stimulusFile rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/.stimulusFile diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__new_amap_format__ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__new_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__new_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__new_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__nmp_amap_format__ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__nmp_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__nmp_amap_format__ rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__nmp_amap_format__ diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__simulator_information__ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__simulator_information__ similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/__simulator_information__ rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/__simulator_information__ diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.inst b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.inst new file mode 100644 index 0000000000000000000000000000000000000000..d679704e20c70d7609ffb64a4e2644e984f39a38 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.inst @@ -0,0 +1,5 @@ +HEADER +"PSFversion" "1.00" +"re2n re3n rf1n rf2n rf3n rf4n rf5n rf6n rf7n rg1n rg2n rg3n" "analogLib_presistor_spectre" +"MP0n" "gpdk_pmos_spectre" +"MN0n" "gpdk_nmos_spectre" diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.net b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.net new file mode 100644 index 0000000000000000000000000000000000000000..01741c91f43710b7791fb7f16ba86ec10727a969 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.net @@ -0,0 +1,4 @@ +HEADER +"PSFversion" "1.00" +"gnd!v" "0v" +"vdd!v" "vdd!v" diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/inv.port b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.port similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/inv.port rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/inv.port diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/top_level_map.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/top_level_map.inst rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/top_level_map.inst diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/top_level_map.net similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/top_level_map.net rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/top_level_map.net diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/top_level_map.port similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/amap/top_level_map.port rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/amap/top_level_map.port diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..98b309896311b15d2fafcd1d54619c9f0ef35f87 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low inv av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..20295e214758d8001df627bc917112254cd4b837 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/ihnl/cds0/map b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/and2_C1/and2/spectre/extracted/netlist/ihnl/cds0/map rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds5/map.ext b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/ihnl/cds5/map.ext rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..a282c44f119dcc941b9b3c06861da61dca168363 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,20 @@ + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..7e55086b6573ce758f5375dd5faecc4129cdc15c --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/inv/av_extracted inv +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..f4a89b4e3d3e7f2870e581c4a8573028ba3a2d6f --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 2:42:24 AM, Thur May 27, 2021 (process id: 117904). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre3_6429_4" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x6fad5e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..194bdab79de38efa12f76a667fe831295df8fe85 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,43 @@ +// Generated for: spectre +// Generated on: May 27 02:42:23 2021 +// Design library name: multiplier_low +// Design cell name: inv +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/1_input_C3.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..597b75fbefd229387749d81c9d75cecedc910088 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "inv" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/inv_C3/inv/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/inv/av_extracted" "inv" ) + ) +( term + ) +( param + ) +( "inv" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..a282c44f119dcc941b9b3c06861da61dca168363 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlist @@ -0,0 +1,20 @@ + +// Library name: multiplier_low +// Cell name: inv +// View name: av_extracted +re2 (Out \4\:Out) resistor r=0.0012 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A A) resistor r=2.1068 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3226 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.2965 c=0 +rf4 (vdd! \1\:vdd!) resistor r=0.02503 c=0 +rf5 (\1\:vdd! \2\:vdd!) resistor r=0.4451 c=0 +rf6 (0 \1\:gnd!) resistor r=0.02703 c=0 +rf7 (\1\:gnd! \2\:gnd!) resistor r=0.524 c=0 +rg1 (\3\:A \4\:A) resistor r=62.7984 c=0 +rg2 (\4\:A \1\:A) resistor r=3.5583 c=0 +rg3 (\4\:A \5\:A) resistor r=58.4234 c=0 +MP0 (\1\:Out \3\:A \2\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN0 (\3\:Out \5\:A \2\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..bd22569c6d978a0de591f33800c8485819d22854 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 02:42:23 2021 +// Design library name: multiplier_low +// Design cell name: inv +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..1854ea5a1e92ed52a548a26d003b86c580a16ee0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre3_6429_4 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..d433d614cf54d9dc7d0a8b76041b7a8ebddcee7d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "inv" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..bcfc18c680f894e5dccd5d01fb973bdc9a1a2ec6 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 02:42:23 2021 +End netlisting May 27 02:42:23 2021 diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..e78a8ebc26df67ad76b3bcb0c7143943f09a2b67 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,27 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:42:24 AM, Thur May 27, 2021 +# Number of equations = 17 +1\:A 4.14997113951355e-07 +1\:gnd! -2.63530438243841e-10 +1\:Out 1.7983563340666 +1\:vdd! 1.79999998065575 +2\:gnd! -5.37229661063647e-09 +2\:Out 1.7983561484743 +2\:vdd! 1.79999963666349 +3\:A 1.39474856029678e-05 +3\:Out 1.79835614488542 +4\:A 1.11591045673335e-06 +4\:Out 1.79835502207936 +5\:A 6.86509157834293e-07 +A 0 +gnd! 0 +MN0:int_d 1.79835612430836 +MN0:int_s -2.19465380096202e-08 +MP0:int_d 1.79835716250093 +MP0:int_s 1.7999985237701 +Out 1.79835502140352 +v0:p -7.79631267488198e-07 +v1:p 1.96979833848185e-07 +v2:p 0 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..8eeb3c1d69419bbad67ff4ee63969e1b31c0a529 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,27 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 2:42:24 AM, Thur May 27, 2021 +# Number of equations = 17 +1\:A 0 +1\:gnd! 5.00017528751802e-13 +1\:Out 1.79999995312089 +1\:vdd! 1.79999999999954 +2\:gnd! 1.01932911160971e-11 +2\:Out 1.79999995311492 +2\:vdd! 1.79999999999129 +3\:A 0 +3\:Out 1.79999995310943 +4\:A 0 +4\:Out 1.79999995311492 +5\:A 0 +A 0 +gnd! 0 +MN0:int_d 1.79999995307795 +MN0:int_s 4.16409344338206e-11 +MP0:int_d 1.79999995314755 +MP0:int_s 1.79999999996463 +Out 1.79999995311492 +v0:p -1.85166559088093e-11 +v1:p 0 +v2:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..c11351a100aba640ed89445585142269540ce6a4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:42:22 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..41eebfb726a5f5b6f02535ad11b7108c6c2ecc99 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:42:24 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..2962da74a1a1f77e42ddc8a79b2b22c4fa1a89d1 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..5e8728756f23181c3ea29ca655cfdf10c2b3ce2b Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..dff25378d9934f072e5db2d7af6d8d5c0fa67637 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 02:42:24 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:42:24 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..e915152d7ea04c56798470336ab381477a2f7bef Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..4f1da2a5e502fe2d03deea5b9b0f4932376339c9 Binary files /dev/null and b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..e49b1f2c9d3fbb7caf0c4fe89ee6cb616fdf9a55 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "2:42:24 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..4248bfe46a94aa998bdb1455a8d467347cdc7e63 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 02:42:24 2021" +"simulator" "spectre" +"date" "May 27 02:42:24 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..06bfa62350756c78b12152dea7919c5a4ebae073 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"inv\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 02:42:22 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..00d9eee23d01cca9cd0602b33602ed1c33927904 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,262 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 117904 +Memory available: 1.8518 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 2201.0 37.1 + 1 0 1 2201.0 42.5 + 2 0 2 2201.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 2201.0 41.9 + 12 1 2 2201.0 29.6 + 13 1 3 2201.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 2201.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 2201.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 2201.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 2:42:24 AM, Thur May 27, 2021 (process id: 117904). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/inv_C3/inv/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre3_6429_4 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 117904 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/inv_C3/inv/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/1_input_C3.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 69.989 ms, elapsed = 113.955 ms. +Time accumulated: CPU = 97.984 ms, elapsed = 113.962 ms. +Peak resident memory used = 36.9 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 31.995 ms, elapsed = 32.0909 ms. +Time accumulated: CPU = 130.979 ms, elapsed = 146.347 ms. +Peak resident memory used = 41.7 Mbytes. + +Time for EDB Visiting: CPU = 1 ms, elapsed = 633.001 us. +Time accumulated: CPU = 131.979 ms, elapsed = 147.163 ms. +Peak resident memory used = 42.2 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 16 + bsim3v3 2 + capacitor 1 + resistor 12 + vsource 3 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 1.999 ms, elapsed = 83.38 ms. +Time accumulated: CPU = 133.978 ms, elapsed = 230.71 ms. +Peak resident memory used = 43.1 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre3_6429_4, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 1 ms, elapsed = 855.207 us. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 3 (current) + save 16 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.265 ns (7.55 %), step = 30.42 ps (101 m%) + +Notice from spectre at time = 2.68212 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 3.0845 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 3.6845 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. +Notice from spectre at time = 4.2845 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + + tran: time = 4.285 ns (14.3 %), step = 600 ps (2 %) + tran: time = 5.485 ns (18.3 %), step = 600 ps (2 %) + tran: time = 7.237 ns (24.1 %), step = 600 ps (2 %) + tran: time = 8.424 ns (28.1 %), step = 600 ps (2 %) + +Notice from spectre at time = 9.2 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + Further occurrences of this notice will be suppressed. + + tran: time = 9.907 ns (33 %), step = 249.8 ps (833 m%) + tran: time = 11.61 ns (38.7 %), step = 600 ps (2 %) + tran: time = 12.81 ns (42.7 %), step = 600 ps (2 %) + tran: time = 14.61 ns (48.7 %), step = 600 ps (2 %) + tran: time = 15.81 ns (52.7 %), step = 600 ps (2 %) + tran: time = 17.61 ns (58.7 %), step = 600 ps (2 %) + tran: time = 18.81 ns (62.7 %), step = 600 ps (2 %) + tran: time = 20.61 ns (68.7 %), step = 600 ps (2 %) + tran: time = 21.81 ns (72.7 %), step = 600 ps (2 %) + tran: time = 23.61 ns (78.7 %), step = 600 ps (2 %) + tran: time = 24.81 ns (82.7 %), step = 600 ps (2 %) + tran: time = 26.61 ns (88.7 %), step = 600 ps (2 %) + tran: time = 27.81 ns (92.7 %), step = 600 ps (2 %) + tran: time = 29.5 ns (98.3 %), step = 496.4 ps (1.65 %) +Number of accepted tran steps = 86 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1 ms, elapsed = 957.012 us. +Intrinsic tran analysis time: CPU = 12.999 ms, elapsed = 149.975 ms. +Total time required for tran analysis `tran': CPU = 17.998 ms, elapsed = 155.01 ms. +Time accumulated: CPU = 155.975 ms, elapsed = 655.75 ms. +Peak resident memory used = 44.8 Mbytes. + + +Notice from spectre. + 7 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (2:43:16 AM, Thur May 27, 2021): +Time used: CPU = 235 ms, elapsed = 51.9 s, util. = 453e-03%. +Time spent in licensing: elapsed = 56.4 ms. +Peak memory used = 45.3 Mbytes. +Simulation started at: 2:42:24 AM, Thur May 27, 2021, ended at: 2:43:16 AM, Thur May 27, 2021, with elapsed time (wall clock): 51.9 s. +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..c41412ad4553f4666758474b03ceeabd51c19fc6 --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" 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Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/psf/tran.tran.sig.tmp rename to involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/tran.tran.sig.tmp diff --git a/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/variables_file b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/variables_file new file mode 100644 index 0000000000000000000000000000000000000000..eafe2010ceab789ea0cf45eefd7706421816617d --- /dev/null +++ b/involution/Design/simulation/ADE_output/inv_C3/inv/spectre/av_extracted/psf/variables_file @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"Time Stamp" "May 27 02:42:23 2021" +TYPE +"variable" STRUCT( +"value" FLOAT DOUBLE +) PROP( "key" "element" ) +VALUE +"temp" "variable" ( 27 ) PROP( ) +END diff --git a/Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.control b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.control similarity index 100% rename from Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.control rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.control diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/.controlStatements b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.controlStatements similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/.controlStatements rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.controlStatements diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/.definitionFiles b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.definitionFiles similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/.definitionFiles rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.definitionFiles diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.designVariables b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.designVariables similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.designVariables rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.designVariables diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.includedModels b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.includedModels similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.includedModels rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.includedModels diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.modelFiles b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.modelFiles similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.modelFiles rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.modelFiles diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.nand2.parameters b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.nand2.parameters similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.nand2.parameters rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.nand2.parameters diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.specialFilesInclude b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.specialFilesInclude similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.specialFilesInclude rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.specialFilesInclude diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.stimulusFile b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.stimulusFile similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/.stimulusFile rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/.stimulusFile diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__new_amap_format__ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__new_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__new_amap_format__ rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__new_amap_format__ diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__nmp_amap_format__ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__nmp_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__nmp_amap_format__ rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__nmp_amap_format__ diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__simulator_information__ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__simulator_information__ similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/__simulator_information__ rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/__simulator_information__ diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.inst b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.inst new file mode 100644 index 0000000000000000000000000000000000000000..5532122d949f69db914ba421a1ed94a64a2570cc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.inst @@ -0,0 +1,5 @@ +HEADER +"PSFversion" "1.00" +"re1n re2n re3n rf1n rf2n rf3n rf4n rf5n rf6n rf7n rf8n rg1n rg2n rg3n rg4n rg5n rg6n" "analogLib_presistor_spectre" +"MP1n MP0n" "gpdk_pmos_spectre" +"MN1n MN0n" "gpdk_nmos_spectre" diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.net b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.net new file mode 100644 index 0000000000000000000000000000000000000000..01741c91f43710b7791fb7f16ba86ec10727a969 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.net @@ -0,0 +1,4 @@ +HEADER +"PSFversion" "1.00" +"gnd!v" "0v" +"vdd!v" "vdd!v" diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/nand2.port b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.port similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/nand2.port rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/nand2.port diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/top_level_map.inst similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/top_level_map.inst rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/top_level_map.inst diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/top_level_map.net similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/top_level_map.net rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/top_level_map.net diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/top_level_map.port similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/amap/top_level_map.port rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/amap/top_level_map.port diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..2bc1a4660b990098171e07b06fe420ef25f5bfca --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low nand2 av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..3f5080cfd0cff7aab75332668368cad259fd0a29 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/ihnl/cds0/map b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/and2_C2/and2/spectre/extracted/netlist/ihnl/cds0/map rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/ihnl/cds0/map.ext b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/ihnl/cds0/map.ext rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..af4009c0810e0d5ec742dce287a41e9562a9669c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,29 @@ + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..b0ad8abc6489e972c695f8f162dc8fb07b080fdc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/nand2/av_extracted nand2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..843d528f5eecd47588ea97cb6a2a4f62b5ccb133 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 3:15:13 AM, Thur May 27, 2021 (process id: 165058). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre7_6429_9" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x728f5e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..24d026c9a5487ee2beb90e676b98f4b47792b52d --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,52 @@ +// Generated for: spectre +// Generated on: May 27 03:15:12 2021 +// Design library name: multiplier_low +// Design cell name: nand2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_NAND_C1.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..a93437383fc03538ab5972513ed6c61b9997c900 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "nand2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C1/nand2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/nand2/av_extracted" "nand2" ) + ) +( term + ) +( param + ) +( "nand2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..af4009c0810e0d5ec742dce287a41e9562a9669c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,29 @@ + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..37566a6fca79de042a08b5bbdb444a61924ef0a2 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 03:15:12 2021 +// Design library name: multiplier_low +// Design cell name: nand2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..95b143970bf51d1debfd3f64ccdb28045205bdf8 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre7_6429_9 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..23aba9427fdb21ab5e0980598a082c220c00fb5f --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "nand2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..ee96850e6ef62ab5f59d5151edeaf64080b7c399 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 03:15:12 2021 +End netlisting May 27 03:15:12 2021 diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..7aeece065bc447235d31b23713a961ad59359ba7 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,39 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:15:13 AM, Thur May 27, 2021 +# Number of equations = 24 +1\:A 1.79999999950534 +1\:B 1.80000000003002 +1\:gnd! 3.62154031162755e-13 +1\:Out 1.10315668238146e-08 +1\:vdd! 1.79999999999714 +2\:A 1.79999999999974 +2\:B 1.80000000008378 +2\:Out 1.10265336956851e-08 +2\:vdd! 1.80000000000042 +3\:A 1.79999999569335 +3\:B 1.80000000052798 +3\:Out 1.10661479199249e-08 +3\:vdd! 1.80000000000401 +4\:A 1.79999999862004 +4\:B 1.80000000055544 +4\:Out 1.08542904468776e-08 +5\:A 1.79999998533306 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 5.90207499018642e-09 +MN0:int_s 1.11904909428343e-08 +MN1:int_d 1.77325156262432e-12 +MN1:int_s 5.66813959960672e-09 +MP0:int_d 1.10508349697499e-08 +MP0:int_s 1.80000000001556 +MP1:int_d 1.79999999998852 +MP1:int_s 1.10309879623209e-08 +net9 5.78510729489657e-09 +Out 1.08541947657529e-08 +v0:p 2.21010854453215e-11 +v1:p -2.35436534709036e-10 +v2:p 0 +v3:p 1.42960201601725e-11 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..e1608278f60826e91be0fcc2ed5fb445d8efaa28 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,39 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:15:13 AM, Thur May 27, 2021 +# Number of equations = 24 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 4.0541356355123e-12 +1\:Out 1.1781384560353e-08 +1\:vdd! 1.79999999999778 +2\:A 1.8 +2\:B 1.8 +2\:Out 1.17777810906863e-08 +2\:vdd! 1.79999999999976 +3\:A 1.8 +3\:B 1.8 +3\:Out 1.17727484987019e-08 +3\:vdd! 1.79999999999768 +4\:A 1.8 +4\:B 1.8 +4\:Out 1.17777810906863e-08 +5\:A 1.8 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 5.9036643785842e-09 +MN0:int_s 1.17569519581313e-08 +MN1:int_d 1.98506760443386e-11 +MN1:int_s 5.87207129768563e-09 +MP0:int_d 1.17880748598881e-08 +MP0:int_s 1.799999999991 +MP1:int_d 1.7999999999911 +MP1:int_s 1.17880748598881e-08 +net9 5.88786783813492e-09 +Out 1.17777810906863e-08 +v0:p -9.29208268778866e-12 +v1:p 0 +v2:p 0 +v3:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/inv_C1/inv/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..74c6162d961ceb8dc854c7f30236eadb849c0b2a --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:15:12 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..c761b1c90af03bca0bb2a864e54838f11afa19c8 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..daa5c19e31c780899445ecc10ea934501ed178b8 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..a145a48c0d52654d15da6fe821c7d3ae86c684c8 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..b0569f8a2ebd81357f9d10166e720dab3828c559 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:15:13 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..fd0bb826c252c91bd3ad625b54cb93cc2cf6a9b3 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..100bc2c82bf8f3a43077c0de599cc0085be8e5cd Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..b8fd42fb5a5ee898a996c3319fbc64f140569023 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..4c02a0bfbf963d3cf45ade8e359cebe6cd0863e1 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 03:15:14 2021" +"simulator" "spectre" +"date" "May 27 03:15:14 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..73ba9621fc70f4283d0a4511381640b501464893 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"nand2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 03:15:12 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..e8fb966f9aa90aae6608dca2c3541adf8b43c849 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,264 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 165058 +Memory available: 1.5131 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 2201.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 2201.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 2201.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 2201.0 35.1 + 11 1 1 1200.0 41.9 + 12 1 2 2201.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 2201.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 3:15:13 AM, Thur May 27, 2021 (process id: 165058). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C1/nand2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre7_6429_9 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 165058 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C1/nand2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_NAND_C1.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 61.991 ms, elapsed = 108.84 ms. +Time accumulated: CPU = 92.985 ms, elapsed = 108.845 ms. +Peak resident memory used = 38.8 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 26.996 ms, elapsed = 26.4421 ms. +Time accumulated: CPU = 119.981 ms, elapsed = 135.473 ms. +Peak resident memory used = 43.6 Mbytes. + +Time for EDB Visiting: CPU = 1 ms, elapsed = 665.903 us. +Time accumulated: CPU = 120.981 ms, elapsed = 136.326 ms. +Peak resident memory used = 44.1 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 23 + bsim3v3 4 + capacitor 1 + resistor 17 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 2.999 ms, elapsed = 141.923 ms. +Time accumulated: CPU = 123.98 ms, elapsed = 278.416 ms. +Peak resident memory used = 45 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre7_6429_9, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 0 s, elapsed = 1.06812 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 23 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.261 ns (7.54 %), step = 27.94 ps (93.1 m%) + +Notice from spectre at time = 3.62594 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. +Notice from spectre at time = 3.92594 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. + + tran: time = 3.926 ns (13.1 %), step = 300 ps (1 %) + +Notice from spectre at time = 4.06297 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. +Notice from spectre at time = 4.2 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. + + tran: time = 5.497 ns (18.3 %), step = 411.3 ps (1.37 %) + tran: time = 7 ns (23.3 %), step = 600 ps (2 %) + tran: time = 8.8 ns (29.3 %), step = 600 ps (2 %) + tran: time = 10 ns (33.3 %), step = 600 ps (2 %) + +Notice from spectre at time = 11.2 ns during transient analysis `tran'. + Found trapezoidal ringing on node v1:p. + Further occurrences of this notice will be suppressed. + + tran: time = 11.8 ns (39.3 %), step = 600 ps (2 %) + tran: time = 13 ns (43.3 %), step = 600 ps (2 %) + tran: time = 14.8 ns (49.3 %), step = 600 ps (2 %) + tran: time = 16 ns (53.3 %), step = 600 ps (2 %) + tran: time = 17.8 ns (59.3 %), step = 600 ps (2 %) + tran: time = 19 ns (63.3 %), step = 600 ps (2 %) + tran: time = 20.8 ns (69.3 %), step = 600 ps (2 %) + tran: time = 22 ns (73.3 %), step = 600 ps (2 %) + tran: time = 23.8 ns (79.3 %), step = 600 ps (2 %) + tran: time = 25 ns (83.3 %), step = 600 ps (2 %) + tran: time = 26.8 ns (89.3 %), step = 600 ps (2 %) + tran: time = 28 ns (93.3 %), step = 600 ps (2 %) + tran: time = 29.6 ns (98.7 %), step = 400 ps (1.33 %) +Number of accepted tran steps = 114 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1 ms, elapsed = 1.18804 ms. +Intrinsic tran analysis time: CPU = 12.998 ms, elapsed = 99.8399 ms. +Total time required for tran analysis `tran': CPU = 17.998 ms, elapsed = 105.693 ms. +Time accumulated: CPU = 145.977 ms, elapsed = 944.307 ms. +Peak resident memory used = 46.8 Mbytes. + + +Notice from spectre. + 32 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (3:15:31 AM, Thur May 27, 2021): +Time used: CPU = 217 ms, elapsed = 17.8 s, util. = 1.22%. +Time spent in licensing: elapsed = 58.1 ms. +Peak memory used = 47.2 Mbytes. +Simulation started at: 3:15:13 AM, Thur May 27, 2021, ended at: 3:15:31 AM, Thur May 27, 2021, with elapsed time (wall clock): 17.8 s. +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..38da8b9ea8890f7cbb19d9b15d9bac4c9fb54717 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:13 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..eb7729e05806c0eb6014da7727b0770923a65cb3 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/nand2_C1/nand2/spectre/av_extracted/psf/tran.tran.0.sig.tmp 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rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.designVariables rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.designVariables diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.includedModels b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.includedModels similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.includedModels rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.includedModels diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.modelFiles b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.modelFiles similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.modelFiles rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.modelFiles diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/.nand2.parameters b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.nand2.parameters similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/.nand2.parameters rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.nand2.parameters diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.specialFilesInclude b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.specialFilesInclude similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.specialFilesInclude rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.specialFilesInclude diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.stimulusFile b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.stimulusFile similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/.stimulusFile rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/.stimulusFile diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__multiplefiles_amap_format__ rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__multiplefiles_amap_format__ diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__new_amap_format__ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__new_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__new_amap_format__ rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__new_amap_format__ diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__nmp_amap_format__ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__nmp_amap_format__ similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__nmp_amap_format__ rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__nmp_amap_format__ diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__simulator_information__ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__simulator_information__ similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/__simulator_information__ rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/__simulator_information__ diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/amap/gpdk_pcapacitor_spectre.inst rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/analogLib_presistor_spectre.inst diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/gpdk_nmos_spectre.inst rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/gpdk_nmos_spectre.inst diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/amap/gpdk_pmos_spectre.inst rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/gpdk_pmos_spectre.inst diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.inst b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.inst new file mode 100644 index 0000000000000000000000000000000000000000..5532122d949f69db914ba421a1ed94a64a2570cc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.inst @@ -0,0 +1,5 @@ +HEADER +"PSFversion" "1.00" +"re1n re2n re3n rf1n rf2n rf3n rf4n rf5n rf6n rf7n rf8n rg1n rg2n rg3n rg4n rg5n rg6n" "analogLib_presistor_spectre" +"MP1n MP0n" "gpdk_pmos_spectre" +"MN1n MN0n" "gpdk_nmos_spectre" diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.net b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.net new file mode 100644 index 0000000000000000000000000000000000000000..01741c91f43710b7791fb7f16ba86ec10727a969 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.net @@ -0,0 +1,4 @@ +HEADER +"PSFversion" "1.00" +"gnd!v" "0v" +"vdd!v" "vdd!v" diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/nand2.port b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.port similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/nand2.port rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/nand2.port diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/top_level_map.inst b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/top_level_map.inst similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/top_level_map.inst rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/top_level_map.inst diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/top_level_map.net b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/top_level_map.net similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/top_level_map.net rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/top_level_map.net diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/top_level_map.port b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/top_level_map.port similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/amap/top_level_map.port rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/amap/top_level_map.port diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/artSimEnvLog diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/control b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/control similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/control rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/control diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/emir.conf b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/emir.conf similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/emir.conf rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/emir.conf diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/blockdirmap b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/blockdirmap new file mode 100644 index 0000000000000000000000000000000000000000..2bc1a4660b990098171e07b06fe420ef25f5bfca --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/blockdirmap @@ -0,0 +1,3 @@ +CADENCE IHNL01071 + +multiplier_low nand2 av_extracted cds0 \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/control b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/control new file mode 100644 index 0000000000000000000000000000000000000000..3f5080cfd0cff7aab75332668368cad259fd0a29 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/control differ diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/ihnl/cds0/map b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/map similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/ihnl/cds0/map rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/map diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/ihnl/cds0/map.ext b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/map.ext similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/ihnl/cds0/map.ext rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/map.ext diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/netlist b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/netlist new file mode 100644 index 0000000000000000000000000000000000000000..af4009c0810e0d5ec742dce287a41e9562a9669c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/cds0/netlist @@ -0,0 +1,29 @@ + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/control b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/control new file mode 100644 index 0000000000000000000000000000000000000000..0debd8b4626dff80ca16b8c0669267e6b2b6c43d --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/control @@ -0,0 +1,786 @@ +hnlLastStopCellInfo = '( + ( "analogLib" "presistor" "spectre" "27" "1414734901" ) + ( "gpdk" "pmos" "spectre" "49" "1610355397" ) + ( "gpdk" "nmos" "spectre" "49" "1610355397" ) + ) +hnlLastMaxNameLength = 1024 +hnlLastNamePrefix = "hnl_" +hnlLastNetNamePrefix = "_net" +hnlLastInstNamePrefix = "_inst" +hnlLastParamNamePrefix = "_par" +hnlLastGlobalNetPrefix = "_gnet" +hnlLastModulePrefix = "_sub" +hnlLastHierarchyDelimiter = "." +hnlLastMapNetFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..b0ad8abc6489e972c695f8f162dc8fb07b080fdc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/nand2/av_extracted nand2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..57a162382b8e16575d8b124d75fa611dede3623f --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 3:15:47 AM, Thur May 27, 2021 (process id: 169079). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre7_6429_10" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x77be5e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..163aa5eff58171857153c064237069270ae6ebd5 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,52 @@ +// Generated for: spectre +// Generated on: May 27 03:15:46 2021 +// Design library name: multiplier_low +// Design cell name: nand2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_NAND_C2.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..d1c38552d2bf89e42f68a97b7210bc703fc8201c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "nand2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C2/nand2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/nand2/av_extracted" "nand2" ) + ) +( term + ) +( param + ) +( "nand2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..af4009c0810e0d5ec742dce287a41e9562a9669c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,29 @@ + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..32de17448ecf3b57580927080a1b743b422f4fde --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 03:15:46 2021 +// Design library name: multiplier_low +// Design cell name: nand2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..6acaeb68b49f80bb33b606fe9ef9c22f242206b1 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre7_6429_10 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..23aba9427fdb21ab5e0980598a082c220c00fb5f --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "nand2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..c943fe0f59a48275db78bb02cf533934e6a1addc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 03:15:46 2021 +End netlisting May 27 03:15:46 2021 diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..1c6428e3a0b81c1bce4cbf6eb12c4c1da518a4a8 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,39 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:15:47 AM, Thur May 27, 2021 +# Number of equations = 24 +1\:A 1.7999999989938 +1\:B 1.79999999959379 +1\:gnd! 4.8363041411968e-10 +1\:Out 8.47019362020975e-09 +1\:vdd! 1.79999999999764 +2\:A 1.79999999999947 +2\:B 1.79999999886641 +2\:Out 8.45664377435979e-09 +2\:vdd! 1.80000000000112 +3\:A 1.79999999112607 +3\:B 1.79999998948667 +3\:Out 8.75387799619647e-09 +3\:vdd! 1.80000000001071 +4\:A 1.799999997193 +4\:B 1.7999999989522 +4\:Out 7.28914789238381e-09 +5\:A 1.79999997027179 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 1.69488199117615e-07 +MN0:int_s 9.68685099679166e-09 +MN1:int_d 2.36804871346292e-09 +MN1:int_s 1.68185808387073e-07 +MP0:int_d 8.51387430849771e-09 +MP0:int_s 1.80000000004159 +MP1:int_d 1.79999999999053 +MP1:int_s 8.47682695467565e-09 +net9 1.68837003752344e-07 +Out 7.28849934842137e-09 +v0:p 4.7430959921754e-11 +v1:p -4.78897080141155e-10 +v2:p 0 +v3:p -1.93432689767003e-10 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..40ee10980f68dd20907efcf7774a0afeada84b56 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,39 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:15:47 AM, Thur May 27, 2021 +# Number of equations = 24 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 4.0541356355123e-12 +1\:Out 1.1781384560353e-08 +1\:vdd! 1.79999999999778 +2\:A 1.8 +2\:B 1.8 +2\:Out 1.17777810906863e-08 +2\:vdd! 1.79999999999976 +3\:A 1.8 +3\:B 1.8 +3\:Out 1.17727484987019e-08 +3\:vdd! 1.79999999999768 +4\:A 1.8 +4\:B 1.8 +4\:Out 1.17777810906863e-08 +5\:A 1.8 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 5.9036643785842e-09 +MN0:int_s 1.17569519581313e-08 +MN1:int_d 1.98506760443386e-11 +MN1:int_s 5.87207129768563e-09 +MP0:int_d 1.17880748598881e-08 +MP0:int_s 1.799999999991 +MP1:int_d 1.7999999999911 +MP1:int_s 1.17880748598881e-08 +net9 5.88786783813492e-09 +Out 1.17777810906863e-08 +v0:p -9.29208268778866e-12 +v1:p 0 +v2:p 0 +v3:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..41d138d961f33f0a240743c2cd4c7c85142bfcb7 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:15:46 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..fd44c3c92c0435d7dd588dd9d7db429a3f0123b5 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:47 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..ef67b4fb0116b56cb65a1e0bbecfb1374af8de07 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..ae4a19d8ae396420d33682ff2dec74dd07df7e2c Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..6ddd1f87a12d34aee4c792a80b51c45d8fc30093 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:15:47 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:47 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..1fba98243c0f8c6d1cdb223ada7b1665312b8754 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..736e514991a53e49eac8f0b28a0ba3653fe56f2e Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..9eac283f0463047e661267b282178f05cd885900 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:47 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..878b913ceec261c17268f23e98f81029477ab224 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 03:15:47 2021" +"simulator" "spectre" +"date" "May 27 03:15:47 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..13aea1fcc7a9939d206aee05fd01fa8c1709d672 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"nand2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 03:15:46 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..78a0d8cf46389a5472abb78e4e16285ce457056c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,266 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 169079 +Memory available: 1.5139 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 2201.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 2201.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 2201.0 7.4 + 7 0 10 2201.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 2201.0 41.9 + 12 1 2 2201.0 29.6 + 13 1 3 2201.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 2201.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 2201.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 3:15:47 AM, Thur May 27, 2021 (process id: 169079). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C2/nand2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre7_6429_10 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 169079 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C2/nand2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_NAND_C2.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 68.989 ms, elapsed = 114.948 ms. +Time accumulated: CPU = 91.985 ms, elapsed = 114.953 ms. +Peak resident memory used = 36.9 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 25.996 ms, elapsed = 25.964 ms. +Time accumulated: CPU = 117.981 ms, elapsed = 141.101 ms. +Peak resident memory used = 41.7 Mbytes. + +Time for EDB Visiting: CPU = 0 s, elapsed = 635.147 us. +Time accumulated: CPU = 118.981 ms, elapsed = 141.922 ms. +Peak resident memory used = 42.2 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 23 + bsim3v3 4 + capacitor 1 + resistor 17 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 3 ms, elapsed = 165.09 ms. +Time accumulated: CPU = 121.981 ms, elapsed = 307.172 ms. +Peak resident memory used = 43.1 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre7_6429_10, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 1 ms, elapsed = 1.08194 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 23 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.266 ns (7.55 %), step = 31.21 ps (104 m%) + +Notice from spectre at time = 2.43342 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:A. + + tran: time = 3.766 ns (12.6 %), step = 234.2 ps (781 m%) + tran: time = 5.285 ns (17.6 %), step = 122.4 ps (408 m%) + tran: time = 6.895 ns (23 %), step = 495 ps (1.65 %) + tran: time = 8.695 ns (29 %), step = 600 ps (2 %) + tran: time = 9.895 ns (33 %), step = 600 ps (2 %) + +Notice from spectre at time = 11.695 ns during transient analysis `tran'. + Found trapezoidal ringing on node MN0:int_d. + + tran: time = 11.69 ns (39 %), step = 600 ps (2 %) + +Notice from spectre at time = 12.295 ns during transient analysis `tran'. + Found trapezoidal ringing on node MN0:int_d. +Notice from spectre at time = 12.895 ns during transient analysis `tran'. + Found trapezoidal ringing on node MN0:int_d. + + tran: time = 12.89 ns (43 %), step = 600 ps (2 %) + +Notice from spectre at time = 13.495 ns during transient analysis `tran'. + Found trapezoidal ringing on node MN0:int_d. + Further occurrences of this notice will be suppressed. + + tran: time = 14.69 ns (49 %), step = 600 ps (2 %) + tran: time = 15.89 ns (53 %), step = 600 ps (2 %) + tran: time = 17.69 ns (59 %), step = 600 ps (2 %) + tran: time = 18.89 ns (63 %), step = 600 ps (2 %) + tran: time = 20.69 ns (69 %), step = 600 ps (2 %) + tran: time = 21.89 ns (73 %), step = 600 ps (2 %) + tran: time = 23.69 ns (79 %), step = 600 ps (2 %) + tran: time = 24.89 ns (83 %), step = 600 ps (2 %) + tran: time = 26.69 ns (89 %), step = 600 ps (2 %) + tran: time = 27.89 ns (93 %), step = 600 ps (2 %) + tran: time = 29.55 ns (98.5 %), step = 452.5 ps (1.51 %) +Number of accepted tran steps = 108 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1 ms, elapsed = 1.23 ms. +Intrinsic tran analysis time: CPU = 16.997 ms, elapsed = 67.415 ms. +Total time required for tran analysis `tran': CPU = 21.996 ms, elapsed = 72.8211 ms. +Time accumulated: CPU = 149.976 ms, elapsed = 535.336 ms. +Peak resident memory used = 45 Mbytes. + + +Notice from spectre. + 28 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (3:16:02 AM, Thur May 27, 2021): +Time used: CPU = 215 ms, elapsed = 15.2 s, util. = 1.41%. +Time spent in licensing: elapsed = 60.5 ms. +Peak memory used = 45.5 Mbytes. +Simulation started at: 3:15:47 AM, Thur May 27, 2021, ended at: 3:16:02 AM, Thur May 27, 2021, with elapsed time (wall clock): 15.2 s. +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..5d0ff6b38c3c291deeab6dd93333edec733aeccf --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:15:47 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..00e1e3e73d319880d9b8531f119695be939ae337 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran.0.sig.tmp b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran.0.sig.tmp new file mode 100644 index 0000000000000000000000000000000000000000..f0445ff899fc9279a7e15a31ac33af4ddf58f5cc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran.0.sig.tmp @@ -0,0 +1,71 @@ +*cdnsheobpacket 26 1 +*cdnshlastgoodpoint 26 0,0 +*cdnshnumflushes 26 0 +*cdnshnxdbpid 26 169079 +*cdnshrunkey 26 -1 +*cdnshserieskey 26 -1 +*cdnshsweepcount 26 0 +*cdnshsweepprecision 26 -1 +*cdnshsweeprange 26 0,0 +*cdnshsweepstoptime 26 -1 +*cdnshtimestamp 26 8708489921622056547 +*cdnshuuid 26 11276135155157119594142178189199127152236246-3870700278-31622056547-3-862636253-7-367536670536657513 +:pwr 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 0 W 0 +A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 18 V 0 +B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 19 V 0 +Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 22 V 0 +\1\:A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1 V 0 +\1\:B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2 V 0 +\1\:Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 4 V 0 +\1\:gnd! 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0 1 592 0 2.9999999999999997319e-08 1.8000000000000000444 1.8000000000000000444 109 27 V 0 +­­¨ª|1|­­¨ª 0 0 0 25960 0 RootScope 28 28 0 0 0 0 0 0 <> +­­¨ª|141018080|­­¨ª 0 0 0 25960 0 RootScope 28 28 0 0 0 0 0 0 <> diff --git a/Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/psf/tran.tran.sig.tmp b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran.sig.tmp similarity index 100% rename from Design/simulation/ADE_output/inv_C2/inv/spectre/extracted/psf/tran.tran.sig.tmp rename to involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/tran.tran.sig.tmp diff --git a/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/variables_file b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/variables_file new file mode 100644 index 0000000000000000000000000000000000000000..2d09f42a534ba442fe5deb2bcd9aec1545054aba --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C2/nand2/spectre/av_extracted/psf/variables_file @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"Time Stamp" "May 27 03:15:46 2021" +TYPE +"variable" STRUCT( +"value" FLOAT DOUBLE +) PROP( "key" "element" ) +VALUE +"temp" "variable" ( 27 ) PROP( ) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/.control b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/.control new file mode 100755 index 0000000000000000000000000000000000000000..1beb90f7f38f765096259ec214ede2192c8d975e --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/.control @@ -0,0 +1,4 @@ + #!/bin/sh +xargs cat > netlist <" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..b0ad8abc6489e972c695f8f162dc8fb07b080fdc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/nand2/av_extracted nand2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..1b280509c2fc26af074f82f226f43a35f0ea2d54 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 3:18:53 AM, Thur May 27, 2021 (process id: 190549). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre7_6429_12" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x79825e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..564fec43c57b96c56f7d98de2f84966fce139abc --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,52 @@ +// Generated for: spectre +// Generated on: May 27 03:18:50 2021 +// Design library name: multiplier_low +// Design cell name: nand2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_NAND_C3.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..5b53b8f700084a4b8264addc3dbedf670de59699 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "nand2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C3/nand2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/nand2/av_extracted" "nand2" ) + ) +( term + ) +( param + ) +( "nand2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..af4009c0810e0d5ec742dce287a41e9562a9669c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,29 @@ + +// Library name: multiplier_low +// Cell name: nand2 +// View name: av_extracted +re1 (A \2\:A) resistor r=0.001111 c=0 +re2 (Out \4\:Out) resistor r=0.001111 c=0 +re3 (\2\:Out \4\:Out) resistor r=2 c=0 +rf1 (\1\:A \2\:A) resistor r=2.1 c=0 +rf2 (\1\:Out \2\:Out) resistor r=0.3878 c=0 +rf3 (\2\:Out \3\:Out) resistor r=0.5416 c=0 +rf4 (\1\:B B) resistor r=2.1 c=0 +rf5 (\1\:vdd! vdd!) resistor r=0.479 c=0 +rf6 (vdd! \2\:vdd!) resistor r=0.05202 c=0 +rf7 (\2\:vdd! \3\:vdd!) resistor r=0.4475 c=0 +rf8 (\1\:gnd! 0) resistor r=0.4363 c=0 +rg1 (\3\:A \4\:A) resistor r=72.8433 c=0 +rg2 (\4\:A \1\:A) resistor r=3.7604 c=0 +rg3 (\4\:A \5\:A) resistor r=68.0516 c=0 +rg4 (\1\:B \2\:B) resistor r=3.7604 c=0 +rg5 (\2\:B \3\:B) resistor r=48.2599 c=0 +rg6 (\2\:B \4\:B) resistor r=92.6349 c=0 +MP1 (\1\:vdd! \4\:B \1\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP0 (\1\:Out \3\:A \3\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\1\:gnd! \3\:B net9 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net9 \5\:A \3\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..16c7300f951a99a0e2eb18019e51ce9d234e161c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 03:18:50 2021 +// Design library name: multiplier_low +// Design cell name: nand2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..13c57813ced54f01f13b9bd4786a031b9077cab0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre7_6429_12 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..23aba9427fdb21ab5e0980598a082c220c00fb5f --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "nand2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..1f7e7997ba86e6d10993af9cdbacf56fedd68d3f --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,39 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:18:53 AM, Thur May 27, 2021 +# Number of equations = 24 +1\:A 1.79999996905874 +1\:B 1.80000001762401 +1\:gnd! 6.83850722220862e-08 +1\:Out 4.61817702331698e-05 +1\:vdd! 1.79999999999836 +2\:A 1.79999999998364 +2\:B 1.80000004918272 +2\:Out 4.61693028999511e-05 +2\:vdd! 1.80000000000058 +3\:A 1.79999990562612 +3\:B 1.80000045736887 +3\:Out 4.60653990479116e-05 +3\:vdd! 1.80000000000555 +4\:A 1.79999991368256 +4\:B 1.80000004309685 +4\:Out 4.64886973683658e-05 +5\:A 1.79999891907152 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 7.57693073099062e-05 +MN0:int_s 4.57392606644788e-05 +MN1:int_d 3.34840774210504e-07 +MN1:int_s 7.51069640567954e-05 +MP0:int_d 4.62049275583079e-05 +MP0:int_s 1.80000000002154 +MP1:int_d 1.79999999999344 +MP1:int_s 4.62049072861515e-05 +net9 7.54381356833508e-05 +Out 4.6488874791993e-05 +v0:p -3.19725669893949e-08 +v1:p -1.47261516732004e-08 +v2:p 0 +v3:p 8.3923835202358e-09 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..0a73c6133d5c8f495a75f3667a5931105b60761e --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,39 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:18:53 AM, Thur May 27, 2021 +# Number of equations = 24 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 4.0541356355123e-12 +1\:Out 1.1781384560353e-08 +1\:vdd! 1.79999999999778 +2\:A 1.8 +2\:B 1.8 +2\:Out 1.17777810906863e-08 +2\:vdd! 1.79999999999976 +3\:A 1.8 +3\:B 1.8 +3\:Out 1.17727484987019e-08 +3\:vdd! 1.79999999999768 +4\:A 1.8 +4\:B 1.8 +4\:Out 1.17777810906863e-08 +5\:A 1.8 +A 1.8 +B 1.8 +gnd! 0 +MN0:int_d 5.9036643785842e-09 +MN0:int_s 1.17569519581313e-08 +MN1:int_d 1.98506760443386e-11 +MN1:int_s 5.87207129768563e-09 +MP0:int_d 1.17880748598881e-08 +MP0:int_s 1.799999999991 +MP1:int_d 1.7999999999911 +MP1:int_s 1.17880748598881e-08 +net9 5.88786783813492e-09 +Out 1.17777810906863e-08 +v0:p -9.29208268778866e-12 +v1:p 0 +v2:p 0 +v3:p 0 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..05978d49965f0c8147f073d5f1bc0b6448afbaa1 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:18:50 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..a92b7a0327062e2d889c7e35c668a4f3c36968d7 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:18:54 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..0536f4a0ad0bcd96113d4974b49aa144f23e8b0f Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..9006c48af378e44ca1bf07be6a3684abe675ac5a Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..9adcef726770613856549294b7d107bfdef41773 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:18:54 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:18:54 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..d610248d3f01cc5db5ca15cf9e8579180769e4a6 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..18ae6805322cfbd8f4553ea712a68f2ee8afcfe0 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..93b26ddc7f9f59c3de58d510b7a05e4a2f7caf25 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:18:54 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic 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wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..f3f68eebb16db738c797c01a1412aa1d756cb8ac --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 03:18:54 2021" +"simulator" "spectre" +"date" "May 27 03:18:54 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..d8cf120ec2071431e61dcd9a7dbbce619747339c --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"nand2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 03:18:50 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..2b3bb8becac6392474bb1fe40a4cd21edc4a7e84 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,260 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 190549 +Memory available: 1.4304 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 2201.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 2201.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 2201.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 2201.0 35.1 + 11 1 1 1200.0 41.9 + 12 1 2 2201.0 29.6 + 13 1 3 2201.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1600.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 2201.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 3:18:53 AM, Thur May 27, 2021 (process id: 190549). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C3/nand2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre7_6429_12 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 190549 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/nand2_C3/nand2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_NAND_C3.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 61.991 ms, elapsed = 108.102 ms. +Time accumulated: CPU = 88.986 ms, elapsed = 108.106 ms. +Peak resident memory used = 38.8 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 24.995 ms, elapsed = 24.8952 ms. +Time accumulated: CPU = 114.981 ms, elapsed = 133.21 ms. +Peak resident memory used = 43.6 Mbytes. + +Time for EDB Visiting: CPU = 0 s, elapsed = 614.882 us. +Time accumulated: CPU = 114.981 ms, elapsed = 133.975 ms. +Peak resident memory used = 44.1 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 23 + bsim3v3 4 + capacitor 1 + resistor 17 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 3 ms, elapsed = 104.967 ms. +Time accumulated: CPU = 117.981 ms, elapsed = 239.1 ms. +Peak resident memory used = 45 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre7_6429_12, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 999 us, elapsed = 959.158 us. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 23 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.251 ns (7.5 %), step = 22.53 ps (75.1 m%) + +Notice from spectre at time = 2.37066 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:A. +Notice from spectre at time = 2.51293 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:A. +Notice from spectre at time = 2.77772 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:A. +Notice from spectre at time = 3.26881 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:A. +Notice from spectre at time = 3.86881 ns during transient analysis `tran'. + Found trapezoidal ringing on node 3\:A. + Further occurrences of this notice will be suppressed. + + tran: time = 3.869 ns (12.9 %), step = 600 ps (2 %) + tran: time = 5.669 ns (18.9 %), step = 600 ps (2 %) + tran: time = 6.869 ns (22.9 %), step = 600 ps (2 %) + tran: time = 8.669 ns (28.9 %), step = 600 ps (2 %) + tran: time = 9.869 ns (32.9 %), step = 600 ps (2 %) + tran: time = 11.67 ns (38.9 %), step = 600 ps (2 %) + tran: time = 12.87 ns (42.9 %), step = 600 ps (2 %) + tran: time = 14.26 ns (47.5 %), step = 26.94 ps (89.8 m%) + tran: time = 15.86 ns (52.9 %), step = 600 ps (2 %) + tran: time = 17.6 ns (58.7 %), step = 600 ps (2 %) + tran: time = 18.8 ns (62.7 %), step = 600 ps (2 %) + tran: time = 20.6 ns (68.7 %), step = 600 ps (2 %) + tran: time = 21.8 ns (72.7 %), step = 600 ps (2 %) + tran: time = 23.6 ns (78.7 %), step = 600 ps (2 %) + tran: time = 24.8 ns (82.7 %), step = 600 ps (2 %) + tran: time = 26.6 ns (88.7 %), step = 600 ps (2 %) + tran: time = 27.8 ns (92.7 %), step = 600 ps (2 %) + tran: time = 29.6 ns (98.7 %), step = 600 ps (2 %) +Number of accepted tran steps = 99 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 999 us, elapsed = 1.05906 ms. +Intrinsic tran analysis time: CPU = 15.997 ms, elapsed = 98.4049 ms. +Total time required for tran analysis `tran': CPU = 20.996 ms, elapsed = 103.326 ms. +Time accumulated: CPU = 142.977 ms, elapsed = 498.219 ms. +Peak resident memory used = 46.8 Mbytes. + + +Notice from spectre. + 7 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (3:24:27 AM, Thur May 27, 2021): +Time used: CPU = 218 ms, elapsed = 334 s (5m 34.0s), util. = 65.3e-03%. +Time spent in licensing: elapsed = 58 ms. +Peak memory used = 47.2 Mbytes. +Simulation started at: 3:18:53 AM, Thur May 27, 2021, ended at: 3:24:27 AM, Thur May 27, 2021, with elapsed time (wall clock): 334 s (5m 34.0s). +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..e3269cce0c763f19d80c0947dd81e2d0594a20d1 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:18:54 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..1c4f9d802948aeeb6d727cdc2ca50c95c68caef3 Binary files /dev/null and b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran.0.sig.tmp b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran.0.sig.tmp new file mode 100644 index 0000000000000000000000000000000000000000..cb7efa1d89a49c887ff6a5c7afa6be7dffc3520d --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran.0.sig.tmp @@ -0,0 +1,71 @@ +*cdnsheobpacket 26 1 +*cdnshlastgoodpoint 26 0,0 +*cdnshnumflushes 26 0 +*cdnshnxdbpid 26 190549 +*cdnshrunkey 26 -1 +*cdnshserieskey 26 -1 +*cdnshsweepcount 26 0 +*cdnshsweepprecision 26 -1 +*cdnshsweeprange 26 0,0 +*cdnshsweepstoptime 26 -1 +*cdnshtimestamp 26 2625931591622056734 +*cdnshuuid 26 20322014122324722113364757019519213111519562-3262487943-31622056734-3-862636253-7-367536670536657513 +:pwr 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 0 W 0 +A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 18 V 0 +B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 19 V 0 +Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 22 V 0 +\1\:A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1 V 0 +\1\:B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2 V 0 +\1\:Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 4 V 0 +\1\:gnd! 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0 1 592 0 2.9999999999999997319e-08 1.8000000000000000444 1.8000000000000000444 100 27 V 0 +­­¨ª|1|­­¨ª 0 0 0 23872 0 RootScope 28 28 0 0 0 0 0 0 <> +­­¨ª|142869456|­­¨ª 0 0 0 23872 0 RootScope 28 28 0 0 0 0 0 0 <> diff --git a/Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/psf/tran.tran.sig.tmp b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran.sig.tmp similarity index 100% rename from Design/simulation/ADE_output/inv_C3/inv/spectre/extracted/psf/tran.tran.sig.tmp rename to involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/tran.tran.sig.tmp diff --git a/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/variables_file b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/variables_file new file mode 100644 index 0000000000000000000000000000000000000000..afc22aa2df2d84bc116084b648bb0c98d6a0cf03 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/nand2/spectre/av_extracted/psf/variables_file @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"Time Stamp" "May 27 03:18:50 2021" +TYPE +"variable" STRUCT( +"value" FLOAT DOUBLE +) PROP( "key" "element" ) +VALUE +"temp" "variable" ( 27 ) PROP( ) +END diff --git a/Design/simulation/ADE_output/and2_C3/nand2/spectre/extracted/netlist/artSimEnvLog b/involution/Design/simulation/ADE_output/nand2_C3/xor2/spectre/av_extracted/netlist/artSimEnvLog similarity index 100% rename from Design/simulation/ADE_output/and2_C3/nand2/spectre/extracted/netlist/artSimEnvLog rename to involution/Design/simulation/ADE_output/nand2_C3/xor2/spectre/av_extracted/netlist/artSimEnvLog diff --git a/involution/Design/simulation/ADE_output/nand2_C3/xor2/spectre/av_extracted/netlist/spectre8.ocn b/involution/Design/simulation/ADE_output/nand2_C3/xor2/spectre/av_extracted/netlist/spectre8.ocn new file mode 100644 index 0000000000000000000000000000000000000000..070a8b45fcabbd2eb1cab05543e6e7a1f937a1b4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/nand2_C3/xor2/spectre/av_extracted/netlist/spectre8.ocn @@ -0,0 +1,41 @@ +simulator( 'spectre ) +design( "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C1/xor2/spectre/av_extracted/netlist/netlist") +resultsDir( "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C1/xor2/spectre/av_extracted" ) +modelFile( + '("/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" "NN") +) +analysis('tran ?stop "30n" ) +envOption( + 'analysisOrder list("tran") +) +temp( 27 ) +run() +resultsDir( "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C2/xor2/spectre/av_extracted" ) +modelFile( + '("/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" "NN") +) +run() +resultsDir( "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C3/xor2/spectre/av_extracted" ) +modelFile( + '("/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" "NN") +) +run() +resultsDir( "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C2/xor2/spectre/av_extracted" ) +modelFile( + '("/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" "NN") +) +run() +resultsDir( "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C3/xor2/spectre/av_extracted" ) +modelFile( + '("/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" "NN") +) +run() +modelFile( + '("/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" "NN") +) +run() +modelFile( + '("/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" "NN") +) +analysis('tran ?stop "40n" ) +run() diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/.control b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/.control new file mode 100755 index 0000000000000000000000000000000000000000..1beb90f7f38f765096259ec214ede2192c8d975e --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/.control @@ -0,0 +1,4 @@ + #!/bin/sh +xargs cat > netlist <" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..08a08705c73dbbbfae0ef256b60d7d4a79b29fac --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/xor2/av_extracted xor2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..8a76fece12e6d0fb658af299bbc414ba71e25cf4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 3:25:07 AM, Thur May 27, 2021 (process id: 40076). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre8_6429_13" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x66a15e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..154f04526777a625c04d185339b717e5988e06a9 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,105 @@ +// Generated for: spectre +// Generated on: May 27 03:25:06 2021 +// Design library name: multiplier_low +// Design cell name: xor2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_XOR_C1.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: xor2 +// View name: av_extracted +re1 (\4\:Ai \2\:Ai) resistor r=4.1723 c=0 +re2 (\7\:A \1\:A) resistor r=4.652 c=0 +re3 (Out \3\:Out) resistor r=5.0851 c=0 +rf1 (\1\:A A) resistor r=0.003806 c=0 +rf2 (\1\:A \2\:A) resistor r=0.006818 c=0 +rf3 (Ai \2\:Ai) resistor r=0.4786 c=0 +rf4 (\2\:Ai \3\:Ai) resistor r=0.6211 c=0 +rf5 (\5\:Ai \4\:Ai) resistor r=0.09851 c=0 +rf6 (\6\:A \7\:A) resistor r=0.007087 c=0 +rf7 (\1\:Out \2\:Out) resistor r=0.6277 c=0 +rf8 (\2\:Out \3\:Out) resistor r=0.2434 c=0 +rf9 (\2\:Out \4\:Out) resistor r=0.4877 c=0 +rf10 (\3\:Out \5\:Out) resistor r=0.637 c=0 +rf11 (\3\:Out \6\:Out) resistor r=0.4883 c=0 +rf12 (\5\:Bi \6\:Bi) resistor r=0.2091 c=0 +rf13 (\6\:Bi Bi) resistor r=0.419 c=0 +rf14 (\6\:Bi \7\:Bi) resistor r=0.9147 c=0 +rf15 (\1\:vdd! vdd!) resistor r=0.4396 c=0 +rf16 (vdd! \2\:vdd!) resistor r=0.02609 c=0 +rf17 (\2\:vdd! \3\:vdd!) resistor r=0.1063 c=0 +rf18 (\3\:vdd! \4\:vdd!) resistor r=0.1044 c=0 +rf19 (\4\:vdd! vdd!) resistor r=0.06674 c=0 +rf20 (vdd! \5\:vdd!) resistor r=0.1518 c=0 +rf21 (\5\:vdd! vdd!) resistor r=0.1358 c=0 +rf22 (vdd! \6\:vdd!) resistor r=0.0436 c=0 +rf23 (\6\:vdd! \7\:vdd!) resistor r=0.4398 c=0 +rf24 (\3\:vdd! \8\:vdd!) resistor r=0.4 c=0 +rf25 (\5\:vdd! \9\:vdd!) resistor r=0.4844 c=0 +rf27 (B \1\:B) resistor r=0.04913 c=0 +rf29 (\1\:gnd! \2\:gnd!) resistor r=0.4481 c=0 +rf30 (\2\:gnd! \3\:gnd!) resistor r=0.1073 c=0 +rf31 (\3\:gnd! \4\:gnd!) resistor r=0.1061 c=0 +rf32 (\4\:gnd! 0) resistor r=0.06321 c=0 +rf33 (0 \5\:gnd!) resistor r=0.159 c=0 +rf34 (\5\:gnd! \6\:gnd!) resistor r=0.1812 c=0 +rf35 (\3\:gnd! \7\:gnd!) resistor r=0.385 c=0 +rf36 (\5\:gnd! \8\:gnd!) resistor r=0.4644 c=0 +rf37 (\6\:gnd! \9\:gnd!) resistor r=0.4233 c=0 +rg1 (\3\:A \4\:A) resistor r=152.382 c=0 +rg2 (\4\:A \2\:A) resistor r=10.7763 c=0 +rg3 (\4\:A \5\:A) resistor r=56.5484 c=0 +rg4 (\6\:Ai \5\:Ai) resistor r=438.925 c=0 +rg5 (\5\:Ai \7\:Ai) resistor r=89.7447 c=0 +rg6 (\8\:A \9\:A) resistor r=257.237 c=0 +rg7 (\9\:A \6\:A) resistor r=27.4119 c=0 +rg8 (\9\:A \10\:A) resistor r=53.5985 c=0 +rg9 (Bi \2\:Bi) resistor r=2.0523 c=0 +rg10 (\2\:Bi \3\:Bi) resistor r=38.5093 c=0 +rg11 (\2\:Bi \4\:Bi) resistor r=170.801 c=0 +rg12 (\1\:B \2\:B) resistor r=7.3761 c=0 +rg13 (\2\:B \3\:B) resistor r=170.445 c=0 +rg14 (\3\:B \4\:B) resistor r=337.766 c=0 +rg15 (\4\:B \5\:B) resistor r=299.266 c=0 +rg16 (\2\:B \6\:B) resistor r=38.7782 c=0 +MP5 (\1\:vdd! \3\:B \7\:Bi vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP4 (Ai \3\:A \7\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MP0 (net8 \7\:Ai \9\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\6\:Out \4\:B net8 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP3 (net022 \8\:A \4\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP2 (\8\:vdd! \4\:Bi net022 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN5 (\1\:gnd! \6\:B \5\:Bi 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN4 (\3\:Ai \5\:A \9\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN3 (net17 \5\:B \8\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\5\:Out \10\:A net17 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net32 \6\:Ai \1\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\7\:gnd! \3\:Bi net32 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..56648be87542da9474e9a37e41561aed51460ea3 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "xor2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C1/xor2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/xor2/av_extracted" "xor2" ) + ) +( term + ) +( param + ) +( "xor2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..b63a8da30defc81ef0d9f1319877259b09692f91 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,82 @@ + +// Library name: multiplier_low +// Cell name: xor2 +// View name: av_extracted +re1 (\4\:Ai \2\:Ai) resistor r=4.1723 c=0 +re2 (\7\:A \1\:A) resistor r=4.652 c=0 +re3 (Out \3\:Out) resistor r=5.0851 c=0 +rf1 (\1\:A A) resistor r=0.003806 c=0 +rf2 (\1\:A \2\:A) resistor r=0.006818 c=0 +rf3 (Ai \2\:Ai) resistor r=0.4786 c=0 +rf4 (\2\:Ai \3\:Ai) resistor r=0.6211 c=0 +rf5 (\5\:Ai \4\:Ai) resistor r=0.09851 c=0 +rf6 (\6\:A \7\:A) resistor r=0.007087 c=0 +rf7 (\1\:Out \2\:Out) resistor r=0.6277 c=0 +rf8 (\2\:Out \3\:Out) resistor r=0.2434 c=0 +rf9 (\2\:Out \4\:Out) resistor r=0.4877 c=0 +rf10 (\3\:Out \5\:Out) resistor r=0.637 c=0 +rf11 (\3\:Out \6\:Out) resistor r=0.4883 c=0 +rf12 (\5\:Bi \6\:Bi) resistor r=0.2091 c=0 +rf13 (\6\:Bi Bi) resistor r=0.419 c=0 +rf14 (\6\:Bi \7\:Bi) resistor r=0.9147 c=0 +rf15 (\1\:vdd! vdd!) resistor r=0.4396 c=0 +rf16 (vdd! \2\:vdd!) resistor r=0.02609 c=0 +rf17 (\2\:vdd! \3\:vdd!) resistor r=0.1063 c=0 +rf18 (\3\:vdd! \4\:vdd!) resistor r=0.1044 c=0 +rf19 (\4\:vdd! vdd!) resistor r=0.06674 c=0 +rf20 (vdd! \5\:vdd!) resistor r=0.1518 c=0 +rf21 (\5\:vdd! vdd!) resistor r=0.1358 c=0 +rf22 (vdd! \6\:vdd!) resistor r=0.0436 c=0 +rf23 (\6\:vdd! \7\:vdd!) resistor r=0.4398 c=0 +rf24 (\3\:vdd! \8\:vdd!) resistor r=0.4 c=0 +rf25 (\5\:vdd! \9\:vdd!) resistor r=0.4844 c=0 +rf27 (B \1\:B) resistor r=0.04913 c=0 +rf29 (\1\:gnd! \2\:gnd!) resistor r=0.4481 c=0 +rf30 (\2\:gnd! \3\:gnd!) resistor r=0.1073 c=0 +rf31 (\3\:gnd! \4\:gnd!) resistor r=0.1061 c=0 +rf32 (\4\:gnd! 0) resistor r=0.06321 c=0 +rf33 (0 \5\:gnd!) resistor r=0.159 c=0 +rf34 (\5\:gnd! \6\:gnd!) resistor r=0.1812 c=0 +rf35 (\3\:gnd! \7\:gnd!) resistor r=0.385 c=0 +rf36 (\5\:gnd! \8\:gnd!) resistor r=0.4644 c=0 +rf37 (\6\:gnd! \9\:gnd!) resistor r=0.4233 c=0 +rg1 (\3\:A \4\:A) resistor r=152.382 c=0 +rg2 (\4\:A \2\:A) resistor r=10.7763 c=0 +rg3 (\4\:A \5\:A) resistor r=56.5484 c=0 +rg4 (\6\:Ai \5\:Ai) resistor r=438.925 c=0 +rg5 (\5\:Ai \7\:Ai) resistor r=89.7447 c=0 +rg6 (\8\:A \9\:A) resistor r=257.237 c=0 +rg7 (\9\:A \6\:A) resistor r=27.4119 c=0 +rg8 (\9\:A \10\:A) resistor r=53.5985 c=0 +rg9 (Bi \2\:Bi) resistor r=2.0523 c=0 +rg10 (\2\:Bi \3\:Bi) resistor r=38.5093 c=0 +rg11 (\2\:Bi \4\:Bi) resistor r=170.801 c=0 +rg12 (\1\:B \2\:B) resistor r=7.3761 c=0 +rg13 (\2\:B \3\:B) resistor r=170.445 c=0 +rg14 (\3\:B \4\:B) resistor r=337.766 c=0 +rg15 (\4\:B \5\:B) resistor r=299.266 c=0 +rg16 (\2\:B \6\:B) resistor r=38.7782 c=0 +MP5 (\1\:vdd! \3\:B \7\:Bi vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP4 (Ai \3\:A \7\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MP0 (net8 \7\:Ai \9\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\6\:Out \4\:B net8 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP3 (net022 \8\:A \4\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP2 (\8\:vdd! \4\:Bi net022 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN5 (\1\:gnd! \6\:B \5\:Bi 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN4 (\3\:Ai \5\:A \9\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN3 (net17 \5\:B \8\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\5\:Out \10\:A net17 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net32 \6\:Ai \1\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\7\:gnd! \3\:Bi net32 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..fe3123c12becccd717eecda8c6c1438f31d4f8a3 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 03:25:06 2021 +// Design library name: multiplier_low +// Design cell name: xor2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..14c71bcaf1f28bf991bcd35fa1d181846dac96be --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre8_6429_13 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..7413b1aa1770672a025b4e56e89d6883dc9ce092 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "xor2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..5cf5026e1203f9d580d87a0dc19eb6143aec37df --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 03:25:06 2021 +End netlisting May 27 03:25:06 2021 diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..0149523b96b8ef4cedf23fc6652269a00c22c90f --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,95 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:25:07 AM, Thur May 27, 2021 +# Number of equations = 64 +1\:A 1.7999999999999 +1\:B 1.80000000000073 +1\:gnd! 4.39098374992629e-12 +1\:Out 2.79890579025077e-08 +1\:vdd! 1.79999999999803 +2\:A 1.79999999999926 +2\:Ai 1.5225229119729e-09 +2\:B 1.80000000011073 +2\:Bi 1.95286589074861e-09 +2\:gnd! 3.07149872669312e-12 +2\:Out 2.79821969561265e-08 +2\:vdd! 1.79999999999994 +3\:A 1.79999999353383 +3\:Ai 1.52932335067767e-09 +3\:B 1.8000000026994 +3\:Bi 1.89298068865468e-09 +3\:gnd! 2.75554080883345e-12 +3\:Out 2.79798144405934e-08 +3\:vdd! 1.7999999999997 +4\:A 1.79999999898426 +4\:Ai 1.45034332744618e-09 +4\:B 1.80000000802235 +4\:Bi 1.65986347012588e-09 +4\:gnd! 1.02875042541115e-12 +4\:Out 2.79816400917885e-08 +4\:vdd! 1.79999999999988 +5\:A 1.79999999568071 +5\:Ai 1.44863913290798e-09 +5\:B 1.80000001265475 +5\:Bi 1.96051814531521e-09 +5\:gnd! 8.30875074914061e-12 +5\:Out 2.79386564079984e-08 +5\:vdd! 1.80000000000013 +6\:A 1.80000000032227 +6\:Ai -1.66212330276916e-09 +6\:B 1.80000000010007 +6\:Bi 1.96094838849342e-09 +6\:gnd! 1.48946906025782e-11 +6\:Out 2.79804792550785e-08 +6\:vdd! 1.80000000000029 +7\:A 1.80000000032178 +7\:Ai 5.32123084014279e-10 +7\:Bi 1.96582203838806e-09 +7\:gnd! 7.88778316988621e-12 +7\:vdd! 1.80000000000323 +8\:A 1.80000000451642 +8\:gnd! 1.56973768489974e-11 +8\:vdd! 1.79999999999809 +9\:A 1.80000000221926 +9\:gnd! 3.02800567171484e-11 +9\:vdd! 1.80000000000098 +10\:A 1.80000000544981 +A 1.8 +Ai 1.52556235088629e-09 +B 1.8 +Bi 1.9595780301577e-09 +gnd! 0 +MN0:int_d 1.09113699302159 +MN0:int_s 2.80076394045755e-08 +MN1:int_d 3.05496325563529e-11 +MN1:int_s 1.09113699301861 +MN2:int_d 2.78288155046835e-08 +MN2:int_s 2.32810058940311e-08 +MN3:int_d 2.32426787723287e-08 +MN3:int_s 4.27444577485595e-11 +MN4:int_d 1.54793669119949e-09 +MN4:int_s 9.20686756511653e-11 +MN5:int_d 9.39684078964152e-12 +MN5:int_s 1.95702023329721e-09 +MP0:int_d 1.79999998845015 +MP0:int_s 1.8000000000035 +MP1:int_d 2.7982439797488e-08 +MP1:int_s 1.79999998843114 +MP2:int_d 1.79999999999231 +MP2:int_s 1.79999998842852 +MP3:int_d 1.79999998840985 +MP3:int_s 2.79799958747561e-08 +MP4:int_d 1.53470734051286e-09 +MP4:int_s 1.80000000001287 +MP5:int_d 1.79999999999156 +MP5:int_s 1.9734945603606e-09 +net8 1.79999998844065 +net17 2.32618423331799e-08 +net022 1.79999998841919 +net32 1.0911369930201 +Out 2.82516757365688e-08 +v0:p 2.71544618114613e-11 +v1:p -2.51166541505237e-11 +v2:p 0 +v3:p 1.49102815829976e-11 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..3d04594e205ef5c29982251727c01882fc9044c2 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,95 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:25:07 AM, Thur May 27, 2021 +# Number of equations = 64 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 3.36703285815914e-12 +1\:Out 1.17811095262107e-08 +1\:vdd! 1.79999999999796 +2\:A 1.8 +2\:Ai 2.9497936821549e-09 +2\:B 1.8 +2\:Bi 2.94622183211162e-09 +2\:gnd! 1.28514172926229e-12 +2\:Out 1.17811095269634e-08 +2\:vdd! 1.79999999999993 +3\:A 1.8 +3\:Ai 2.94690802586508e-09 +3\:B 1.8 +3\:Bi 2.94622183211162e-09 +3\:gnd! 7.86621492416421e-13 +3\:Out 1.17799786811327e-08 +3\:vdd! 1.79999999999965 +4\:A 1.8 +4\:Ai 2.94979368215489e-09 +4\:B 1.8 +4\:Bi 2.94622183211162e-09 +4\:gnd! 2.93676360142e-13 +4\:Out 1.17833754006443e-08 +4\:vdd! 1.79999999999986 +5\:A 1.8 +5\:Ai 2.94979368215489e-09 +5\:B 1.8 +5\:Bi 2.94525034486286e-09 +5\:gnd! 2.21616107119979e-12 +5\:Out 1.17740596270072e-08 +5\:vdd! 1.79999999999967 +6\:A 1.80000000000006 +6\:Ai 2.94979368215489e-09 +6\:B 1.8 +6\:Bi 2.94622183211162e-09 +6\:gnd! 3.0580237637966e-12 +6\:Out 1.17822473424376e-08 +6\:vdd! 1.7999999999998 +7\:A 1.80000000000006 +7\:Ai 2.94979368215489e-09 +7\:Bi 2.95047156614529e-09 +7\:gnd! 7.86622018746815e-13 +7\:vdd! 1.79999999999776 +8\:A 1.80000000000006 +8\:gnd! 6.531402370616e-12 +8\:vdd! 1.7999999999978 +9\:A 1.80000000000006 +9\:gnd! 5.02469306719741e-12 +9\:vdd! 1.79999999999742 +10\:A 1.80000000000006 +A 1.8 +Ai 2.95201727755065e-09 +B 1.8 +Bi 2.94622183211162e-09 +gnd! 0 +MN0:int_d -2.63267897631264e-08 +MN0:int_s 1.17811095241722e-08 +MN1:int_d 7.866243428031e-13 +MN1:int_s -2.63267897674158e-08 +MN2:int_d 1.17582630932342e-08 +MN2:int_s 5.90609201144538e-09 +MN3:int_d 5.87449894414211e-09 +MN3:int_s 2.23279359817434e-11 +MN4:int_d 2.93900975555002e-09 +MN4:int_s 1.29229633619798e-11 +MN5:int_d 1.12653031530144e-11 +MN5:int_s 2.93735207454775e-09 +MP0:int_d 1.79999998826053 +MP0:int_s 1.79999999999074 +MP1:int_d 1.17889376399578e-08 +MP1:int_s 1.79999998824717 +MP2:int_d 1.79999999999112 +MP2:int_s 1.79999998826091 +MP3:int_d 1.79999998824755 +MP3:int_s 1.17900656981645e-08 +MP4:int_d 2.95870757711165e-09 +MP4:int_s 1.79999999999108 +MP5:int_d 1.79999999999128 +MP5:int_s 2.95716186570632e-09 +net8 1.79999998825385 +net17 5.89029547779375e-09 +net022 1.79999998825423 +net32 -2.63267897652677e-08 +Out 1.17799786811327e-08 +v0:p -1.86129395935218e-11 +v1:p 1.37390099297368e-14 +v2:p 0 +v3:p -1.56125112837913e-18 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..262c81789b063c0c4fd22af6d2f88385814504cc --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:25:06 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..b150a81dd27c3986f4c30e87845f57090b5df74a --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:25:07 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..70a3cb9ce6eec796e27a45b08d8cdb6477995a09 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..fdb282af15f314acfad58f369f1888a5e635617e Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..4393d914430ecf0d7fd073775b4b7a4e9882598d --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:25:07 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:25:07 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..554a9324ec85b75e42a88a28c5416af93044e7b0 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..0a1c0e20359311ac0c0a225b869ea30ea49ee53b Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..91d205f9cda15fec45dd9131d6dfb419f56a18b1 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:25:07 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type 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ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..a5f56754866de4c5e7385464197618567af90d25 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 03:25:07 2021" +"simulator" "spectre" +"date" "May 27 03:25:07 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..caadb1020381a6463392dab938bad4544374c4d0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"xor2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 03:25:06 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..abfe08ee374dc608ba58275beb545fc8ced11697 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,251 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 40076 +Memory available: 1.3992 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 2201.0 37.1 + 1 0 1 2201.0 42.5 + 2 0 2 2201.0 30.6 + 3 0 3 1200.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 1200.0 41.9 + 12 1 2 1200.0 29.6 + 13 1 3 2201.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 2201.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 2201.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 2201.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 3:25:07 AM, Thur May 27, 2021 (process id: 40076). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C1/xor2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre8_6429_13 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 40076 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C1/xor2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_XOR_C1.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 68.989 ms, elapsed = 115.552 ms. +Time accumulated: CPU = 99.983 ms, elapsed = 115.557 ms. +Peak resident memory used = 38.8 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 30.996 ms, elapsed = 30.534 ms. +Time accumulated: CPU = 130.979 ms, elapsed = 146.281 ms. +Peak resident memory used = 43.8 Mbytes. + +Time for EDB Visiting: CPU = 999 us, elapsed = 1.2002 ms. +Time accumulated: CPU = 131.978 ms, elapsed = 147.669 ms. +Peak resident memory used = 44.3 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 63 + bsim3v3 12 + capacitor 1 + resistor 54 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 3 ms, elapsed = 132.863 ms. +Time accumulated: CPU = 134.978 ms, elapsed = 280.704 ms. +Peak resident memory used = 45.3 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre8_6429_13, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 1 ms, elapsed = 1.07288 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 63 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + tran: time = 2.255 ns (7.52 %), step = 12.74 ps (42.5 m%) + +Notice from spectre at time = 3.7929 ns during transient analysis `tran'. + Found trapezoidal ringing on node 6\:Ai. + + tran: time = 3.793 ns (12.6 %), step = 283.2 ps (944 m%) + +Notice from spectre at time = 4.19259 ns during transient analysis `tran'. + Found trapezoidal ringing on node 6\:Ai. + + tran: time = 5.343 ns (17.8 %), step = 332.8 ps (1.11 %) + tran: time = 7 ns (23.3 %), step = 600 ps (2 %) + tran: time = 8.8 ns (29.3 %), step = 600 ps (2 %) + tran: time = 10 ns (33.3 %), step = 600 ps (2 %) + tran: time = 11.8 ns (39.3 %), step = 600 ps (2 %) + tran: time = 13 ns (43.3 %), step = 600 ps (2 %) + tran: time = 14.8 ns (49.3 %), step = 600 ps (2 %) + tran: time = 16 ns (53.3 %), step = 600 ps (2 %) + tran: time = 17.8 ns (59.3 %), step = 600 ps (2 %) + tran: time = 19 ns (63.3 %), step = 600 ps (2 %) + tran: time = 20.8 ns (69.3 %), step = 600 ps (2 %) + tran: time = 22 ns (73.3 %), step = 600 ps (2 %) + tran: time = 23.8 ns (79.3 %), step = 600 ps (2 %) + tran: time = 25 ns (83.3 %), step = 600 ps (2 %) + tran: time = 26.8 ns (89.3 %), step = 600 ps (2 %) + tran: time = 28 ns (93.3 %), step = 600 ps (2 %) + tran: time = 29.6 ns (98.7 %), step = 400 ps (1.33 %) +Number of accepted tran steps = 143 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1 ms, elapsed = 1.16682 ms. +Intrinsic tran analysis time: CPU = 30.995 ms, elapsed = 142.977 ms. +Total time required for tran analysis `tran': CPU = 33.995 ms, elapsed = 146.528 ms. +Time accumulated: CPU = 174.972 ms, elapsed = 606.274 ms. +Peak resident memory used = 47.5 Mbytes. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (3:25:17 AM, Thur May 27, 2021): +Time used: CPU = 245 ms, elapsed = 10.2 s, util. = 2.39%. +Time spent in licensing: elapsed = 60.8 ms. +Peak memory used = 47.6 Mbytes. +Simulation started at: 3:25:07 AM, Thur May 27, 2021, ended at: 3:25:17 AM, Thur May 27, 2021, with elapsed time (wall clock): 10.2 s. +spectre completes with 0 errors, 3 warnings, and 4 notices. diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..40818d59ca7d17d1d1bbf58480a8ae7398d86048 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:25:07 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..a9d06a1527a5319507b31ccfe4382b0687bc577c Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp new file mode 100644 index 0000000000000000000000000000000000000000..c3497308d56576dd2a688d31e7795e72db214fa3 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp @@ -0,0 +1,151 @@ +*cdnsheobpacket 26 1 +*cdnshlastgoodpoint 26 0,0 +*cdnshnumflushes 26 0 +*cdnshnxdbpid 26 40076 +*cdnshrunkey 26 -1 +*cdnshserieskey 26 -1 +*cdnshsweepcount 26 0 +*cdnshsweepprecision 26 -1 +*cdnshsweeprange 26 0,0 +*cdnshsweepstoptime 26 -1 +*cdnshtimestamp 26 476101411622057108 +*cdnshuuid 26 252693311310317518081154212138160240106477-347548936-31622057108-3-862636253-7-367536670536657513 +:pwr 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 0 W 0 +A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 53 V 0 +Ai 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 54 V 0 +B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 55 V 0 +Bi 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 56 V 0 +Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 62 V 0 +\10\:A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 52 V 0 +\1\:A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1 V 0 +\1\:B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2 V 0 +\1\:Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 4 V 0 +\1\:gnd! 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0 1 912 0 2.9999999999999997319e-08 1.7999167023935671583 1.8000085127640261806 144 45 V 0 +­­¨©|122410064|­­¨© 0 0 0 912 122227744 \8\:A 0 1 912 0 2.9999999999999997319e-08 -0.00039029616983346157588 1.8000057181572797216 144 46 V 0 +­­¨©|122410976|­­¨© 0 0 0 912 122227744 \8\:gnd! 0 1 912 0 2.9999999999999997319e-08 -1.0974951165097888785e-05 0.00019631549014145126351 144 47 V 0 +­­¨©|122411888|­­¨© 0 0 0 912 122227744 \8\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999451231383101213 1.8000038034294016942 144 48 V 0 +­­¨©|122412800|­­¨© 0 0 0 912 122227744 \9\:A 0 1 912 0 2.9999999999999997319e-08 -1.3815421299535543542e-05 1.8000089700394827918 144 49 V 0 +­­¨©|122413712|­­¨© 0 0 0 912 122227744 \9\:gnd! 0 1 912 0 2.9999999999999997319e-08 -1.5359254000827491531e-05 0.00022672902927772277393 144 50 V 0 +­­¨©|122414624|­­¨© 0 0 0 912 122227744 \9\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999681791495238947 1.8000169146348601323 144 51 V 0 +­­¨©|122416000|­­¨© 0 0 0 912 122227744 \10\:A 0 1 912 0 2.9999999999999997319e-08 -7.122462832171341904e-06 1.8000246397779562368 144 52 V 0 +­­¨©|122416880|­­¨© 0 0 0 912 122227744 A 0 1 912 0 2.9999999999999997319e-08 0 1.8000000000000000444 144 53 V 0 +­­¨©|122417792|­­¨© 0 0 0 912 122227744 Ai 0 1 912 0 2.9999999999999997319e-08 -0.0075329547440748413634 1.8275337630569461478 144 54 V 0 +­­¨©|122418704|­­¨© 0 0 0 912 122227744 B 0 1 912 0 2.9999999999999997319e-08 1.8000000000000000444 1.8000000000000000444 144 55 V 0 +­­¨©|122419616|­­¨© 0 0 0 912 122227744 Bi 0 1 912 0 2.9999999999999997319e-08 -0.0013914062761322940932 0.00080424743080930794544 144 56 V 0 +­­¨©|122420528|­­¨© 0 0 0 912 122227744 gnd! 0 1 912 0 2.9999999999999997319e-08 0 0 144 57 V 0 +­­¨©|122421440|­­¨© 0 0 0 912 122227744 net8 0 1 912 0 2.9999999999999997319e-08 1.7560532709690317432 1.9300295324761109761 144 58 V 0 +­­¨©|122422352|­­¨© 0 0 0 912 122227744 net17 0 1 912 0 2.9999999999999997319e-08 -0.0086092084925157887076 0.28501042095825324107 144 59 V 0 +­­¨©|122423264|­­¨© 0 0 0 912 122227744 net022 0 1 912 0 2.9999999999999997319e-08 1.446028058308981068 1.8196023609777547403 144 60 V 0 +­­¨©|122424176|­­¨© 0 0 0 912 122227744 net32 0 1 912 0 2.9999999999999997319e-08 -0.00041347452695024482444 1.2206168126437553223 144 61 V 0 +­­¨©|122425088|­­¨© 0 0 0 912 122227744 Out 0 1 912 0 2.9999999999999997319e-08 -0.014092445680804595309 1.8193773198895817345 144 62 V 0 +­­¨©|122426000|­­¨© 0 0 0 912 122227744 v0:p 0 1 912 0 2.9999999999999997319e-08 -0.00020012671412806951922 3.0112360149756719818e-05 144 63 A 0 +­­¨©|122426912|­­¨© 0 0 0 912 122227744 v1:p 0 1 912 0 2.9999999999999997319e-08 -8.3105821298452733741e-05 6.5008022718139623665e-05 144 64 A 0 +­­¨©|122428448|­­¨© 0 0 0 912 122227744 v2:p 0 1 912 0 2.9999999999999997319e-08 0 0 144 65 A 0 +­­¨©|122429248|­­¨© 0 0 0 912 122227744 v3:p 0 1 912 0 2.9999999999999997319e-08 -5.2872530039054443999e-06 2.6272615797060801987e-06 144 66 A 0 +­­¨©|122430160|­­¨© 0 0 0 912 122227744 vdd! 0 1 912 0 2.9999999999999997319e-08 1.8000000000000000444 1.8000000000000000444 144 67 V 0 +­­¨ª|1|­­¨ª 0 0 0 80480 0 RootScope 68 68 0 0 0 0 0 0 <> +­­¨ª|122227744|­­¨ª 0 0 0 80480 0 RootScope 68 68 0 0 0 0 0 0 <> diff --git a/Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/psf/tran.tran.sig.tmp b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran.sig.tmp similarity index 100% rename from Design/simulation/ADE_output/nand2_C1/nand2/spectre/extracted/psf/tran.tran.sig.tmp rename to involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/tran.tran.sig.tmp diff --git a/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/variables_file b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/variables_file new file mode 100644 index 0000000000000000000000000000000000000000..5b25561ae98b73a0cc17da52c6f83de424fe5196 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C1/xor2/spectre/av_extracted/psf/variables_file @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"Time Stamp" "May 27 03:25:06 2021" +TYPE +"variable" STRUCT( +"value" FLOAT DOUBLE +) PROP( "key" "element" ) +VALUE +"temp" "variable" ( 27 ) PROP( ) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/.control b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/.control new file mode 100755 index 0000000000000000000000000000000000000000..1beb90f7f38f765096259ec214ede2192c8d975e --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/.control @@ -0,0 +1,4 @@ + #!/bin/sh +xargs cat > netlist <" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..08a08705c73dbbbfae0ef256b60d7d4a79b29fac --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/xor2/av_extracted xor2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..162a6df9e0df04eb2a5187367562c7028dcbcba7 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,8 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 3:28:01 AM, Thur May 27, 2021 (process id: 60859). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre8_6429_16" ) +H->sclSetResultDir( "../psf" ) +H->sclRun( "all" ) +sclCkt0x7f0f5e0 = H->sclGetCircuit( "" ) +H->sclQuit( ) diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..f2beef95797796993e829f1b5d5561e21d4d4c64 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,105 @@ +// Generated for: spectre +// Generated on: May 27 03:28:00 2021 +// Design library name: multiplier_low +// Design cell name: xor2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_XOR_C2.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: xor2 +// View name: av_extracted +re1 (\4\:Ai \2\:Ai) resistor r=4.1723 c=0 +re2 (\7\:A \1\:A) resistor r=4.652 c=0 +re3 (Out \3\:Out) resistor r=5.0851 c=0 +rf1 (\1\:A A) resistor r=0.003806 c=0 +rf2 (\1\:A \2\:A) resistor r=0.006818 c=0 +rf3 (Ai \2\:Ai) resistor r=0.4786 c=0 +rf4 (\2\:Ai \3\:Ai) resistor r=0.6211 c=0 +rf5 (\5\:Ai \4\:Ai) resistor r=0.09851 c=0 +rf6 (\6\:A \7\:A) resistor r=0.007087 c=0 +rf7 (\1\:Out \2\:Out) resistor r=0.6277 c=0 +rf8 (\2\:Out \3\:Out) resistor r=0.2434 c=0 +rf9 (\2\:Out \4\:Out) resistor r=0.4877 c=0 +rf10 (\3\:Out \5\:Out) resistor r=0.637 c=0 +rf11 (\3\:Out \6\:Out) resistor r=0.4883 c=0 +rf12 (\5\:Bi \6\:Bi) resistor r=0.2091 c=0 +rf13 (\6\:Bi Bi) resistor r=0.419 c=0 +rf14 (\6\:Bi \7\:Bi) resistor r=0.9147 c=0 +rf15 (\1\:vdd! vdd!) resistor r=0.4396 c=0 +rf16 (vdd! \2\:vdd!) resistor r=0.02609 c=0 +rf17 (\2\:vdd! \3\:vdd!) resistor r=0.1063 c=0 +rf18 (\3\:vdd! \4\:vdd!) resistor r=0.1044 c=0 +rf19 (\4\:vdd! vdd!) resistor r=0.06674 c=0 +rf20 (vdd! \5\:vdd!) resistor r=0.1518 c=0 +rf21 (\5\:vdd! vdd!) resistor r=0.1358 c=0 +rf22 (vdd! \6\:vdd!) resistor r=0.0436 c=0 +rf23 (\6\:vdd! \7\:vdd!) resistor r=0.4398 c=0 +rf24 (\3\:vdd! \8\:vdd!) resistor r=0.4 c=0 +rf25 (\5\:vdd! \9\:vdd!) resistor r=0.4844 c=0 +rf27 (B \1\:B) resistor r=0.04913 c=0 +rf29 (\1\:gnd! \2\:gnd!) resistor r=0.4481 c=0 +rf30 (\2\:gnd! \3\:gnd!) resistor r=0.1073 c=0 +rf31 (\3\:gnd! \4\:gnd!) resistor r=0.1061 c=0 +rf32 (\4\:gnd! 0) resistor r=0.06321 c=0 +rf33 (0 \5\:gnd!) resistor r=0.159 c=0 +rf34 (\5\:gnd! \6\:gnd!) resistor r=0.1812 c=0 +rf35 (\3\:gnd! \7\:gnd!) resistor r=0.385 c=0 +rf36 (\5\:gnd! \8\:gnd!) resistor r=0.4644 c=0 +rf37 (\6\:gnd! \9\:gnd!) resistor r=0.4233 c=0 +rg1 (\3\:A \4\:A) resistor r=152.382 c=0 +rg2 (\4\:A \2\:A) resistor r=10.7763 c=0 +rg3 (\4\:A \5\:A) resistor r=56.5484 c=0 +rg4 (\6\:Ai \5\:Ai) resistor r=438.925 c=0 +rg5 (\5\:Ai \7\:Ai) resistor r=89.7447 c=0 +rg6 (\8\:A \9\:A) resistor r=257.237 c=0 +rg7 (\9\:A \6\:A) resistor r=27.4119 c=0 +rg8 (\9\:A \10\:A) resistor r=53.5985 c=0 +rg9 (Bi \2\:Bi) resistor r=2.0523 c=0 +rg10 (\2\:Bi \3\:Bi) resistor r=38.5093 c=0 +rg11 (\2\:Bi \4\:Bi) resistor r=170.801 c=0 +rg12 (\1\:B \2\:B) resistor r=7.3761 c=0 +rg13 (\2\:B \3\:B) resistor r=170.445 c=0 +rg14 (\3\:B \4\:B) resistor r=337.766 c=0 +rg15 (\4\:B \5\:B) resistor r=299.266 c=0 +rg16 (\2\:B \6\:B) resistor r=38.7782 c=0 +MP5 (\1\:vdd! \3\:B \7\:Bi vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP4 (Ai \3\:A \7\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MP0 (net8 \7\:Ai \9\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\6\:Out \4\:B net8 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP3 (net022 \8\:A \4\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP2 (\8\:vdd! \4\:Bi net022 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN5 (\1\:gnd! \6\:B \5\:Bi 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN4 (\3\:Ai \5\:A \9\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN3 (net17 \5\:B \8\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\5\:Out \10\:A net17 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net32 \6\:Ai \1\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\7\:gnd! \3\:Bi net32 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..830d0974ee1dce75704a90c7861a2943a3f58ef7 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "xor2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C2/xor2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/xor2/av_extracted" "xor2" ) + ) +( term + ) +( param + ) +( "xor2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..b63a8da30defc81ef0d9f1319877259b09692f91 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,82 @@ + +// Library name: multiplier_low +// Cell name: xor2 +// View name: av_extracted +re1 (\4\:Ai \2\:Ai) resistor r=4.1723 c=0 +re2 (\7\:A \1\:A) resistor r=4.652 c=0 +re3 (Out \3\:Out) resistor r=5.0851 c=0 +rf1 (\1\:A A) resistor r=0.003806 c=0 +rf2 (\1\:A \2\:A) resistor r=0.006818 c=0 +rf3 (Ai \2\:Ai) resistor r=0.4786 c=0 +rf4 (\2\:Ai \3\:Ai) resistor r=0.6211 c=0 +rf5 (\5\:Ai \4\:Ai) resistor r=0.09851 c=0 +rf6 (\6\:A \7\:A) resistor r=0.007087 c=0 +rf7 (\1\:Out \2\:Out) resistor r=0.6277 c=0 +rf8 (\2\:Out \3\:Out) resistor r=0.2434 c=0 +rf9 (\2\:Out \4\:Out) resistor r=0.4877 c=0 +rf10 (\3\:Out \5\:Out) resistor r=0.637 c=0 +rf11 (\3\:Out \6\:Out) resistor r=0.4883 c=0 +rf12 (\5\:Bi \6\:Bi) resistor r=0.2091 c=0 +rf13 (\6\:Bi Bi) resistor r=0.419 c=0 +rf14 (\6\:Bi \7\:Bi) resistor r=0.9147 c=0 +rf15 (\1\:vdd! vdd!) resistor r=0.4396 c=0 +rf16 (vdd! \2\:vdd!) resistor r=0.02609 c=0 +rf17 (\2\:vdd! \3\:vdd!) resistor r=0.1063 c=0 +rf18 (\3\:vdd! \4\:vdd!) resistor r=0.1044 c=0 +rf19 (\4\:vdd! vdd!) resistor r=0.06674 c=0 +rf20 (vdd! \5\:vdd!) resistor r=0.1518 c=0 +rf21 (\5\:vdd! vdd!) resistor r=0.1358 c=0 +rf22 (vdd! \6\:vdd!) resistor r=0.0436 c=0 +rf23 (\6\:vdd! \7\:vdd!) resistor r=0.4398 c=0 +rf24 (\3\:vdd! \8\:vdd!) resistor r=0.4 c=0 +rf25 (\5\:vdd! \9\:vdd!) resistor r=0.4844 c=0 +rf27 (B \1\:B) resistor r=0.04913 c=0 +rf29 (\1\:gnd! \2\:gnd!) resistor r=0.4481 c=0 +rf30 (\2\:gnd! \3\:gnd!) resistor r=0.1073 c=0 +rf31 (\3\:gnd! \4\:gnd!) resistor r=0.1061 c=0 +rf32 (\4\:gnd! 0) resistor r=0.06321 c=0 +rf33 (0 \5\:gnd!) resistor r=0.159 c=0 +rf34 (\5\:gnd! \6\:gnd!) resistor r=0.1812 c=0 +rf35 (\3\:gnd! \7\:gnd!) resistor r=0.385 c=0 +rf36 (\5\:gnd! \8\:gnd!) resistor r=0.4644 c=0 +rf37 (\6\:gnd! \9\:gnd!) resistor r=0.4233 c=0 +rg1 (\3\:A \4\:A) resistor r=152.382 c=0 +rg2 (\4\:A \2\:A) resistor r=10.7763 c=0 +rg3 (\4\:A \5\:A) resistor r=56.5484 c=0 +rg4 (\6\:Ai \5\:Ai) resistor r=438.925 c=0 +rg5 (\5\:Ai \7\:Ai) resistor r=89.7447 c=0 +rg6 (\8\:A \9\:A) resistor r=257.237 c=0 +rg7 (\9\:A \6\:A) resistor r=27.4119 c=0 +rg8 (\9\:A \10\:A) resistor r=53.5985 c=0 +rg9 (Bi \2\:Bi) resistor r=2.0523 c=0 +rg10 (\2\:Bi \3\:Bi) resistor r=38.5093 c=0 +rg11 (\2\:Bi \4\:Bi) resistor r=170.801 c=0 +rg12 (\1\:B \2\:B) resistor r=7.3761 c=0 +rg13 (\2\:B \3\:B) resistor r=170.445 c=0 +rg14 (\3\:B \4\:B) resistor r=337.766 c=0 +rg15 (\4\:B \5\:B) resistor r=299.266 c=0 +rg16 (\2\:B \6\:B) resistor r=38.7782 c=0 +MP5 (\1\:vdd! \3\:B \7\:Bi vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP4 (Ai \3\:A \7\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MP0 (net8 \7\:Ai \9\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\6\:Out \4\:B net8 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP3 (net022 \8\:A \4\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP2 (\8\:vdd! \4\:Bi net022 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN5 (\1\:gnd! \6\:B \5\:Bi 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN4 (\3\:Ai \5\:A \9\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN3 (net17 \5\:B \8\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\5\:Out \10\:A net17 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net32 \6\:Ai \1\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\7\:gnd! \3\:Bi net32 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..96a7d902865df35ee9e09f8596ee23618bb7a2b3 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 03:28:00 2021 +// Design library name: multiplier_low +// Design cell name: xor2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..16718829bd883ee89d557fccc785808e017d32e8 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre8_6429_16 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..7413b1aa1770672a025b4e56e89d6883dc9ce092 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "xor2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/si.foregnd.log b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/si.foregnd.log new file mode 100644 index 0000000000000000000000000000000000000000..3c0b21840923f4052da0bdf44cf7d0677b1ca0a2 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/si.foregnd.log @@ -0,0 +1,2 @@ +Begin Incremental Netlisting May 27 03:28:00 2021 +End netlisting May 27 03:28:00 2021 diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..7ecc5a5cfc934d7988bf27533b38483df8a3bbb9 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,95 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:28:01 AM, Thur May 27, 2021 +# Number of equations = 64 +1\:A 1.80000000000181 +1\:B 1.79999999998512 +1\:gnd! 6.843064099015e-13 +1\:Out 2.1594620062461e-08 +1\:vdd! 1.7999999999964 +2\:A 1.80000000000525 +2\:Ai -3.71005466904876e-10 +2\:B 1.79999999775067 +2\:Bi 8.18458581410074e-12 +2\:gnd! 1.6160341638324e-12 +2\:Out 2.15750313097916e-08 +2\:vdd! 1.79999999999984 +3\:A 1.80000005136554 +3\:Ai -4.09031994705166e-10 +3\:B 1.79999994630651 +3\:Bi -2.89609607677241e-11 +3\:gnd! 1.83914147915663e-12 +3\:Out 2.15831932521957e-08 +3\:vdd! 1.79999999999918 +4\:A 1.80000000545208 +4\:Ai 1.42992206928093e-10 +4\:B 1.79999984057645 +4\:Bi -2.30187251837093e-09 +4\:gnd! 6.86622957282443e-13 +4\:Out 2.15434574990661e-08 +4\:vdd! 1.79999999999968 +5\:A 1.80000001699586 +5\:Ai 1.55127938023479e-10 +5\:B 1.79999973956689 +5\:Bi 4.57833690733147e-11 +5\:gnd! 1.84049616806727e-10 +5\:Out 2.23607781446678e-08 +5\:vdd! 1.79999999999611 +6\:A 1.79999999986161 +6\:Ai 2.22020214574674e-08 +6\:B 1.79999999770768 +6\:Bi 4.39923183744221e-11 +6\:gnd! 1.61906077085763e-10 +6\:Out 2.15945483168031e-08 +6\:vdd! 1.79999999999573 +7\:A 1.79999999986182 +7\:Ai 6.70322338480578e-09 +7\:Bi 4.94109183640527e-11 +7\:gnd! 6.82175521621078e-12 +7\:vdd! 1.79999999995271 +8\:A 1.80000008038032 +8\:gnd! 7.78365389160918e-10 +8\:vdd! 1.79999999999476 +9\:A 1.79999999903708 +9\:gnd! 1.10176715254172e-10 +9\:vdd! 1.79999999996982 +10\:A 1.799999980476 +A 1.8 +Ai -4.0066354298738e-10 +B 1.8 +Bi 3.7921246492103e-11 +gnd! 0 +MN0:int_d 1.12047776827371 +MN0:int_s 2.16476722841242e-08 +MN1:int_d 2.88229067824239e-11 +MN1:int_s 1.12047776830149 +MN2:int_d 2.44359654558179e-08 +MN2:int_s 5.08281793346266e-07 +MN3:int_d 5.0807496365938e-07 +MN3:int_s 2.95393992189589e-09 +MN4:int_d -5.13113619661685e-10 +MN4:int_s -9.75717258365543e-11 +MN5:int_d -2.85047864183367e-12 +MN5:int_s 6.03447568692007e-11 +MP0:int_d 1.79999998134377 +MP0:int_s 1.79999999989167 +MP1:int_d 2.16280344790694e-08 +MP1:int_s 1.79999998134917 +MP2:int_d 1.79999999997885 +MP2:int_s 1.79999999126692 +MP3:int_d 1.7999999910747 +MP3:int_s 2.14502315662289e-08 +MP4:int_d -4.89898038513508e-10 +MP4:int_s 1.79999999981184 +MP5:int_d 1.7999999999846 +MP5:int_s 5.79413479968001e-11 +net8 1.79999998134647 +net17 5.08178378502823e-07 +net022 1.79999999117081 +net32 1.1204777682876 +Out 1.54280882607325e-08 +v0:p -6.15145685657942e-10 +v1:p 4.7523373193936e-10 +v2:p 0 +v3:p -3.02933654902481e-10 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..7e957e932cd405efa38d8969fe95830f6f355d01 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,95 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:28:01 AM, Thur May 27, 2021 +# Number of equations = 64 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 3.36703285815914e-12 +1\:Out 1.17811095262107e-08 +1\:vdd! 1.79999999999796 +2\:A 1.8 +2\:Ai 2.9497936821549e-09 +2\:B 1.8 +2\:Bi 2.94622183211162e-09 +2\:gnd! 1.28514172926229e-12 +2\:Out 1.17811095269634e-08 +2\:vdd! 1.79999999999993 +3\:A 1.8 +3\:Ai 2.94690802586508e-09 +3\:B 1.8 +3\:Bi 2.94622183211162e-09 +3\:gnd! 7.86621492416421e-13 +3\:Out 1.17799786811327e-08 +3\:vdd! 1.79999999999965 +4\:A 1.8 +4\:Ai 2.94979368215489e-09 +4\:B 1.8 +4\:Bi 2.94622183211162e-09 +4\:gnd! 2.93676360142e-13 +4\:Out 1.17833754006443e-08 +4\:vdd! 1.79999999999986 +5\:A 1.8 +5\:Ai 2.94979368215489e-09 +5\:B 1.8 +5\:Bi 2.94525034486286e-09 +5\:gnd! 2.21616107119979e-12 +5\:Out 1.17740596270072e-08 +5\:vdd! 1.79999999999967 +6\:A 1.80000000000006 +6\:Ai 2.94979368215489e-09 +6\:B 1.8 +6\:Bi 2.94622183211162e-09 +6\:gnd! 3.0580237637966e-12 +6\:Out 1.17822473424376e-08 +6\:vdd! 1.7999999999998 +7\:A 1.80000000000006 +7\:Ai 2.94979368215489e-09 +7\:Bi 2.95047156614529e-09 +7\:gnd! 7.86622018746815e-13 +7\:vdd! 1.79999999999776 +8\:A 1.80000000000006 +8\:gnd! 6.531402370616e-12 +8\:vdd! 1.7999999999978 +9\:A 1.80000000000006 +9\:gnd! 5.02469306719741e-12 +9\:vdd! 1.79999999999742 +10\:A 1.80000000000006 +A 1.8 +Ai 2.95201727755065e-09 +B 1.8 +Bi 2.94622183211162e-09 +gnd! 0 +MN0:int_d -2.63267897631264e-08 +MN0:int_s 1.17811095241722e-08 +MN1:int_d 7.866243428031e-13 +MN1:int_s -2.63267897674158e-08 +MN2:int_d 1.17582630932342e-08 +MN2:int_s 5.90609201144538e-09 +MN3:int_d 5.87449894414211e-09 +MN3:int_s 2.23279359817434e-11 +MN4:int_d 2.93900975555002e-09 +MN4:int_s 1.29229633619798e-11 +MN5:int_d 1.12653031530144e-11 +MN5:int_s 2.93735207454775e-09 +MP0:int_d 1.79999998826053 +MP0:int_s 1.79999999999074 +MP1:int_d 1.17889376399578e-08 +MP1:int_s 1.79999998824717 +MP2:int_d 1.79999999999112 +MP2:int_s 1.79999998826091 +MP3:int_d 1.79999998824755 +MP3:int_s 1.17900656981645e-08 +MP4:int_d 2.95870757711165e-09 +MP4:int_s 1.79999999999108 +MP5:int_d 1.79999999999128 +MP5:int_s 2.95716186570632e-09 +net8 1.79999998825385 +net17 5.89029547779375e-09 +net022 1.79999998825423 +net32 -2.63267897652677e-08 +Out 1.17799786811327e-08 +v0:p -1.86129395935218e-11 +v1:p 1.37390099297368e-14 +v2:p 0 +v3:p -1.56125112837913e-18 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..2e465b2cc882fa8c86d0c8a1c25cb5560bba70d0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:27:59 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..5c83ac46a81ea02b88b01d41281e56dbcd909502 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:28:01 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..081e675aded771581bf4c27e1c0473c2df442492 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..e6bd67c674f1f6eeb2ecea7ffcb93571ffb08db9 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..d4fb7845a6528d5df244ffbbd5c3687aee43a007 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/logFile @@ -0,0 +1,105 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:28:01 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:28:01 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 30 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..034b8ba0ad6e0d1ffc96b4e514e316bfdaa3b338 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..d9c892a57eb9aa0494581dbd96e4976d284ffe6c Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..49f47e4b2989e9f592816fe347e839de15f6408b --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:28:01 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..4aed00fd9d420d7a319dbc43eb8e4fbcd2bdee3a --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 03:28:01 2021" +"simulator" "spectre" +"date" "May 27 03:28:01 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..ec5d22b84076871643894358167d1703a5571ee4 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"xor2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 03:27:59 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..f3cbe33dd3ea718dd0b0162e3aaad122c1548d9d --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,262 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 60859 +Memory available: 1.3561 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 1200.0 37.1 + 1 0 1 2201.0 42.5 + 2 0 2 1200.0 30.6 + 3 0 3 2201.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 1200.0 41.9 + 12 1 2 2201.0 29.6 + 13 1 3 2201.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 2201.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 2201.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 1200.0 6.1 + 34 1 4 1200.0 4.3 + 35 1 8 1200.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 3:28:01 AM, Thur May 27, 2021 (process id: 60859). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C2/xor2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre8_6429_16 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 60859 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C2/xor2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_XOR_C2.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 65.99 ms, elapsed = 111.915 ms. +Time accumulated: CPU = 93.985 ms, elapsed = 111.92 ms. +Peak resident memory used = 38.8 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 24.996 ms, elapsed = 25.1999 ms. +Time accumulated: CPU = 118.981 ms, elapsed = 137.28 ms. +Peak resident memory used = 43.8 Mbytes. + +Time for EDB Visiting: CPU = 999 us, elapsed = 974.894 us. +Time accumulated: CPU = 120.98 ms, elapsed = 138.433 ms. +Peak resident memory used = 44.3 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 63 + bsim3v3 12 + capacitor 1 + resistor 54 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 3 ms, elapsed = 142.259 ms. +Time accumulated: CPU = 123.98 ms, elapsed = 280.849 ms. +Peak resident memory used = 45.3 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre8_6429_16, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 30 ns) +************************************************ +DC simulation time: CPU = 1 ms, elapsed = 912.905 us. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 30 ns + step = 30 ps + maxstep = 600 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 63 (voltage) + others 1 + + tran: time = 930 ps (3.1 %), step = 480 ps (1.6 %) + +Notice from spectre at time = 1.8825 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. +Notice from spectre at time = 2 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. + + tran: time = 2.264 ns (7.55 %), step = 14.43 ps (48.1 m%) + tran: time = 3.859 ns (12.9 %), step = 209.7 ps (699 m%) + tran: time = 5.548 ns (18.5 %), step = 459.6 ps (1.53 %) + tran: time = 7.18 ns (23.9 %), step = 600 ps (2 %) + +Notice from spectre at time = 7.98996 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:Ai. +Notice from spectre at time = 8.09498 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:Ai. +Notice from spectre at time = 8.2 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:Ai. + Further occurrences of this notice will be suppressed. + + tran: time = 8.26 ns (27.5 %), step = 19.81 ps (66 m%) + tran: time = 9.777 ns (32.6 %), step = 165.4 ps (551 m%) + tran: time = 11.79 ns (39.3 %), step = 600 ps (2 %) + tran: time = 12.99 ns (43.3 %), step = 600 ps (2 %) + tran: time = 14.79 ns (49.3 %), step = 600 ps (2 %) + tran: time = 15.99 ns (53.3 %), step = 600 ps (2 %) + tran: time = 17.79 ns (59.3 %), step = 600 ps (2 %) + tran: time = 18.99 ns (63.3 %), step = 600 ps (2 %) + tran: time = 20.79 ns (69.3 %), step = 600 ps (2 %) + tran: time = 21.99 ns (73.3 %), step = 600 ps (2 %) + tran: time = 23.79 ns (79.3 %), step = 600 ps (2 %) + tran: time = 24.99 ns (83.3 %), step = 600 ps (2 %) + tran: time = 26.79 ns (89.3 %), step = 600 ps (2 %) + tran: time = 27.99 ns (93.3 %), step = 600 ps (2 %) + tran: time = 29.6 ns (98.7 %), step = 404.7 ps (1.35 %) +Number of accepted tran steps = 137 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 1 ms, elapsed = 972.033 us. +Intrinsic tran analysis time: CPU = 24.997 ms, elapsed = 179.176 ms. +Total time required for tran analysis `tran': CPU = 27.996 ms, elapsed = 182.114 ms. +Time accumulated: CPU = 156.975 ms, elapsed = 762.859 ms. +Peak resident memory used = 47.5 Mbytes. + + +Notice from spectre. + 26 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. + +Aggregate audit (3:28:06 AM, Thur May 27, 2021): +Time used: CPU = 239 ms, elapsed = 5.83 s, util. = 4.1%. +Time spent in licensing: elapsed = 60.2 ms. +Peak memory used = 47.7 Mbytes. +Simulation started at: 3:28:01 AM, Thur May 27, 2021, ended at: 3:28:06 AM, Thur May 27, 2021, with elapsed time (wall clock): 5.83 s. +spectre completes with 0 errors, 3 warnings, and 8 notices. diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..ec1fcc26c3d069e46af91255981b3529198702bd --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:28:01 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..1dd0ff237805fd06271c22d6f5caa79a44ba314b Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp new file mode 100644 index 0000000000000000000000000000000000000000..9ff29d99f45ed115f2df6912d4432fc61a52c48f --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp @@ -0,0 +1,151 @@ +*cdnsheobpacket 26 1 +*cdnshlastgoodpoint 26 0,0 +*cdnshnumflushes 26 0 +*cdnshnxdbpid 26 60859 +*cdnshrunkey 26 -1 +*cdnshserieskey 26 -1 +*cdnshsweepcount 26 0 +*cdnshsweepprecision 26 -1 +*cdnshsweeprange 26 0,0 +*cdnshsweepstoptime 26 -1 +*cdnshtimestamp 26 6388133861622057281 +*cdnshuuid 26 22425311018515913759197818197952555615373-3638739981-31622057281-3-862636253-7-367536670536657513 +:pwr 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 0 W 0 +A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 53 V 0 +Ai 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 54 V 0 +B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 55 V 0 +Bi 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 56 V 0 +Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 62 V 0 +\10\:A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 52 V 0 +\1\:A 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 1 V 0 +\1\:B 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 2 V 0 +\1\:Out 0 1 -1 1.7976931348623157081e+308 -1.7976931348623157081e+308 1.7976931348623157081e+308 -1.7976931348623157081e+308 0 4 V 0 +\1\:gnd! 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0 1 912 0 2.9999999999999997319e-08 1.8000000000000000444 1.8000000000000000444 138 67 V 0 +­¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬*cdnstlastgoodpoint 26 2.9999999999999997319e-08,77744 +­­¨©|147988880|­­¨© 0 0 0 912 147844240 :pwr 0 1 912 0 2.9999999999999997319e-08 2.0491492893634245014e-11 0.00054419146966155126227 138 0 W 0 +­­¨©|147989744|­­¨© 0 0 0 912 147844240 \1\:A 0 1 912 0 2.9999999999999997319e-08 -1.7184862409011087718e-09 1.8000000070050783396 138 1 V 0 +­­¨©|147990320|­­¨© 0 0 0 912 147844240 \1\:B 0 1 912 0 2.9999999999999997319e-08 1.7999999460537419171 1.8000000805474645205 138 2 V 0 +­­¨©|147991040|­­¨© 0 0 0 912 147844240 \1\:gnd! 0 1 912 0 2.9999999999999997319e-08 -1.741747030877559077e-06 3.7140802603747078006e-07 138 3 V 0 +­­¨©|147991984|­­¨© 0 0 0 912 147844240 \1\:Out 0 1 912 0 2.9999999999999997319e-08 -0.0053979191714222584872 1.8048773364492627369 138 4 V 0 +­­¨©|147992736|­­¨© 0 0 0 912 147844240 \1\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999999858572630629 1.8000000145680672414 138 5 V 0 +­­¨©|147993456|­­¨© 0 0 0 912 147844240 \2\:A 0 1 912 0 2.9999999999999997319e-08 -3.6609705186509849133e-09 1.8000000127324160548 138 6 V 0 +­­¨©|147994176|­­¨© 0 0 0 912 147844240 \2\:Ai 0 1 912 0 2.9999999999999997319e-08 -0.0075041525471415395851 1.8263913145721886178 138 7 V 0 +­­¨©|147994896|­­¨© 0 0 0 912 147844240 \2\:B 0 1 912 0 2.9999999999999997319e-08 1.7999918468680338179 1.8000121734876950441 138 8 V 0 +­­¨©|147995760|­­¨© 0 0 0 912 147844240 \2\:Bi 0 1 912 0 2.9999999999999997319e-08 -0.0015244818394082048935 0.00033470582367589054272 138 9 V 0 +­­¨©|147996480|­­¨© 0 0 0 912 147844240 \2\:gnd! 0 1 912 0 2.9999999999999997319e-08 -6.6556348702853551617e-07 1.4104059412368198585e-07 138 10 V 0 +­­¨©|147997200|­­¨© 0 0 0 912 147844240 \2\:Out 0 1 912 0 2.9999999999999997319e-08 -0.0053980340359101493253 1.8048775268221917134 138 11 V 0 +­­¨©|147997920|­­¨© 0 0 0 912 147844240 \2\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999982560514644625 1.8000001078946787914 138 12 V 0 +­­¨©|147998640|­­¨© 0 0 0 912 147844240 \3\:A 0 1 912 0 2.9999999999999997319e-08 -3.4989541544655825521e-05 1.800108582416423797 138 13 V 0 +­­¨©|147999360|­­¨© 0 0 0 912 147844240 \3\:Ai 0 1 912 0 2.9999999999999997319e-08 -0.0075026870440751698005 1.8263923174254583781 138 14 V 0 +­­¨©|148000080|­­¨© 0 0 0 912 147844240 \3\:B 0 1 912 0 2.9999999999999997319e-08 1.7998047387540827557 1.8002832431200708196 138 15 V 0 +­­¨©|148000800|­­¨© 0 0 0 912 147844240 \3\:Bi 0 1 912 0 2.9999999999999997319e-08 -0.0015214788955961522973 0.00033622594450212088318 138 16 V 0 +­­¨©|148001584|­­¨© 0 0 0 912 147844240 \3\:gnd! 0 1 912 0 2.9999999999999997319e-08 -4.0786544138024213409e-07 8.5877850440688142552e-08 138 17 V 0 +­­¨©|148002304|­­¨© 0 0 0 912 147844240 \3\:Out 0 1 912 0 2.9999999999999997319e-08 -0.0053987800398018750622 1.8048749562388062273 138 18 V 0 +­­¨©|148003024|­­¨© 0 0 0 912 147844240 \3\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999911505808112722 1.8000005474962259555 138 19 V 0 +­­¨©|148004016|­­¨© 0 0 0 912 147844240 \4\:A 0 1 912 0 2.9999999999999997319e-08 -3.3995527078499256676e-06 1.8000107294098075528 138 20 V 0 +­­¨©|148004720|­­¨© 0 0 0 912 147844240 \4\:Ai 0 1 912 0 2.9999999999999997319e-08 -0.007502860966846855266 1.8263890633589521251 138 21 V 0 +­­¨©|148005440|­­¨© 0 0 0 912 147844240 \4\:B 0 1 912 0 2.9999999999999997319e-08 1.7994336498350063103 1.8008484584813988505 138 22 V 0 +­­¨©|148006160|­­¨© 0 0 0 912 147844240 \4\:Bi 0 1 912 0 2.9999999999999997319e-08 -0.0019624396123359070902 0.00039258008441627855866 138 23 V 0 +­­¨©|148006880|­­¨© 0 0 0 912 147844240 \4\:gnd! 0 1 912 0 2.9999999999999997319e-08 -1.5227201316901014769e-07 3.206153757223966413e-08 138 24 V 0 +­­¨©|148007600|­­¨© 0 0 0 912 147844240 \4\:Out 0 1 912 0 2.9999999999999997319e-08 -0.005396628515206516874 1.8048828254068165489 138 25 V 0 +­­¨©|148008320|­­¨© 0 0 0 912 147844240 \4\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999965489643761085 1.8000002135088120081 138 26 V 0 +­­¨©|148009040|­­¨© 0 0 0 912 147844240 \5\:A 0 1 912 0 2.9999999999999997319e-08 -9.5065896992284877414e-06 1.8000382915805070994 138 27 V 0 +­­¨©|148009888|­­¨© 0 0 0 912 147844240 \5\:Ai 0 1 912 0 2.9999999999999997319e-08 -0.0075028304720179050599 1.826389010206730168 138 28 V 0 +­­¨©|148010800|­­¨© 0 0 0 912 147844240 \5\:B 0 1 912 0 2.9999999999999997319e-08 1.7992512211202571493 1.8014238371935171745 138 29 V 0 +­­¨©|148011712|­­¨© 0 0 0 912 147844240 \5\:Bi 0 1 912 0 2.9999999999999997319e-08 -0.0015178277270905451285 0.00033368163536536357174 138 30 V 0 +­­¨©|148012624|­­¨© 0 0 0 912 147844240 \5\:gnd! 0 1 912 0 2.9999999999999997319e-08 -3.8450986465170443682e-06 7.3839295372316255187e-05 138 31 V 0 +­­¨©|148013536|­­¨© 0 0 0 912 147844240 \5\:Out 0 1 912 0 2.9999999999999997319e-08 -0.0054027902334065468909 1.8048706149666837728 138 32 V 0 +­­¨©|148014768|­­¨© 0 0 0 912 147844240 \5\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999961172542946475 1.8000021162947918985 138 33 V 0 +­­¨©|148015616|­­¨© 0 0 0 912 147844240 \6\:A 0 1 912 0 2.9999999999999997319e-08 -1.4632828444998899342e-05 1.8000046684388932849 138 34 V 0 +­­¨©|148016528|­­¨© 0 0 0 912 147844240 \6\:Ai 0 1 912 0 2.9999999999999997319e-08 -0.0074688284735453473046 1.8262741875922319235 138 35 V 0 +­­¨©|148017440|­­¨© 0 0 0 912 147844240 \6\:B 0 1 912 0 2.9999999999999997319e-08 1.7999918364565401507 1.8000141253440191669 138 36 V 0 +­­¨©|148018352|­­¨© 0 0 0 912 147844240 \6\:Bi 0 1 912 0 2.9999999999999997319e-08 -0.0015183415339091311906 0.00033377089526291219565 138 37 V 0 +­­¨©|148019264|­­¨© 0 0 0 912 147844240 \6\:gnd! 0 1 912 0 2.9999999999999997319e-08 -6.9895505439343084901e-06 0.00012016729241022265271 138 38 V 0 +­­¨©|148020176|­­¨© 0 0 0 912 147844240 \6\:Out 0 1 912 0 2.9999999999999997319e-08 -0.005398741798788966699 1.804874913727085195 138 39 V 0 +­­¨©|148021088|­­¨© 0 0 0 912 147844240 \6\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999923699040050185 1.8000008003275704827 138 40 V 0 +­­¨©|148022000|­­¨© 0 0 0 912 147844240 \7\:A 0 1 912 0 2.9999999999999997319e-08 -1.4610519952284323209e-05 1.800004661348323598 138 41 V 0 +­­¨©|148022912|­­¨© 0 0 0 912 147844240 \7\:Ai 0 1 912 0 2.9999999999999997319e-08 -0.0074820012467238117965 1.8263640645845131694 138 42 V 0 +­­¨©|148023824|­­¨© 0 0 0 912 147844240 \7\:Bi 0 1 912 0 2.9999999999999997319e-08 -0.0015183164566653457525 0.00033381531509596944597 138 43 V 0 +­­¨©|148024736|­­¨© 0 0 0 912 147844240 \7\:gnd! 0 1 912 0 2.9999999999999997319e-08 -4.106862603737170963e-07 8.323070184669840889e-08 138 44 V 0 +­­¨©|148025648|­­¨© 0 0 0 912 147844240 \7\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999154039356888291 1.8000088733565959842 138 45 V 0 +­­¨©|148026560|­­¨© 0 0 0 912 147844240 \8\:A 0 1 912 0 2.9999999999999997319e-08 -0.00092965432469565862511 1.8000844584346180621 138 46 V 0 +­­¨©|148027472|­­¨© 0 0 0 912 147844240 \8\:gnd! 0 1 912 0 2.9999999999999997319e-08 -7.0167291569107835864e-06 0.00020599642135748607707 138 47 V 0 +­­¨©|148028384|­­¨© 0 0 0 912 147844240 \8\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999437296940292708 1.8000034813335747952 138 48 V 0 +­­¨©|148029296|­­¨© 0 0 0 912 147844240 \9\:A 0 1 912 0 2.9999999999999997319e-08 -0.00010092013921130481291 1.8000320941467795599 138 49 V 0 +­­¨©|148030208|­­¨© 0 0 0 912 147844240 \9\:gnd! 0 1 912 0 2.9999999999999997319e-08 -1.4335281714887553462e-05 0.00022839378880175565051 138 50 V 0 +­­¨©|148031120|­­¨© 0 0 0 912 147844240 \9\:vdd! 0 1 912 0 2.9999999999999997319e-08 1.7999698774602073126 1.8000164183232498782 138 51 V 0 +­­¨©|148032496|­­¨© 0 0 0 912 147844240 \10\:A 0 1 912 0 2.9999999999999997319e-08 -9.6960771865665235092e-05 1.8000826231987605563 138 52 V 0 +­­¨©|148033376|­­¨© 0 0 0 912 147844240 A 0 1 912 0 2.9999999999999997319e-08 0 1.8000000000000000444 138 53 V 0 +­­¨©|148034288|­­¨© 0 0 0 912 147844240 Ai 0 1 912 0 2.9999999999999997319e-08 -0.0075054299731885203151 1.8263908000394271092 138 54 V 0 +­­¨©|148035200|­­¨© 0 0 0 912 147844240 B 0 1 912 0 2.9999999999999997319e-08 1.8000000000000000444 1.8000000000000000444 138 55 V 0 +­­¨©|148036112|­­¨© 0 0 0 912 147844240 Bi 0 1 912 0 2.9999999999999997319e-08 -0.001519382600555880744 0.00033392940900265965587 138 56 V 0 +­­¨©|148037024|­­¨© 0 0 0 912 147844240 gnd! 0 1 912 0 2.9999999999999997319e-08 0 0 138 57 V 0 +­­¨©|148037936|­­¨© 0 0 0 912 147844240 net8 0 1 912 0 2.9999999999999997319e-08 1.7562266198368121639 1.928142500898402556 138 58 V 0 +­­¨©|148038848|­­¨© 0 0 0 912 147844240 net17 0 1 912 0 2.9999999999999997319e-08 -0.0049209898176668835992 0.31268842416875181067 138 59 V 0 +­­¨©|148039760|­­¨© 0 0 0 912 147844240 net022 0 1 912 0 2.9999999999999997319e-08 1.4349200549152092421 1.818052931034108477 138 60 V 0 +­­¨©|148040672|­­¨© 0 0 0 912 147844240 net32 0 1 912 0 2.9999999999999997319e-08 -0.00041130781475679233138 1.2508670368713401544 138 61 V 0 +­­¨©|148041584|­­¨© 0 0 0 912 147844240 Out 0 1 912 0 2.9999999999999997319e-08 -0.0053827508228137966456 1.8048563503495356208 138 62 V 0 +­­¨©|148042496|­­¨© 0 0 0 912 147844240 v0:p 0 1 912 0 2.9999999999999997319e-08 -0.00021946659747740411561 2.6755134827437318122e-05 138 63 A 0 +­­¨©|148043408|­­¨© 0 0 0 912 147844240 v1:p 0 1 912 0 2.9999999999999997319e-08 -7.6392516310826513661e-05 6.236168713049126738e-05 138 64 A 0 +­­¨©|148044944|­­¨© 0 0 0 912 147844240 v2:p 0 1 912 0 2.9999999999999997319e-08 0 0 138 65 A 0 +­­¨©|148045744|­­¨© 0 0 0 912 147844240 v3:p 0 1 912 0 2.9999999999999997319e-08 -1.0980309006857368853e-06 1.6394761746864665282e-06 138 66 A 0 +­­¨©|148046656|­­¨© 0 0 0 912 147844240 vdd! 0 1 912 0 2.9999999999999997319e-08 1.8000000000000000444 1.8000000000000000444 138 67 V 0 +­­¨ª|1|­­¨ª 0 0 0 77168 0 RootScope 68 68 0 0 0 0 0 0 <> +­­¨ª|147844240|­­¨ª 0 0 0 77168 0 RootScope 68 68 0 0 0 0 0 0 <> diff --git a/Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/psf/tran.tran.sig.tmp b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran.sig.tmp similarity index 100% rename from Design/simulation/ADE_output/nand2_C2/nand2/spectre/extracted/psf/tran.tran.sig.tmp rename to involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/tran.tran.sig.tmp diff --git a/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/variables_file b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/variables_file new file mode 100644 index 0000000000000000000000000000000000000000..9cd0d9a44d5b48993a18a27e48a7877f892646bb --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C2/xor2/spectre/av_extracted/psf/variables_file @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"Time Stamp" "May 27 03:27:59 2021" +TYPE +"variable" STRUCT( +"value" FLOAT DOUBLE +) PROP( "key" "element" ) +VALUE +"temp" "variable" ( 27 ) PROP( ) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/.control b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/.control new file mode 100755 index 0000000000000000000000000000000000000000..1beb90f7f38f765096259ec214ede2192c8d975e --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/.control @@ -0,0 +1,4 @@ + #!/bin/sh +xargs cat > netlist <" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapNetInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstFirstChar = '( + ( "!" "\\!" ) + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( "0" "_0" ) + ( "1" "_1" ) + ( "2" "_2" ) + ( "3" "_3" ) + ( "4" "_4" ) + ( "5" "_5" ) + ( "6" "_6" ) + ( "7" "_7" ) + ( "8" "_8" ) + ( "9" "_9" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "\\<" ) + ( "=" "\\=" ) + ( ">" "\\>" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapInstInName = '( + ( "\"" "\\\"" ) + ( "#" "\\#" ) + ( "$" "\\$" ) + ( "%" "\\%" ) + ( "&" "\\&" ) + ( "'" "\\'" ) + ( "(" "\\(" ) + ( ")" "\\)" ) + ( "*" "\\*" ) + ( "+" "\\+" ) + ( "," "\\," ) + ( "-" "\\-" ) + ( "." "_" ) + ( "/" "\\/" ) + ( ":" "\\:" ) + ( ";" "\\;" ) + ( "<" "_" ) + ( "=" "\\=" ) + ( ">" ) + ( "?" "\\?" ) + ( "@" "\\@" ) + ( "[" "\\[" ) + ( "\\" "\\\\" ) + ( "]" "\\]" ) + ( "^" "\\^" ) + ( "`" "\\`" ) + ( "{" "\\{" ) + ( "|" "\\|" ) + ( "}" "\\}" ) + ( "~" "\\~" ) + ) +hnlLastMapModelFirstChar = '( + "!" + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + "0" + "1" + "2" + "3" + "4" + "5" + "6" + "7" + "8" + "9" + ":" + ";" + "<" + "=" + ">" + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastMapModelInName = '( + "\"" + "#" + "$" + "%" + "&" + "'" + "(" + ")" + "*" + "+" + "," + "-" + "." + "/" + ":" + ";" + ( "<" "_" ) + "=" + ( ">" ) + "?" + "@" + "[" + "\\" + "]" + "^" + "`" + "{" + "|" + "}" + "~" + ) +hnlLastInvalidNetNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "gnd!" "0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "0" "_0" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidInstNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidModelNames = '( + ( "pow" ) + ( "paramset" ) + ( "log10" ) + ( "P_CELSIUS0" ) + ( "protect" ) + ( "temp" ) + ( "tan" ) + ( "fmod" ) + ( "altergroup" ) + ( "correlate" ) + ( "asinh" ) + ( "PROTECT" ) + ( "scale" ) + ( "if" ) + ( "march" ) + ( "return" ) + ( "process" ) + ( "save" ) + ( "ends" ) + ( "truncate" ) + ( "M_PI" ) + ( "subckt" ) + ( "acosh" ) + ( "M_SQRT2" ) + ( "analogmodel" ) + ( "end" ) + ( "global" ) + ( "int" ) + ( "M_2_SQRTPI" ) + ( "M_LOG2E" ) + ( "asin" ) + ( "pwr" ) + ( "tnom" ) + ( "log" ) + ( "M_LOG10E" ) + ( "M_PI_2" ) + ( "ic" ) + ( "sinh" ) + ( "cos" ) + ( "print" ) + ( "P_H" ) + ( "atan2" ) + ( "library" ) + ( "hypot" ) + ( "atan" ) + ( "M_2_PI" ) + ( "sin" ) + ( "calculate" ) + ( "PROT" ) + ( "P_U0" ) + ( "else" ) + ( "ceil" ) + ( "parameters" ) + ( "mismatch" ) + ( "to" ) + ( "acos" ) + ( "P_C" ) + ( "M_DEGPERRAD" ) + ( "statistics" ) + ( "nodeset" ) + ( "M_E" ) + ( "plot" ) + ( "input" ) + ( "function" ) + ( "output" ) + ( "P_K" ) + ( "sens" ) + ( "floor" ) + ( "min" ) + ( "vary" ) + ( "P_Q" ) + ( "export" ) + ( "M_TWO_PI" ) + ( "sqrt" ) + ( "M_SQRT1_2" ) + ( "P_EPS0" ) + ( "M_LN10" ) + ( "montecarlo" ) + ( "max" ) + ( "abs" ) + ( "local" ) + ( "tanh" ) + ( "integer" ) + ( "exp" ) + ( "prot" ) + ( "endfunction" ) + ( "inline" ) + ( "cosh" ) + ( "atanh" ) + ( "real" ) + ( "M_1_PI" ) + ( "FUNCTION" ) + ( "model" ) + ( "M_PI_4" ) + ( "for" ) + ( "M_LN2" ) + ( "scalem" ) + ) +hnlLastInvalidParamNames = '( + ( "pwl" ) + ( "node" ) + ( "fmod" ) + ( "trap" ) + ( "inst" ) + ( "only" ) + ( "gear2" ) + ( "euler" ) + ( "spice2" ) + ( "suggest" ) + ( "if" ) + ( "scale" ) + ( "pnpv" ) + ( "process" ) + ( "terminals" ) + ( "save" ) + ( "spice" ) + ( "sweep" ) + ( "awb" ) + ( "waveless" ) + ( "brk" ) + ( "z" ) + ( "normal" ) + ( "n" ) + ( "cos" ) + ( "sinh" ) + ( "yang" ) + ( "max_only" ) + ( "calculate" ) + ( "spice3" ) + ( "source" ) + ( "to" ) + ( "acos" ) + ( "allglobal" ) + ( "absout" ) + ( "bsim" ) + ( "moderate" ) + ( "function" ) + ( "rawfile" ) + ( "sens" ) + ( "floor" ) + ( "npn" ) + ( "lvlpub" ) + ( "steps" ) + ( "correlations" ) + ( "dc" ) + ( "relative" ) + ( "montecarlo" ) + ( "abs" ) + ( "fatal" ) + ( "local" ) + ( "tanh" ) + ( "autodc" ) + ( "endfunction" ) + ( "prot" ) + ( "atanh" ) + ( "bulk" ) + ( "rampup" ) + ( "for" ) + ( "trapgear2" ) + ( "pow" ) + ( "max_v_only" ) + ( "nutascii" ) + ( "wsfbin" ) + ( "child" ) + ( "models" ) + ( "subth" ) + ( "nonlinear" ) + ( "altergroup" ) + ( "logfile" ) + ( "screen" ) + ( "sat" ) + ( "forward" ) + ( "p" ) + ( "sum" ) + ( "in" ) + ( "alllocal" ) + ( "dev" ) + ( "warning" ) + ( "title" ) + ( "parent" ) + ( "int" ) + ( "isdb" ) + ( "float" ) + ( "log" ) + ( "spectre" ) + ( "ic" ) + ( "std" ) + ( "atan2" ) + ( "nodes" ) + ( "atan" ) + ( "subthresh" ) + ( "PROT" ) + ( "else" ) + ( "ceil" ) + ( "mismatch" ) + ( "parameters" ) + ( "lvl" ) + ( "on" ) + ( "export" ) + ( "overlap" ) + ( "exp" ) + ( "inline" ) + ( "insist" ) + ( "yes" ) + ( "continue" ) + ( "log10" ) + ( "out" ) + ( "temp" ) + ( "protect" ) + ( "poly" ) + ( "correlate" ) + ( "timedomain" ) + ( "hspice" ) + ( "brief" ) + ( "march" ) + ( "return" ) + ( "detailed" ) + ( "finish" ) + ( "nutbin" ) + ( "none" ) + ( "error" ) + ( "sine" ) + ( "all" ) + ( "wsfascii" ) + ( "end" ) + ( "analogmodel" ) + ( "cdsspice" ) + ( "oppoint" ) + ( "global" ) + ( "dptran" ) + ( "both" ) + ( "turbo" ) + ( "asin" ) + ( "gear2only" ) + ( "delta" ) + ( "tc" ) + ( "gnd" ) + ( "library" ) + ( "hypot" ) + ( "sin" ) + ( "pointlocal" ) + ( "diff" ) + ( "meyer" ) + ( "off" ) + ( "min" ) + ( "vary" ) + ( "vt" ) + ( "vertical" ) + ( "sqrt" ) + ( "gmin" ) + ( "indifferent" ) + ( "lateral" ) + ( "nodes_and_terminals" ) + ( "cosh" ) + ( "pnpl" ) + ( "real" ) + ( "fwd" ) + ( "model" ) + ( "FUNCTION" ) + ( "eng" ) + ( "liberal" ) + ( "bilinear" ) + ( "paramset" ) + ( "tan" ) + ( "asinh" ) + ( "status" ) + ( "PROTECT" ) + ( "psfascii" ) + ( "ends" ) + ( "truncate" ) + ( "subckt" ) + ( "acosh" ) + ( "traponly" ) + ( "pulse" ) + ( "file" ) + ( "override" ) + ( "breakdown" ) + ( "psfbin" ) + ( "allpub" ) + ( "tnom" ) + ( "pwr" ) + ( "full" ) + ( "debug" ) + ( "sigglobal" ) + ( "print" ) + ( "spiceplus" ) + ( "inversez" ) + ( "ptran" ) + ( "quit" ) + ( "tabular" ) + ( "nodeset" ) + ( "statistics" ) + ( "pnp" ) + ( "rev" ) + ( "sci" ) + ( "sources" ) + ( "plot" ) + ( "input" ) + ( "no" ) + ( "output" ) + ( "bert" ) + ( "backward" ) + ( "list" ) + ( "conservative" ) + ( "max" ) + ( "triode" ) + ( "absin" ) + ( "absolute" ) + ( "selected" ) + ( "integer" ) + ( "nowhere" ) + ( "npnv" ) + ( "scalem" ) + ) +hnlLastInstNameDifferentFrom = '( ) +hnlLastModelNameDifferentFrom = '( ) +hnlLastNetNameDifferentFrom = '( ) +hnlLastTermNameDifferentFrom = '( ) +hnlLastParamNameDifferentFrom = '( ) +hnlLastLibInfo = '( + ( "multiplier_low" "1622009074" ) + ) +hnlLastConstants = '( + "P_CELSIUS0" + "M_PI" + "M_SQRT2" + "M_2_SQRTPI" + "M_LOG2E" + "M_LOG10E" + "M_PI_2" + "P_H" + "M_2_PI" + "P_U0" + "P_C" + "M_DEGPERRAD" + "M_E" + "P_K" + "P_Q" + "M_TWO_PI" + "M_SQRT1_2" + "P_EPS0" + "M_LN10" + "M_1_PI" + "M_PI_4" + "M_LN2" + ) +hnlLastDesignVars = '( ) diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/ihnl/globalmap b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/ihnl/globalmap new file mode 100644 index 0000000000000000000000000000000000000000..08a08705c73dbbbfae0ef256b60d7d4a79b29fac --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/ihnl/globalmap @@ -0,0 +1,10 @@ +CADENCE IHNL01070 +$model +multiplier_low/xor2/av_extracted xor2 +$endmodel +$net +gnd! 0 +vdd! vdd! +$endnet +$param +$endparam diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/input.scllog b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/input.scllog new file mode 100644 index 0000000000000000000000000000000000000000..43ac06e8413ca839f34d12d758a70f0e589710cd --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/input.scllog @@ -0,0 +1,5 @@ +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Simulating `input.scs' on serveric3 at 3:31:17 AM, Thur May 27, 2021 (process id: 83857). +H = mpsImport( "spectre" "ipi" "v0.0" ?session "spectre8_6429_19" ) +H->sclSetResultDir( "../psf" ) diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/input.scs b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/input.scs new file mode 100644 index 0000000000000000000000000000000000000000..f3044cfbddba3e673fcc98f44a516fe7f39fda27 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/input.scs @@ -0,0 +1,105 @@ +// Generated for: spectre +// Generated on: May 27 03:31:12 2021 +// Design library name: multiplier_low +// Design cell name: xor2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! +include "/home/SME_VLSI/VLSI_57/306cadence/test_files/2_XOR_C3.input" +include "/home/SME_VLSI/306cadence/assuraTech/oa_2014/gpdk/../models/gpdk.scs" section=NN + +// Library name: multiplier_low +// Cell name: xor2 +// View name: av_extracted +re1 (\4\:Ai \2\:Ai) resistor r=4.1723 c=0 +re2 (\7\:A \1\:A) resistor r=4.652 c=0 +re3 (Out \3\:Out) resistor r=5.0851 c=0 +rf1 (\1\:A A) resistor r=0.003806 c=0 +rf2 (\1\:A \2\:A) resistor r=0.006818 c=0 +rf3 (Ai \2\:Ai) resistor r=0.4786 c=0 +rf4 (\2\:Ai \3\:Ai) resistor r=0.6211 c=0 +rf5 (\5\:Ai \4\:Ai) resistor r=0.09851 c=0 +rf6 (\6\:A \7\:A) resistor r=0.007087 c=0 +rf7 (\1\:Out \2\:Out) resistor r=0.6277 c=0 +rf8 (\2\:Out \3\:Out) resistor r=0.2434 c=0 +rf9 (\2\:Out \4\:Out) resistor r=0.4877 c=0 +rf10 (\3\:Out \5\:Out) resistor r=0.637 c=0 +rf11 (\3\:Out \6\:Out) resistor r=0.4883 c=0 +rf12 (\5\:Bi \6\:Bi) resistor r=0.2091 c=0 +rf13 (\6\:Bi Bi) resistor r=0.419 c=0 +rf14 (\6\:Bi \7\:Bi) resistor r=0.9147 c=0 +rf15 (\1\:vdd! vdd!) resistor r=0.4396 c=0 +rf16 (vdd! \2\:vdd!) resistor r=0.02609 c=0 +rf17 (\2\:vdd! \3\:vdd!) resistor r=0.1063 c=0 +rf18 (\3\:vdd! \4\:vdd!) resistor r=0.1044 c=0 +rf19 (\4\:vdd! vdd!) resistor r=0.06674 c=0 +rf20 (vdd! \5\:vdd!) resistor r=0.1518 c=0 +rf21 (\5\:vdd! vdd!) resistor r=0.1358 c=0 +rf22 (vdd! \6\:vdd!) resistor r=0.0436 c=0 +rf23 (\6\:vdd! \7\:vdd!) resistor r=0.4398 c=0 +rf24 (\3\:vdd! \8\:vdd!) resistor r=0.4 c=0 +rf25 (\5\:vdd! \9\:vdd!) resistor r=0.4844 c=0 +rf27 (B \1\:B) resistor r=0.04913 c=0 +rf29 (\1\:gnd! \2\:gnd!) resistor r=0.4481 c=0 +rf30 (\2\:gnd! \3\:gnd!) resistor r=0.1073 c=0 +rf31 (\3\:gnd! \4\:gnd!) resistor r=0.1061 c=0 +rf32 (\4\:gnd! 0) resistor r=0.06321 c=0 +rf33 (0 \5\:gnd!) resistor r=0.159 c=0 +rf34 (\5\:gnd! \6\:gnd!) resistor r=0.1812 c=0 +rf35 (\3\:gnd! \7\:gnd!) resistor r=0.385 c=0 +rf36 (\5\:gnd! \8\:gnd!) resistor r=0.4644 c=0 +rf37 (\6\:gnd! \9\:gnd!) resistor r=0.4233 c=0 +rg1 (\3\:A \4\:A) resistor r=152.382 c=0 +rg2 (\4\:A \2\:A) resistor r=10.7763 c=0 +rg3 (\4\:A \5\:A) resistor r=56.5484 c=0 +rg4 (\6\:Ai \5\:Ai) resistor r=438.925 c=0 +rg5 (\5\:Ai \7\:Ai) resistor r=89.7447 c=0 +rg6 (\8\:A \9\:A) resistor r=257.237 c=0 +rg7 (\9\:A \6\:A) resistor r=27.4119 c=0 +rg8 (\9\:A \10\:A) resistor r=53.5985 c=0 +rg9 (Bi \2\:Bi) resistor r=2.0523 c=0 +rg10 (\2\:Bi \3\:Bi) resistor r=38.5093 c=0 +rg11 (\2\:Bi \4\:Bi) resistor r=170.801 c=0 +rg12 (\1\:B \2\:B) resistor r=7.3761 c=0 +rg13 (\2\:B \3\:B) resistor r=170.445 c=0 +rg14 (\3\:B \4\:B) resistor r=337.766 c=0 +rg15 (\4\:B \5\:B) resistor r=299.266 c=0 +rg16 (\2\:B \6\:B) resistor r=38.7782 c=0 +MP5 (\1\:vdd! \3\:B \7\:Bi vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP4 (Ai \3\:A \7\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MP0 (net8 \7\:Ai \9\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\6\:Out \4\:B net8 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP3 (net022 \8\:A \4\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP2 (\8\:vdd! \4\:Bi net022 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN5 (\1\:gnd! \6\:B \5\:Bi 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN4 (\3\:Ai \5\:A \9\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN3 (net17 \5\:B \8\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\5\:Out \10\:A net17 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net32 \6\:Ai \1\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\7\:gnd! \3\:Bi net32 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=40n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/map/current b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/map/current new file mode 100644 index 0000000000000000000000000000000000000000..b34b943d4d0552bdf088ecf2ef33cadd197bcc74 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/map/current @@ -0,0 +1,26 @@ +( ( nil + version "2.1" + mapType "incremental" + blockName "xor2" + repList "spectre cmos_sch cmos.sch schematic veriloga" + stopList "spectre" + globalList "gnd! vdd!" + hierDelim "." + netlistDir "/home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C3/xor2/spectre/av_extracted/netlist" + ) +( instViewTable + ) +( net +( "gnd!" "0" ) + ) +( inst + ) +( model +( "multiplier_low/xor2/av_extracted" "xor2" ) + ) +( term + ) +( param + ) +( "xor2" "ihnl/cds0/map" ) + ) diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/map/current.ext b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/map/current.ext similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/map/current.ext rename to involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/map/current.ext diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlist b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlist new file mode 100644 index 0000000000000000000000000000000000000000..b63a8da30defc81ef0d9f1319877259b09692f91 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlist @@ -0,0 +1,82 @@ + +// Library name: multiplier_low +// Cell name: xor2 +// View name: av_extracted +re1 (\4\:Ai \2\:Ai) resistor r=4.1723 c=0 +re2 (\7\:A \1\:A) resistor r=4.652 c=0 +re3 (Out \3\:Out) resistor r=5.0851 c=0 +rf1 (\1\:A A) resistor r=0.003806 c=0 +rf2 (\1\:A \2\:A) resistor r=0.006818 c=0 +rf3 (Ai \2\:Ai) resistor r=0.4786 c=0 +rf4 (\2\:Ai \3\:Ai) resistor r=0.6211 c=0 +rf5 (\5\:Ai \4\:Ai) resistor r=0.09851 c=0 +rf6 (\6\:A \7\:A) resistor r=0.007087 c=0 +rf7 (\1\:Out \2\:Out) resistor r=0.6277 c=0 +rf8 (\2\:Out \3\:Out) resistor r=0.2434 c=0 +rf9 (\2\:Out \4\:Out) resistor r=0.4877 c=0 +rf10 (\3\:Out \5\:Out) resistor r=0.637 c=0 +rf11 (\3\:Out \6\:Out) resistor r=0.4883 c=0 +rf12 (\5\:Bi \6\:Bi) resistor r=0.2091 c=0 +rf13 (\6\:Bi Bi) resistor r=0.419 c=0 +rf14 (\6\:Bi \7\:Bi) resistor r=0.9147 c=0 +rf15 (\1\:vdd! vdd!) resistor r=0.4396 c=0 +rf16 (vdd! \2\:vdd!) resistor r=0.02609 c=0 +rf17 (\2\:vdd! \3\:vdd!) resistor r=0.1063 c=0 +rf18 (\3\:vdd! \4\:vdd!) resistor r=0.1044 c=0 +rf19 (\4\:vdd! vdd!) resistor r=0.06674 c=0 +rf20 (vdd! \5\:vdd!) resistor r=0.1518 c=0 +rf21 (\5\:vdd! vdd!) resistor r=0.1358 c=0 +rf22 (vdd! \6\:vdd!) resistor r=0.0436 c=0 +rf23 (\6\:vdd! \7\:vdd!) resistor r=0.4398 c=0 +rf24 (\3\:vdd! \8\:vdd!) resistor r=0.4 c=0 +rf25 (\5\:vdd! \9\:vdd!) resistor r=0.4844 c=0 +rf27 (B \1\:B) resistor r=0.04913 c=0 +rf29 (\1\:gnd! \2\:gnd!) resistor r=0.4481 c=0 +rf30 (\2\:gnd! \3\:gnd!) resistor r=0.1073 c=0 +rf31 (\3\:gnd! \4\:gnd!) resistor r=0.1061 c=0 +rf32 (\4\:gnd! 0) resistor r=0.06321 c=0 +rf33 (0 \5\:gnd!) resistor r=0.159 c=0 +rf34 (\5\:gnd! \6\:gnd!) resistor r=0.1812 c=0 +rf35 (\3\:gnd! \7\:gnd!) resistor r=0.385 c=0 +rf36 (\5\:gnd! \8\:gnd!) resistor r=0.4644 c=0 +rf37 (\6\:gnd! \9\:gnd!) resistor r=0.4233 c=0 +rg1 (\3\:A \4\:A) resistor r=152.382 c=0 +rg2 (\4\:A \2\:A) resistor r=10.7763 c=0 +rg3 (\4\:A \5\:A) resistor r=56.5484 c=0 +rg4 (\6\:Ai \5\:Ai) resistor r=438.925 c=0 +rg5 (\5\:Ai \7\:Ai) resistor r=89.7447 c=0 +rg6 (\8\:A \9\:A) resistor r=257.237 c=0 +rg7 (\9\:A \6\:A) resistor r=27.4119 c=0 +rg8 (\9\:A \10\:A) resistor r=53.5985 c=0 +rg9 (Bi \2\:Bi) resistor r=2.0523 c=0 +rg10 (\2\:Bi \3\:Bi) resistor r=38.5093 c=0 +rg11 (\2\:Bi \4\:Bi) resistor r=170.801 c=0 +rg12 (\1\:B \2\:B) resistor r=7.3761 c=0 +rg13 (\2\:B \3\:B) resistor r=170.445 c=0 +rg14 (\3\:B \4\:B) resistor r=337.766 c=0 +rg15 (\4\:B \5\:B) resistor r=299.266 c=0 +rg16 (\2\:B \6\:B) resistor r=38.7782 c=0 +MP5 (\1\:vdd! \3\:B \7\:Bi vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP4 (Ai \3\:A \7\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MP0 (net8 \7\:Ai \9\:vdd! vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP1 (\6\:Out \4\:B net8 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP3 (net022 \8\:A \4\:Out vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MP2 (\8\:vdd! \4\:Bi net022 vdd!) pmos1 w=1e-06 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN5 (\1\:gnd! \6\:B \5\:Bi 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN4 (\3\:Ai \5\:A \9\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) +MN3 (net17 \5\:B \8\:gnd! 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN2 (\5\:Out \10\:A net17 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN0 (net32 \6\:Ai \1\:Out 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 ad=1.2e-12 \ + ps=5.2u pd=5.2u m=(1)*(1) +MN1 (\7\:gnd! \3\:Bi net32 0) nmos1 w=8e-07 l=1.8e-07 as=1.2e-12 \ + ad=1.2e-12 ps=5.2u pd=5.2u m=(1)*(1) diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/netlistFooter b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlistFooter similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/netlistFooter rename to involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlistFooter diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlistHeader b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlistHeader new file mode 100644 index 0000000000000000000000000000000000000000..99efcbac92cfc2e49a18b4cc64f1ae2db4ed2e81 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/netlistHeader @@ -0,0 +1,7 @@ +// Generated for: spectre +// Generated on: May 27 03:31:12 2021 +// Design library name: multiplier_low +// Design cell name: xor2 +// Design view name: av_extracted +simulator lang=spectre +global 0 vdd! diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/runSimulation b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/runSimulation new file mode 100755 index 0000000000000000000000000000000000000000..372a3ba71b1140e4a0709d7f68c39492b2e07ffe --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/runSimulation @@ -0,0 +1,2 @@ +# runSimulation scripts generated for spectre interactive are not intended to be used for command line. +spectre input.scs +escchars +log ../psf/spectre.out +inter=mpsc +mpssession=spectre8_6429_19 -format psfxl -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/si.env b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/si.env new file mode 100644 index 0000000000000000000000000000000000000000..7413b1aa1770672a025b4e56e89d6883dc9ce092 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/si.env @@ -0,0 +1,15 @@ +simLibName = "multiplier_low" +simCellName = "xor2" +simViewName = "av_extracted" +simSimulator = "spectre" +simNotIncremental = 't +simReNetlistAll = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = 't +nlFormatterClass = 'spectreFormatter +nlCreateAmap = 't +nlDesignVarNameList = nil +simViewList = '("spectre" "cmos_sch" "cmos.sch" "schematic" "veriloga") +simStopList = '("spectre") +simNetlistHier = t diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.fc b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.fc new file mode 100644 index 0000000000000000000000000000000000000000..e4571a647b385ea520f49e9fc499318407308457 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.fc @@ -0,0 +1,95 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:31:17 AM, Thur May 27, 2021 +# Number of equations = 64 +1\:A 1.80000000000012 +1\:B 1.80000000000405 +1\:gnd! 4.94654396978078e-12 +1\:Out 4.15201498089543e-05 +1\:vdd! 1.79999999999841 +2\:A 1.80000000000001 +2\:Ai -8.86026176250805e-10 +2\:B 1.8000000006121 +2\:Bi 2.09936660311041e-09 +2\:gnd! 3.33504308674307e-12 +2\:Out 4.15201353629225e-05 +2\:vdd! 1.79999999999989 +3\:A 1.79999999829269 +3\:Ai -8.77824448818421e-10 +3\:B 1.80000001466236 +3\:Bi 2.01793601546319e-09 +3\:gnd! 2.94916037138948e-12 +3\:Out 4.15200881219248e-05 +3\:vdd! 1.79999999999944 +4\:A 1.79999999983385 +4\:Ai -9.78313126199423e-10 +4\:B 1.80000004364415 +4\:Bi 2.31078938971128e-09 +4\:gnd! 1.10103612944025e-12 +4\:Out 4.15202187955572e-05 +4\:vdd! 1.79999999999978 +5\:A 1.79999999953381 +5\:Ai -9.80492065259282e-10 +5\:B 1.8000000774755 +5\:Bi 2.100637882211e-09 +5\:gnd! 7.268497163547e-09 +5\:Out 4.14902806456166e-05 +5\:vdd! 1.79999999999991 +6\:A 1.80000000021551 +6\:Ai -1.00926707503787e-08 +6\:B 1.80000000061222 +6\:Bi 2.10153328653236e-09 +6\:gnd! 7.2673109588887e-09 +6\:Out 4.15201697266766e-05 +6\:vdd! 1.79999999999992 +7\:A 1.80000000021518 +7\:Ai -1.1024322411858e-09 +7\:Bi 2.10625215123842e-09 +7\:gnd! 8.27078598078417e-12 +7\:vdd! 1.79999999999913 +8\:A 1.79999999092831 +8\:gnd! 2.85010346797566e-08 +8\:vdd! 1.79999999999644 +9\:A 1.80000000148311 +9\:gnd! 7.26453987482766e-09 +9\:vdd! 1.79999999999929 +10\:A 1.80000000616088 +A 1.8 +Ai -8.81760032033324e-10 +B 1.8 +Bi 2.10116593317429e-09 +gnd! 0 +MN0:int_d 1.14268247203977 +MN0:int_s 4.15201889331444e-05 +MN1:int_d 3.17688730872023e-11 +MN1:int_s 1.14268247203812 +MN2:int_d 4.14107316507595e-05 +MN2:int_s 2.46258476431346e-05 +MN3:int_d 2.44683575212735e-05 +MN3:int_s 1.0622565521713e-07 +MN4:int_d -8.55375669821395e-10 +MN4:int_s 7.2534110231769e-09 +MN5:int_d 1.10602496184398e-11 +MN5:int_s 2.09335817228128e-09 +MP0:int_d 1.79999999942313 +MP0:int_s 1.79999999999744 +MP1:int_d 4.1520410379641e-05 +MP1:int_s 1.79999999942048 +MP2:int_d 1.79999999998565 +MP2:int_s 1.79999998191196 +MP3:int_d 1.79999998191016 +MP3:int_s 4.15204651416594e-05 +MP4:int_d -8.68924161424937e-10 +MP4:int_s 1.79999999999652 +MP5:int_d 1.7999999999932 +MP5:int_s 2.11368099695476e-09 +net8 1.7999999994218 +net17 2.4547102582204e-05 +net022 1.79999998191106 +net32 1.14268247203895 +Out 4.17562011040211e-05 +v0:p -2.70392721886289e-10 +v1:p 3.06915420918911e-11 +v2:p 0 +v3:p 8.24332539860596e-11 +vdd! 1.8 diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.ic b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.ic new file mode 100644 index 0000000000000000000000000000000000000000..b55ef1c046dd91743eed58673d3f93f9f9920b97 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.ic @@ -0,0 +1,95 @@ +# CHECKPOINT_VERSION 1 +# Generated by spectre (mode: Spectre) from circuit file `input.scs' during analysis tran. +# 3:31:17 AM, Thur May 27, 2021 +# Number of equations = 64 +1\:A 1.8 +1\:B 1.8 +1\:gnd! 3.36703285815914e-12 +1\:Out 1.17811095262107e-08 +1\:vdd! 1.79999999999796 +2\:A 1.8 +2\:Ai 2.9497936821549e-09 +2\:B 1.8 +2\:Bi 2.94622183211162e-09 +2\:gnd! 1.28514172926229e-12 +2\:Out 1.17811095269634e-08 +2\:vdd! 1.79999999999993 +3\:A 1.8 +3\:Ai 2.94690802586508e-09 +3\:B 1.8 +3\:Bi 2.94622183211162e-09 +3\:gnd! 7.86621492416421e-13 +3\:Out 1.17799786811327e-08 +3\:vdd! 1.79999999999965 +4\:A 1.8 +4\:Ai 2.94979368215489e-09 +4\:B 1.8 +4\:Bi 2.94622183211162e-09 +4\:gnd! 2.93676360142e-13 +4\:Out 1.17833754006443e-08 +4\:vdd! 1.79999999999986 +5\:A 1.8 +5\:Ai 2.94979368215489e-09 +5\:B 1.8 +5\:Bi 2.94525034486286e-09 +5\:gnd! 2.21616107119979e-12 +5\:Out 1.17740596270072e-08 +5\:vdd! 1.79999999999967 +6\:A 1.80000000000006 +6\:Ai 2.94979368215489e-09 +6\:B 1.8 +6\:Bi 2.94622183211162e-09 +6\:gnd! 3.0580237637966e-12 +6\:Out 1.17822473424376e-08 +6\:vdd! 1.7999999999998 +7\:A 1.80000000000006 +7\:Ai 2.94979368215489e-09 +7\:Bi 2.95047156614529e-09 +7\:gnd! 7.86622018746815e-13 +7\:vdd! 1.79999999999776 +8\:A 1.80000000000006 +8\:gnd! 6.531402370616e-12 +8\:vdd! 1.7999999999978 +9\:A 1.80000000000006 +9\:gnd! 5.02469306719741e-12 +9\:vdd! 1.79999999999742 +10\:A 1.80000000000006 +A 1.8 +Ai 2.95201727755065e-09 +B 1.8 +Bi 2.94622183211162e-09 +gnd! 0 +MN0:int_d -2.63267897631264e-08 +MN0:int_s 1.17811095241722e-08 +MN1:int_d 7.866243428031e-13 +MN1:int_s -2.63267897674158e-08 +MN2:int_d 1.17582630932342e-08 +MN2:int_s 5.90609201144538e-09 +MN3:int_d 5.87449894414211e-09 +MN3:int_s 2.23279359817434e-11 +MN4:int_d 2.93900975555002e-09 +MN4:int_s 1.29229633619798e-11 +MN5:int_d 1.12653031530144e-11 +MN5:int_s 2.93735207454775e-09 +MP0:int_d 1.79999998826053 +MP0:int_s 1.79999999999074 +MP1:int_d 1.17889376399578e-08 +MP1:int_s 1.79999998824717 +MP2:int_d 1.79999999999112 +MP2:int_s 1.79999998826091 +MP3:int_d 1.79999998824755 +MP3:int_s 1.17900656981645e-08 +MP4:int_d 2.95870757711165e-09 +MP4:int_s 1.79999999999108 +MP5:int_d 1.79999999999128 +MP5:int_s 2.95716186570632e-09 +net8 1.79999998825385 +net17 5.89029547779375e-09 +net022 1.79999998825423 +net32 -2.63267897652677e-08 +Out 1.17799786811327e-08 +v0:p -1.86129395935218e-11 +v1:p 1.37390099297368e-14 +v2:p 0 +v3:p -1.56125112837913e-18 +vdd! 1.8 diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/spectre.inp b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.inp similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/spectre.inp rename to involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.inp diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/spectre.sim b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.sim similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/netlist/spectre.sim rename to involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/netlist/spectre.sim diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/psf/.simDone b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/.simDone similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/psf/.simDone rename to involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/.simDone diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/artistLogFile b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/artistLogFile new file mode 100644 index 0000000000000000000000000000000000000000..cbed2ac64cc3e3977b0264e64ed308b29c7f87a0 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/artistLogFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:31:12 2021" +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"variables" "analysisInst" ( +"design_variables" +"variables_file" +"PSF" +"" +() +"" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/designParamVals.info b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/designParamVals.info new file mode 100644 index 0000000000000000000000000000000000000000..295214b726218ee6ab4fe33ab1d8347f50011816 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/designParamVals.info @@ -0,0 +1,62 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:31:20 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info" +"analysis name" "designParamVals" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"top-level" STRUCT( +"temp" FLOAT DOUBLE +"tnom" FLOAT DOUBLE +"time" FLOAT DOUBLE +"toxn" FLOAT DOUBLE +"dvthn" FLOAT DOUBLE +"dlxn" FLOAT DOUBLE +"dxwn" FLOAT DOUBLE +"cjn" FLOAT DOUBLE +"cjswn" FLOAT DOUBLE +"cjswgn" FLOAT DOUBLE +"cgon" FLOAT DOUBLE +"hdifn" FLOAT DOUBLE +"toxp" FLOAT DOUBLE +"dvthp" FLOAT DOUBLE +"dxlp" FLOAT DOUBLE +"dxwp" FLOAT DOUBLE +"cjp" FLOAT DOUBLE +"cjswp" FLOAT DOUBLE +"cjswgp" FLOAT DOUBLE +"cgop" FLOAT DOUBLE +"hdifp" FLOAT DOUBLE +) PROP( +"key" "parameters" +) +VALUE +"top-level" "top-level" ( +2.700000000000000e+01 +2.700000000000000e+01 +0.000000000000000e+00 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.000000000000000e-03 +2.000000000000000e-10 +3.300000000000000e-10 +3.700000000000000e-10 +2.000000000000000e-07 +4.000000000000000e-09 +0.000000000000000e+00 +0.000000000000000e+00 +0.000000000000000e+00 +1.100000000000000e-03 +2.500000000000000e-10 +4.200000000000000e-10 +3.300000000000000e-10 +2.000000000000000e-07 +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/element.info b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/element.info new file mode 100644 index 0000000000000000000000000000000000000000..cde2817d3644fbd86a343c3af575df24f320e145 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/element.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/finalTimeOP.info b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/finalTimeOP.info new file mode 100644 index 0000000000000000000000000000000000000000..0b61de51d6a1b627dd76cd88e82bf4091c33e090 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/finalTimeOP.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/logFile b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/logFile new file mode 100644 index 0000000000000000000000000000000000000000..b7e19c46813ade33887237910c3fc2bca559b37c --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/logFile @@ -0,0 +1,104 @@ +HEADER +"PSFversion" "1.00" +"Log Generator" "drlLog rev. 1.0" +"Log Time Stamp" "Thu May 27 03:31:20 2021" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:31:20 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"signalNameType" "spectre" +"measdgt" 0 +"ingold" 2 +"sst2usecolon" 0 +TYPE +"analysisInst" STRUCT( +"analysisType" STRING * +"dataFile" STRING * +"format" STRING * +"parent" STRING * +"sweepVariable" ARRAY ( * ) STRING * +"description" STRING * +) +VALUE +"tran-tran" "analysisInst" ( +"tran" +"tran.tran" +"PSF" +"" +("time") +"Transient Analysis `tran': time = (0 s -> 40 ns)" +) PROP( +"data_type" "swept_scalar" +) + +"finalTimeOP-info" "analysisInst" ( +"info" +"finalTimeOP.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"modelParameter-info" "analysisInst" ( +"info" +"modelParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"element-info" "analysisInst" ( +"info" +"element.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"outputParameter-info" "analysisInst" ( +"info" +"outputParameter.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"designParamVals-info" "analysisInst" ( +"info" +"designParamVals.info" +"PSF" +"" +() +"Circuit Information" +) PROP( +"data_type" "struct" +) + +"primitives-info.primitives" "analysisInst" ( +"info.primitives" +"primitives.info.primitives" +"PSF" +"" +() +"Circuit Information" +) +"subckts-info.subckts" "analysisInst" ( +"info.subckts" +"subckts.info.subckts" +"PSF" +"" +() +"Circuit Information" +) \ No newline at end of file diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/modelParameter.info b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/modelParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..1a43fd361028c3d3059b054583aae20566b1f39a Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/modelParameter.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/outputParameter.info b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/outputParameter.info new file mode 100644 index 0000000000000000000000000000000000000000..5bc6fc7d5a6890d5a562a44985f3f50b22ffda89 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/outputParameter.info differ diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/primitives.info.primitives b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/primitives.info.primitives new file mode 100644 index 0000000000000000000000000000000000000000..d1e2047c1a6c02bb073912c709c281b988d6784f --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/primitives.info.primitives @@ -0,0 +1,56 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:31:20 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.primitives" +"analysis name" "primitives" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"primitive" STRUCT( +"model" STRING * +"oppoint" STRING * +"output" STRING * +"inst" STRING * +"region" STRING * +"terminals" STRING * +) PROP( +"key" "prim" +) +VALUE +"bsim3v3" "primitive" ( +"type vtho vfb k1 k2 k3 k3b w0 nlx gamma1 gamma2 vbx vbm dvt0 dvt1 dvt2 dvt0w dvt1w dvt2w a0 b0 b1 a1 a2 ags keta vfbflag vthmod ivth ivthw ivthl ivth_vdsmin nsub nch ngate xj lint wint ll lln lw lwn lwl wl wln ww wwn wwl dwg dwb tox dtoxcv toxm toxe xt rdsw prwb prwg wr binunit binflag lref wref mobmod u0 vsat ua ub uc drout pclm pdiblc1 pdiblc2 pdiblcb pscbe1 pscbe2 pvag delta cdsc cdscb cdscd nfactor cit voff dsub eta0 etab alpha0 alpha1 beta0 rsh rs rd lgcs lgcd rsc rdc rss rdd sc ldif hdif minr js jsw jssw is n nj jtss jtsd jtssws jtsswd jtsswgs jtsswgd njts njtssw njtsswg njtsd njtsswd njtsswgd xtss xtsd xtssws xtsswd xtsswgs xtsswgd vtss vtsd vtssws vtsswd vtsswgs vtsswgd tnjts tnjtssw tnjtsswg tnjtsd tnjtsswd tnjtsswgd jsswg dskip imelt ijth jmelt vnds nds tt cgso cgdo cgbo meto cgsl cgdl ckappa cbs cbd cj mj pb fc cjsw mjsw pbsw cjswg mjswg pbswg fcsw capmod nqsmod acnqsmod dwc dlc clc cle cf elm vfbcv acde moin noff voffcv xpart llc lwc lwlc wlc wwc wwlc wmlt lmlt w l as ad ps pd nrd nrs version paramchk fullreinit level acm geo calcacm tnom trise tlev tlevc eg gap1 gap2 eglev diomod kt1 kt1l kt2 at ua1 ub1 uc1 prt trs trd ute xti pta tpb ptp tpbsw tpbswg cta tcj ctp tcjsw tcjswg noimod kf af ef noia noib noic noid wnoi em flkmod gamma nlev gdsnoi lintnoi agidl bgidl cgidl egidl agisl bgisl cgisl egisl bforward breverse cforward creverse tcc aigbinv bigbinv cigbinv eigbinv nigbinv aigbacc bigbacc cigbacc nigbacc aigsd bigsd cigsd aigc bigc cigc nigc pigcd dlcig ntox toxref poxedge igcmod igbmod wmax wmin lmax lmin alarm imax jmax bvj vbox warn apwarn vds_max vgd_max vgs_max vbd_max vbs_max vgb_max vgdr_max vgsr_max vgbr_max vbsr_max vbdr_max lvtho lvth0 lk1 lk2 lk3 lk3b lw0 lnlx lgamma1 lgamma2 lvbx lvbm ldvt0 ldvt1 ldvt2 ldvt0w ldvt1w ldvt2w la0 lb0 lb1 la1 la2 lags lketa lnsub lnch lngate lxj ldwg ldwb lxt lrdsw lprwb lprwg lwr lu0 lvsat lua lub luc ldrout lpclm lpdiblc1 lpdiblc2 lpdiblcb lpscbe1 lpscbe2 lpvag ldelta lcdsc lcdscb lcdscd lnfactor lcit lvoff ldsub leta0 letab lalpha0 lalpha1 lbeta0 lcgsl lcgdl lckappa lclc lcle lcf lelm lvfbcv lvfb lacde lmoin lnoff lvoffcv lkt1 lkt1l lkt2 lat lua1 lub1 luc1 lprt lute xl xlref lagidl lbgidl lcgidl legidl wvtho wvth0 wk1 wk2 wk3 wk3b ww0 wnlx wgamma1 wgamma2 wvbx wvbm wdvt0 wdvt1 wdvt2 wdvt0w wdvt1w wdvt2w wa0 wb0 wb1 wa1 wa2 wags wketa wnsub wnch wngate wxj wdwg wdwb wxt wrdsw wprwb wprwg wwr wu0 wvsat wua wub wuc wdrout wpclm wpdiblc1 wpdiblc2 wpdiblcb wpscbe1 wpscbe2 wpvag wdelta wcdsc wcdscb wcdscd wnfactor wcit wvoff wdsub weta0 wetab walpha0 walpha1 wbeta0 wcgsl wcgdl wckappa wclc wcle wcf welm wvfbcv wvfb wacde wmoin wnoff wvoffcv wkt1 wkt1l wkt2 wat wua1 wub1 wuc1 wprt wute xw xwref wagidl wbgidl wcgidl wegidl pvtho pvth0 pk1 pk2 pk3 pk3b pw0 pnlx pgamma1 pgamma2 pvbx pvbm pdvt0 pdvt1 pdvt2 pdvt0w pdvt1w pdvt2w pa0 pb0 pb1 pa1 pa2 pags pketa pnsub pnch pngate pxj pdwg pdwb pxt prdsw pprwb pprwg pwr pu0 pvsat pua pub puc pdrout ppclm ppdiblc1 ppdiblc2 ppdiblcb ppscbe1 ppscbe2 ppvag pdelta pcdsc pcdscb pcdscd pnfactor pcit pvoff pdsub peta0 petab palpha0 palpha1 pbeta0 pcgsl pcgdl pckappa pclc pcle pcf pelm pvfbcv pvfb pacde pmoin pnoff pvoffcv pkt1 pkt1l pkt2 pat pua1 pub1 puc1 pprt pute pagidl pbgidl pcgidl pegidl mvtwl mvtwl2 mvt0 mbewl mbe0 mismatchmod mismatchdist stimod sa0 saref sb0 sbref wlod ku0 kvsat kvth0 tku0 llodku0 wlodku0 llodvth wlodvth lku0 wku0 pku0 lkvth0 wkvth0 pkvth0 stk2 lodk2 steta0 lodeta0 wpemod web wec kvth0we k2we lkvth0we wkvth0we pkvth0we lk2we wk2we pk2we ku0we lku0we wku0we pku0we scref mnr bnr cnr dnr tmnr tcnr tdnr xjbv ijthrev nrfwd shrink shrink2 msgskip compatible " +"region reversed ids isub vgs vds vbs vgb vdb vgd vth vdsat vfbeff gm gds gmbs betaeff cjd cjs qb qg qd qbd qbs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id is ibulk ibs ibd pwr gmoverid ueff cgsovl cgdovl cgbovl i1 i3 i4 gbd gbs vgsteff qinv igd igs igb igcs igcd igidl igisl qgi qsi qdi qbi cddbi cssbi cggbi cgsbi cgdbi cbdbi cbsbi qsrco ide ige ise ibe idb isb vsb gmb vgt vdss vsat_marg self_gain rout beff fug vearly " +"tempeff meff weff leff rseff rdeff aseff adeff pseff pdeff " +"w l as ad ps pd nrd nrs m nqsmod acnqsmod isnoisy trise aforward areverse delvto mulmu0 mulu0 delk1 delnfct geo rdc rsc sa sb sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 stimod sca scb scc sc mulid0 mulbeta " +"off triode sat subth breakdown " +"d g s b " +) +"capacitor" "primitive" ( +"c trise tnom w l etch cj cjsw scalec rforce di thick coeffs symmetric min max tc1 tc2 shrink shrink2 bv_max " +"cap " +"tempeff meff leff weff ceff " +"c w l m scale trise tc1 tc2 ic area perim coeffs symmetric bv_max scalec " +"" +"1 2 " +) +"resistor" "primitive" ( +"r rsh thresh rthresh rac l w etch etchl scaler tc1 tc2 tnom trise coeffs nonlinform symmetric kf af wdexp ldexp weexp wf leexp lf fexp mr mrl mrlp mrw mrwp mrlw1 mrlw1p mrlw2 mrlw2p c cj cjsw thick di cratio tc1c tc2c shrink scalec dtemp cap dw dlr cox capsw res ef bv_max " +"v i res pwr " +"leff weff reff ceff tempeff meff " +"r l w lvl m scale resform tc1 tc1r tc2 tc2r trise isnoisy bv_max c tc1c tc2c rac scaler scalec dtemp cap " +"" +"1 2 0 " +) +"vsource" "primitive" ( +"" +"v i pwr " +"tempeff " +"dc type fundname delay edgetype val0 val1 period rise fall width file offset scale stretch rms pwlfilter rolloff pwlbandwidth allbrkpts pwlperiod pwlperiodstart twidth sinedc ampl freq sinephase ampl2 freq2 sinephase2 fundname2 iqmodfiles fmmodindex fmmodfreq fmmodfiles ammodindex ammodoffset ammodfreq ammodphase damp freqvec amplvec phasevec maxharms td1 tau1 td2 tau2 expperiod data rptstart rpttimes ref jitter rjseed rjrms pjamp pjfreq pjtype seed taps lfsrtaps lfsrseed registerlength triggerthreshold triggerdelthresh triggerdirection transitionreference noisefile noisetype noiseinterp isnoisy mag phase xfmag pacmag pacphase m tc1 tc2 tnom trise " +"" +"p n ctlp ctln " +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/runObjFile b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/runObjFile new file mode 100644 index 0000000000000000000000000000000000000000..1fd4b156df2e092daf60b14b0f9913995a4b9bcc --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/runObjFile @@ -0,0 +1,23 @@ +HEADER +"PSFversion" "1.00" +"Run Generator" "drlRun rev. 1.0" +"Run Time Stamp" "May 27 03:31:21 2021" +"simulator" "spectre" +"date" "May 27 03:31:21 2021" +"netlistDir" "../netlist" +TYPE +"runObject" STRUCT( +"logName" ARRAY( * ) STRING * +"parent" STRING * +"sweepVariable" ARRAY( * ) STRING * +) PROP( "key" "runObject" ) +VALUE +"Run1" "runObject" ( +( +"logFile" +"artistLogFile" +) +"" +() +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/simRunData b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/simRunData new file mode 100644 index 0000000000000000000000000000000000000000..6f168dde2e57282ca154bcf17e5ad5b8bab216b6 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/simRunData @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"design" "(\"multiplier_low\" \"xor2\" \"av_extracted\" \"\")" +"simulator" "spectre" +"temperature" "27" +"host" "" +"date" "May 27 03:31:12 2021" +"title" "" +"analysisList" "()" +END diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/spectre.out b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/spectre.out new file mode 100644 index 0000000000000000000000000000000000000000..ddda2a9087eefc4ee9af423c62d92e18cb40190d --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/spectre.out @@ -0,0 +1,257 @@ + +Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator +Version 13.1.1.205.isr10 64bit -- 23 Jul 2014 +Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. + +Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. + +User: VLSI_57 Host: serveric3 HostID: 140A347E PID: 83857 +Memory available: 1.3164 GB physical: 135.2177 GB +CPU Type: Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz + Processor PhysicalID CoreID Frequency Load + 0 0 0 2201.0 37.1 + 1 0 1 1200.0 42.5 + 2 0 2 1200.0 30.6 + 3 0 3 2201.0 20.0 + 4 0 4 1200.0 13.4 + 5 0 8 1200.0 9.6 + 6 0 9 1200.0 7.4 + 7 0 10 1200.0 6.3 + 8 0 11 1200.0 5.7 + 9 0 12 1200.0 5.3 + 10 1 0 1200.0 35.1 + 11 1 1 2201.0 41.9 + 12 1 2 1200.0 29.6 + 13 1 3 1200.0 19.2 + 14 1 4 1200.0 12.8 + 15 1 8 1200.0 9.2 + 16 1 9 1200.0 7.3 + 17 1 10 1200.0 6.3 + 18 1 11 1200.0 5.9 + 19 1 12 1200.0 5.2 + 20 0 0 1200.0 8.3 + 21 0 1 1200.0 8.9 + 22 0 2 1200.0 7.8 + 23 0 3 1200.0 6.2 + 24 0 4 1200.0 4.4 + 25 0 8 1200.0 3.0 + 26 0 9 1200.0 2.4 + 27 0 10 1200.0 1.7 + 28 0 11 1200.0 1.4 + 29 0 12 1200.0 1.6 + 30 1 0 1200.0 9.0 + 31 1 1 1200.0 8.9 + 32 1 2 1200.0 7.7 + 33 1 3 2201.0 6.1 + 34 1 4 2201.0 4.3 + 35 1 8 2201.0 2.9 + 36 1 9 1200.0 2.1 + 37 1 10 1200.0 1.6 + 38 1 11 1200.0 1.3 + 39 1 12 1200.0 1.2 + + +Simulating `input.scs' on serveric3 at 3:31:17 AM, Thur May 27, 2021 (process id: 83857). +Current working directory: /home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C3/xor2/spectre/av_extracted/netlist +Command line: + /home/eda_tools/Cadence/MMSIM1311ISR10/tools/bin/spectre -64 \ + input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ + +mpssession=spectre8_6429_19 -format psfxl -raw ../psf \ + +lqtimeout 900 -maxw 5 -maxn 5 +spectre pid = 83857 + +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... +Loading /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... +Reading file: /home/SME_VLSI/VLSI_57/simulation/delay2/xor2_C3/xor2/spectre/av_extracted/netlist/input.scs +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/configs/spectre.cfg +Reading file: /home/SME_VLSI/VLSI_57/306cadence/test_files/2_XOR_C3.input +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/gpdk.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/nmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/pmos1.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/resistor.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/diode.scs +Reading file: /home/SME_VLSI/306cadence/assuraTech/oa_2014/models/bipolar.scs +Time for NDB Parsing: CPU = 80.988 ms, elapsed = 3.13275 s. +Time accumulated: CPU = 114.982 ms, elapsed = 3.13276 s. +Peak resident memory used = 36.9 Mbytes. + +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/discipline.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/disciplines.vams +Reading link: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.h +Reading file: /home/eda_tools/Cadence/MMSIM1311ISR10/tools.lnx86/spectre/etc/ahdl/constants.vams +Time for Elaboration: CPU = 28.995 ms, elapsed = 28.6331 ms. +Time accumulated: CPU = 143.977 ms, elapsed = 3.16158 s. +Peak resident memory used = 41.9 Mbytes. + +Time for EDB Visiting: CPU = 1 ms, elapsed = 1.09196 ms. +Time accumulated: CPU = 144.977 ms, elapsed = 3.16287 s. +Peak resident memory used = 42.4 Mbytes. + + +Notice from spectre during topology check. + Only one connection to node `gnd!'. +Warning from spectre during initial setup. + WARNING (SPECTRE-8059): `ca': `current' No such output parameter, terminal, or internal node name. + WARNING (SPECTRE-8287): Ignoring invalid item `ca:current' in save statement. + + +Global user options: + reltol = 0.001 + vabstol = 1e-06 + iabstol = 1e-12 + temp = 27 + tnom = 27 + scalem = 1 + scale = 1 + gmin = 1e-12 + rforce = 1 + maxnotes = 5 + maxwarns = 5 + digits = 5 + cols = 80 + pivrel = 0.001 + sensfile = ../psf/sens.output + checklimitdest = psf + save = allpub + tnom = 27 + scalem = 1 + scale = 1 + +Circuit inventory: + nodes 63 + bsim3v3 12 + capacitor 1 + resistor 54 + vsource 4 + +Analysis and control statement inventory: + info 7 + tran 1 + +Output statements: + .probe 0 + .measure 0 + save 2 + +Time for parsing: CPU = 2.999 ms, elapsed = 271.417 ms. +Time accumulated: CPU = 147.976 ms, elapsed = 3.43448 s. +Peak resident memory used = 43.4 Mbytes. + +~~~~~~~~~~~~~~~~~~~~~~ +Pre-Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~ +Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre8_6429_19, ). + +Warning from spectre. + WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. + + +************************************************ +Transient Analysis `tran': time = (0 s -> 40 ns) +************************************************ +DC simulation time: CPU = 3 ms, elapsed = 2.06709 ms. +Important parameter values: + start = 0 s + outputstart = 0 s + stop = 40 ns + step = 40 ps + maxstep = 800 ps + ic = all + useprevic = no + skipdc = no + reltol = 1e-03 + abstol(V) = 1 uV + abstol(I) = 1 pA + temp = 27 C + tnom = 27 C + tempeffects = all + errpreset = moderate + method = traponly + lteratio = 3.5 + relref = sigglobal + cmin = 0 F + gmin = 1 pS + + +Output and IC/nodeset summary: + save 4 (current) + save 63 (voltage) + others 1 + + tran: time = 1.24 ns (3.1 %), step = 640 ps (1.6 %) + +Notice from spectre at time = 2 ns during transient analysis `tran'. + Found trapezoidal ringing on node v0:p. + + tran: time = 3.267 ns (8.17 %), step = 348.3 ps (871 m%) + +Notice from spectre at time = 3.80184 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:Ai. +Notice from spectre at time = 4.60184 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:Ai. +Notice from spectre at time = 5.40184 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:Ai. + + tran: time = 5.402 ns (13.5 %), step = 800 ps (2 %) + +Notice from spectre at time = 6.20184 ns during transient analysis `tran'. + Found trapezoidal ringing on node 7\:Ai. + Further occurrences of this notice will be suppressed. + + tran: time = 7.002 ns (17.5 %), step = 800 ps (2 %) + tran: time = 9.402 ns (23.5 %), step = 800 ps (2 %) + tran: time = 11 ns (27.5 %), step = 800 ps (2 %) + tran: time = 13.4 ns (33.5 %), step = 800 ps (2 %) + tran: time = 15 ns (37.5 %), step = 800 ps (2 %) + tran: time = 17.4 ns (43.5 %), step = 800 ps (2 %) + tran: time = 19 ns (47.5 %), step = 800 ps (2 %) + tran: time = 21.4 ns (53.5 %), step = 800 ps (2 %) + tran: time = 23 ns (57.5 %), step = 800 ps (2 %) + tran: time = 25.08 ns (62.7 %), step = 287.3 ps (718 m%) + tran: time = 27.17 ns (67.9 %), step = 800 ps (2 %) + tran: time = 29.57 ns (73.9 %), step = 800 ps (2 %) + tran: time = 31.28 ns (78.2 %), step = 466.7 ps (1.17 %) + tran: time = 33.68 ns (84.2 %), step = 800 ps (2 %) + tran: time = 35.28 ns (88.2 %), step = 800 ps (2 %) + tran: time = 37.68 ns (94.2 %), step = 800 ps (2 %) + tran: time = 39.28 ns (98.2 %), step = 800 ps (2 %) +Number of accepted tran steps = 128 + +Notice from spectre during transient analysis `tran'. + Trapezoidal ringing is detected during tran analysis. + Please use method=trap for better results and performance. + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Post-Transient Simulation Summary +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + - Parasitics slow down simulation. To speed up, consider + add +parasitics on command line + add ++parasitics on command line + - To further speed up simulation, consider + add ++aps on command line + add +cktpreset=sampled on command line for ADC/DAC simulation + add +cktpreset=pll on command line for PLL simulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Initial condition solution time: CPU = 3 ms, elapsed = 2.17009 ms. +Intrinsic tran analysis time: CPU = 25.995 ms, elapsed = 119.609 ms. +Total time required for tran analysis `tran': CPU = 32.995 ms, elapsed = 126.095 ms. +Time accumulated: CPU = 186.97 ms, elapsed = 3.79817 s. +Peak resident memory used = 45.6 Mbytes. + + +Notice from spectre. + 20 notices suppressed. + +finalTimeOP: writing operating point information to rawfile. +modelParameter: writing model parameter values to rawfile. +element: writing instance parameter values to rawfile. +outputParameter: writing output parameter values to rawfile. +designParamVals: writing netlist parameters to rawfile. +primitives: writing primitives to rawfile. +subckts: writing subcircuits to rawfile. diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/subckts.info.subckts b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/subckts.info.subckts new file mode 100644 index 0000000000000000000000000000000000000000..535b969c08c2e888229a6e42cc695a99384f0f40 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/subckts.info.subckts @@ -0,0 +1,24 @@ +HEADER +"PSFversion" "1.00" +"simulator" "spectre" +"version" "13.1.1.205.isr10" +"date" "3:31:20 AM, Thur May 27, 2021" +"design" "// Generated for: spectre" +"analysis type" "info.subckts" +"analysis name" "subckts" +"analysis description" "Circuit Information" +"xVecSorted" "unknown" +"tolerance.relative" 0.00100000 +TYPE +"subckt" STRUCT( +"subckt_params" STRING * +"subckt_terminals" STRING * +) PROP( +"key" "sub" +) +VALUE +"nplusres" "subckt" ( +"" +"" +) +END diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran new file mode 100644 index 0000000000000000000000000000000000000000..f75e86ee37a908a956c4a4194b9c11dd7a1dd458 Binary files /dev/null and b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran differ diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp new file mode 100644 index 0000000000000000000000000000000000000000..c222ae0965482325aef28aa6413fb82bdff917e6 --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran.0.sig.tmp @@ -0,0 +1,151 @@ +*cdnsheobpacket 26 1 +*cdnshlastgoodpoint 26 0,0 +*cdnshnumflushes 26 0 +*cdnshnxdbpid 26 83857 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129 32 V 0 +­­¨©|138167984|­­¨© 0 0 0 912 137997456 \5\:vdd! 0 1 912 0 4.0000000000000000837e-08 1.7999960208707894704 1.8000021400580945574 129 33 V 0 +­­¨©|138168832|­­¨© 0 0 0 912 137997456 \6\:A 0 1 912 0 4.0000000000000000837e-08 -1.7713091093629965145e-05 1.8000115666593214936 129 34 V 0 +­­¨©|138169744|­­¨© 0 0 0 912 137997456 \6\:Ai 0 1 912 0 4.0000000000000000837e-08 -0.0074439825820846496074 1.8261672871589720302 129 35 V 0 +­­¨©|138170656|­­¨© 0 0 0 912 137997456 \6\:B 0 1 912 0 4.0000000000000000837e-08 1.7999967648459165304 1.8000180621481152166 129 36 V 0 +­­¨©|138171568|­­¨© 0 0 0 912 137997456 \6\:Bi 0 1 912 0 4.0000000000000000837e-08 -0.0017450531561181829333 0.00033389518223350309577 129 37 V 0 +­­¨©|138172480|­­¨© 0 0 0 912 137997456 \6\:gnd! 0 1 912 0 4.0000000000000000837e-08 -6.6101389400451204348e-06 0.00012076174708401887998 129 38 V 0 +­­¨©|138173392|­­¨© 0 0 0 912 137997456 \6\:Out 0 1 912 0 4.0000000000000000837e-08 -0.0008901250225191109991 1.724089226544550657 129 39 V 0 +­­¨©|138174304|­­¨© 0 0 0 912 137997456 \6\:vdd! 0 1 912 0 4.0000000000000000837e-08 1.799992350568118793 1.800000799155346165 129 40 V 0 +­­¨©|138175216|­­¨© 0 0 0 912 137997456 \7\:A 0 1 912 0 4.0000000000000000837e-08 -1.7686101603150636286e-05 1.8000115490847521382 129 41 V 0 +­­¨©|138176128|­­¨© 0 0 0 912 137997456 \7\:Ai 0 1 912 0 4.0000000000000000837e-08 -0.0074657964023649749097 1.8262661504128323564 129 42 V 0 +­­¨©|138177040|­­¨© 0 0 0 912 137997456 \7\:Bi 0 1 912 0 4.0000000000000000837e-08 -0.0017450009239420073443 0.00033392755203623977582 129 43 V 0 +­­¨©|138177952|­­¨© 0 0 0 912 137997456 \7\:gnd! 0 1 912 0 4.0000000000000000837e-08 -4.7278028694556512108e-07 8.4833833358504531216e-08 129 44 V 0 +­­¨©|138178864|­­¨© 0 0 0 912 137997456 \7\:vdd! 0 1 912 0 4.0000000000000000837e-08 1.7999151895557023995 1.8000088603599626591 129 45 V 0 +­­¨©|138179776|­­¨© 0 0 0 912 137997456 \8\:A 0 1 912 0 4.0000000000000000837e-08 -0.0010456943739505578095 1.8002957451227687979 129 46 V 0 +­­¨©|138180688|­­¨© 0 0 0 912 137997456 \8\:gnd! 0 1 912 0 4.0000000000000000837e-08 -5.5501141854642804834e-06 0.00020703931425671213192 129 47 V 0 +­­¨©|138181600|­­¨© 0 0 0 912 137997456 \8\:vdd! 0 1 912 0 4.0000000000000000837e-08 1.7999434048270508413 1.8000026436581133549 129 48 V 0 +­­¨©|138182512|­­¨© 0 0 0 912 137997456 \9\:A 0 1 912 0 4.0000000000000000837e-08 -0.00012210609435103769727 1.8000795435665193356 129 49 V 0 +­­¨©|138183424|­­¨© 0 0 0 912 137997456 \9\:gnd! 0 1 912 0 4.0000000000000000837e-08 -1.3948316383421662914e-05 0.00023002042559903075939 129 50 V 0 +­­¨©|138184336|­­¨© 0 0 0 912 137997456 \9\:vdd! 0 1 912 0 4.0000000000000000837e-08 1.7999691297120439248 1.8000166026801684982 129 51 V 0 +­­¨©|138185712|­­¨© 0 0 0 912 137997456 \10\:A 0 1 912 0 4.0000000000000000837e-08 -0.00013378477560475193764 1.8001674105833112005 129 52 V 0 +­­¨©|138186592|­­¨© 0 0 0 912 137997456 A 0 1 912 0 4.0000000000000000837e-08 0 1.8000000000000000444 129 53 V 0 +­­¨©|138187504|­­¨© 0 0 0 912 137997456 Ai 0 1 912 0 4.0000000000000000837e-08 -0.0074893038808937209203 1.8262950837468117093 129 54 V 0 +­­¨©|138188416|­­¨© 0 0 0 912 137997456 B 0 1 912 0 4.0000000000000000837e-08 1.8000000000000000444 1.8000000000000000444 129 55 V 0 +­­¨©|138189328|­­¨© 0 0 0 912 137997456 Bi 0 1 912 0 4.0000000000000000837e-08 -0.0017462713920322558113 0.0003340702550598267798 129 56 V 0 +­­¨©|138190240|­­¨© 0 0 0 912 137997456 gnd! 0 1 912 0 4.0000000000000000837e-08 0 0 129 57 V 0 +­­¨©|138191152|­­¨© 0 0 0 912 137997456 net8 0 1 912 0 4.0000000000000000837e-08 1.7556514455611089698 1.9270133801029181164 129 58 V 0 +­­¨©|138192064|­­¨© 0 0 0 912 137997456 net17 0 1 912 0 4.0000000000000000837e-08 -0.0037130401011645905104 0.31506872895241000432 129 59 V 0 +­­¨©|138192976|­­¨© 0 0 0 912 137997456 net022 0 1 912 0 4.0000000000000000837e-08 1.4322551973536039593 1.8130482093886695072 129 60 V 0 +­­¨©|138193888|­­¨© 0 0 0 912 137997456 net32 0 1 912 0 4.0000000000000000837e-08 -0.00040994766077113531464 1.273634747927837596 129 61 V 0 +­­¨©|138194800|­­¨© 0 0 0 912 137997456 Out 0 1 912 0 4.0000000000000000837e-08 -0.00085863372462538750229 1.724050256833427941 129 62 V 0 +­­¨©|138195712|­­¨© 0 0 0 912 137997456 v0:p 0 1 912 0 4.0000000000000000837e-08 -0.00022479958082586106762 1.2862433712578214527e-05 129 63 A 0 +­­¨©|138196624|­­¨© 0 0 0 912 137997456 v1:p 0 1 912 0 4.0000000000000000837e-08 -7.544481349534510673e-05 6.2266098172252760316e-05 129 64 A 0 +­­¨©|138198160|­­¨© 0 0 0 912 137997456 v2:p 0 1 912 0 4.0000000000000000837e-08 0 0 129 65 A 0 +­­¨©|138198960|­­¨© 0 0 0 912 137997456 v3:p 0 1 912 0 4.0000000000000000837e-08 -3.4828137088079058426e-07 2.2337991621827268531e-06 129 66 A 0 +­­¨©|138199872|­­¨© 0 0 0 912 137997456 vdd! 0 1 912 0 4.0000000000000000837e-08 1.8000000000000000444 1.8000000000000000444 129 67 V 0 +­­¨ª|1|­­¨ª 0 0 0 72200 0 RootScope 68 68 0 0 0 0 0 0 <> +­­¨ª|137997456|­­¨ª 0 0 0 72200 0 RootScope 68 68 0 0 0 0 0 0 <> diff --git a/Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/psf/tran.tran.sig.tmp b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran.sig.tmp similarity index 100% rename from Design/simulation/ADE_output/nand2_C3/nand2/spectre/extracted/psf/tran.tran.sig.tmp rename to involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/tran.tran.sig.tmp diff --git a/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/variables_file b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/variables_file new file mode 100644 index 0000000000000000000000000000000000000000..64f6fd33290be717ceced39d5cfbf289ec9b523a --- /dev/null +++ b/involution/Design/simulation/ADE_output/xor2_C3/xor2/spectre/av_extracted/psf/variables_file @@ -0,0 +1,10 @@ +HEADER +"PSFversion" "1.00" +"Time Stamp" "May 27 03:31:12 2021" +TYPE +"variable" STRUCT( +"value" FLOAT DOUBLE +) PROP( "key" "element" ) +VALUE +"temp" "variable" ( 27 ) PROP( ) +END diff --git a/involution/Design/simulation/test_files/1_input.input b/involution/Design/simulation/test_files/1_input.input new file mode 100644 index 0000000000000000000000000000000000000000..096f9452dec79d2f014ffece6cab771d42cff6e5 --- /dev/null +++ b/involution/Design/simulation/test_files/1_input.input @@ -0,0 +1,7 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 2n 0 2.2n 1.8 9.2n 1.8 9.4n 0] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/Design/simulation/test_files/1_input_C1.input b/involution/Design/simulation/test_files/1_input_C1.input similarity index 100% rename from Design/simulation/test_files/1_input_C1.input rename to involution/Design/simulation/test_files/1_input_C1.input diff --git a/Design/simulation/test_files/1_input_C2.input b/involution/Design/simulation/test_files/1_input_C2.input similarity index 100% rename from Design/simulation/test_files/1_input_C2.input rename to involution/Design/simulation/test_files/1_input_C2.input diff --git a/Design/simulation/test_files/1_input_C3.input b/involution/Design/simulation/test_files/1_input_C3.input similarity index 100% rename from Design/simulation/test_files/1_input_C3.input rename to involution/Design/simulation/test_files/1_input_C3.input diff --git a/Design/simulation/test_files/2_AND_C1.input b/involution/Design/simulation/test_files/2_AND_C1.input similarity index 100% rename from Design/simulation/test_files/2_AND_C1.input rename to involution/Design/simulation/test_files/2_AND_C1.input diff --git a/Design/simulation/test_files/2_AND_C2.input b/involution/Design/simulation/test_files/2_AND_C2.input similarity index 100% rename from Design/simulation/test_files/2_AND_C2.input rename to involution/Design/simulation/test_files/2_AND_C2.input diff --git a/involution/Design/simulation/test_files/2_AND_C3.input b/involution/Design/simulation/test_files/2_AND_C3.input new file mode 100644 index 0000000000000000000000000000000000000000..010f8f01ead3a00bf76e88d26aa08fc2abab9974 --- /dev/null +++ b/involution/Design/simulation/test_files/2_AND_C3.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 8.2n 0 8.4n 1.8 10.4n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 8.2n 1.8 8.4n 1.8 10.4n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=960f +save ca:current +save :pwr diff --git a/involution/Design/simulation/test_files/2_AND_C3.input~ b/involution/Design/simulation/test_files/2_AND_C3.input~ new file mode 100644 index 0000000000000000000000000000000000000000..010f8f01ead3a00bf76e88d26aa08fc2abab9974 --- /dev/null +++ b/involution/Design/simulation/test_files/2_AND_C3.input~ @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 8.2n 0 8.4n 1.8 10.4n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 8.2n 1.8 8.4n 1.8 10.4n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=960f +save ca:current +save :pwr diff --git a/Design/simulation/test_files/2_NAND_C1.input b/involution/Design/simulation/test_files/2_NAND_C1.input similarity index 100% rename from Design/simulation/test_files/2_NAND_C1.input rename to involution/Design/simulation/test_files/2_NAND_C1.input diff --git a/Design/simulation/test_files/2_NAND_C2.input b/involution/Design/simulation/test_files/2_NAND_C2.input similarity index 100% rename from Design/simulation/test_files/2_NAND_C2.input rename to involution/Design/simulation/test_files/2_NAND_C2.input diff --git a/involution/Design/simulation/test_files/2_NAND_C3.input b/involution/Design/simulation/test_files/2_NAND_C3.input new file mode 100644 index 0000000000000000000000000000000000000000..2d8a307b8000bec20054c65ca72234169fa9634e --- /dev/null +++ b/involution/Design/simulation/test_files/2_NAND_C3.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 14.2n 0 14.4n 1.8 16.4n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 14.2n 1.8 14.4n 1.8 16.4n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=960f +save ca:current +save :pwr diff --git a/Design/simulation/test_files/2_AND_C3.input b/involution/Design/simulation/test_files/2_NAND_C3.input~ similarity index 100% rename from Design/simulation/test_files/2_AND_C3.input rename to involution/Design/simulation/test_files/2_NAND_C3.input~ diff --git a/Design/simulation/test_files/2_XOR_C1.input b/involution/Design/simulation/test_files/2_XOR_C1.input similarity index 100% rename from Design/simulation/test_files/2_XOR_C1.input rename to involution/Design/simulation/test_files/2_XOR_C1.input diff --git a/involution/Design/simulation/test_files/2_XOR_C2.input b/involution/Design/simulation/test_files/2_XOR_C2.input new file mode 100644 index 0000000000000000000000000000000000000000..d016a59366537b2073056f493548fa12b49746f0 --- /dev/null +++ b/involution/Design/simulation/test_files/2_XOR_C2.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 8.2n 0 8.4n 1.8 10.4n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 8.2n 1.8 8.4n 1.8 10.4n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=120f +save ca:current +save :pwr diff --git a/Design/simulation/test_files/2_XOR_C2.input b/involution/Design/simulation/test_files/2_XOR_C2.input~ similarity index 100% rename from Design/simulation/test_files/2_XOR_C2.input rename to involution/Design/simulation/test_files/2_XOR_C2.input~ diff --git a/involution/Design/simulation/test_files/2_XOR_C3.input b/involution/Design/simulation/test_files/2_XOR_C3.input new file mode 100644 index 0000000000000000000000000000000000000000..90fb16f0c780f9f7aaceffa71e410ec15ed5bcd1 --- /dev/null +++ b/involution/Design/simulation/test_files/2_XOR_C3.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 24.2n 0 24.4n 1.8 30.4n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 24.2n 1.8 24.4n 1.8 30.4n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=960f +save ca:current +save :pwr diff --git a/involution/Design/simulation/test_files/2_XOR_C3.input~ b/involution/Design/simulation/test_files/2_XOR_C3.input~ new file mode 100644 index 0000000000000000000000000000000000000000..24433c8ae56040d516b0934eca5cf5db4e5fc12d --- /dev/null +++ b/involution/Design/simulation/test_files/2_XOR_C3.input~ @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 0 16.2n 0 16.4n 1.8 24.4n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 1.8 2n 1.8 2.2n 1.8 16.2n 1.8 16.4n 1.8 24.4n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=960f +save ca:current +save :pwr diff --git a/involution/Design/simulation/test_files/2_input.input b/involution/Design/simulation/test_files/2_input.input new file mode 100644 index 0000000000000000000000000000000000000000..cd548cfff8a6368d38f759118181f7054a486e23 --- /dev/null +++ b/involution/Design/simulation/test_files/2_input.input @@ -0,0 +1,8 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 1.8 16n 1.8 16.2n 0 24n 0 24.2n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 0 16n 0 16.2n 1.8 24n 1.8 24.2n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/Design/simulation/test_files/2_input_C1.input b/involution/Design/simulation/test_files/2_input_C1.input similarity index 100% rename from Design/simulation/test_files/2_input_C1.input rename to involution/Design/simulation/test_files/2_input_C1.input diff --git a/Design/simulation/test_files/2_input_C2.input b/involution/Design/simulation/test_files/2_input_C2.input similarity index 100% rename from Design/simulation/test_files/2_input_C2.input rename to involution/Design/simulation/test_files/2_input_C2.input diff --git a/Design/simulation/test_files/2_input_C3.input b/involution/Design/simulation/test_files/2_input_C3.input similarity index 100% rename from Design/simulation/test_files/2_input_C3.input rename to involution/Design/simulation/test_files/2_input_C3.input diff --git a/Design/simulation/test_files/3_input.input b/involution/Design/simulation/test_files/3_input.input similarity index 100% rename from Design/simulation/test_files/3_input.input rename to involution/Design/simulation/test_files/3_input.input diff --git a/involution/Design/simulation/test_files/3_input.input~ b/involution/Design/simulation/test_files/3_input.input~ new file mode 100644 index 0000000000000000000000000000000000000000..d898debac25182fd6d936371b5434a6175e7b1be --- /dev/null +++ b/involution/Design/simulation/test_files/3_input.input~ @@ -0,0 +1,9 @@ +simulator lang=spectre +v0 (vdd! 0) vsource type=dc dc=1.8 +v1 (A 0) vsource type=pwl wave=[0n 0 16n 0 16.2n 1.8] +v3 (B 0) vsource type=pwl wave=[0n 0 8n 0 8.2n 1.8 16n 1.8 16.2n 0 24n 0 24.2n 1.8] +v4 (Cin 0) vsource type=pwl wave=[0n 0 4n 0 4.2n 1.8 8n 1.8 8.2n 0 12n 0 12.2n 1.8 16n 1.8 16.2n 0 20n 0 20.2n 1.8 24n 1.8 24.2n 0 28n 0 28.2n 1.8] +v2 (gnd! 0) vsource type=dc dc=0 +ca (Out 0) capacitor c=0.3p +save ca:current +save :pwr diff --git a/Design/simulation/test_files/4x4_mul.input b/involution/Design/simulation/test_files/4x4_mul.input similarity index 100% rename from Design/simulation/test_files/4x4_mul.input rename to involution/Design/simulation/test_files/4x4_mul.input diff --git a/Design/simulation/test_files/4x4_mul.input~ b/involution/Design/simulation/test_files/4x4_mul.input~ similarity index 100% rename from Design/simulation/test_files/4x4_mul.input~ rename to involution/Design/simulation/test_files/4x4_mul.input~ diff --git a/Design/simulation/test_files/4x4_mul_00011110.input b/involution/Design/simulation/test_files/4x4_mul_00011110.input similarity index 100% rename from Design/simulation/test_files/4x4_mul_00011110.input rename to involution/Design/simulation/test_files/4x4_mul_00011110.input diff --git a/Design/simulation/test_files/4x4_mul_00011110.input~ b/involution/Design/simulation/test_files/4x4_mul_00011110.input~ similarity index 100% rename from Design/simulation/test_files/4x4_mul_00011110.input~ rename to involution/Design/simulation/test_files/4x4_mul_00011110.input~ diff --git a/Design/simulation/test_files/4x4_mul_11100001.input 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If that is unneeded, please comment it out. +\usepackage{cite} +\usepackage{amsmath,amssymb,amsfonts} +\usepackage{algorithmic} +\usepackage{graphicx} +\usepackage{textcomp} +\usepackage{xcolor} +\usepackage{float} +\usepackage{subfigure} +\usepackage{subfig} +% \graphicspath{{../figures/}{../../Design/Design_figures}} +\graphicspath{{../figures}{../../Design/Design_figures}{../../Design/simulation/trans_result}} + + +\def\BibTeX{{\rm B\kern-.05em{\sc i\kern-.025em b}\kern-.08em + T\kern-.1667em\lower.7ex\hbox{E}\kern-.125emX}} +\begin{document} + + +\title{Design of $4\times 4$ multiplier from schematic to layout +\thanks{Identify applicable funding agency here. If none, delete this.} +} + +\author{\IEEEauthorblockN{1\textsuperscript{st} YUAN Tong} +\IEEEauthorblockA{\textit{School of Microelectronic} \\ +\textit{Southern University of Science and Technology}\\ +Shenzhen, China \\ +yuant2018@mail.sustech.edu.cn} +\and +\IEEEauthorblockN{2\textsuperscript{nd} FAN Qinyuan} +\IEEEauthorblockA{\textit{School of Microelectronic} \\ +\textit{Southern University of Science and Technology}\\ +Shenzhen, China \\ +fanqy2018@mail.sustech.edu.cn} +} + +\maketitle + +\begin{abstract} + In this paper a low power and high speed 4X4 multiplier is designed using TSMC 0.18nm CMOS Technology. The important factors in VLSI Design are power, area, speed and design time. Now-a-days, power and speed has become a crucial factor in Digital Signal Processor (DSP) Applications. However, different optimization techniques are available in the digital electronic world. The proposed approach a Low power and high speed Multiplier Design based on Modified Column bypassing technique mainly used to reduce the switching power activity. While this technique offers great dynamic power savings, due to their interconnection. In this work, a low power and high speed multiplier with Hybridization scheme is presented. This scheme is combination of booth encoder algorithm and column bypass technique is called modified column bypassing scheme. The simulations are performed in 0.18µm CMOS Technology in Cadence Virtuoso tools with operating voltage ±1.8v. +\end{abstract} + +\begin{IEEEkeywords} + Multiplier, CMOS, Column Bypassing, Digital Signal Applications (DSP), Row Bypassing, Booth encoder +\end{IEEEkeywords} + +\section{Introduction} + +% In the introduction, students are asked to give a short introduction on the subject. This would include: A brief background study related to the topic; Motivation of the project; Possible application of the design. + +As one of the key components of modern CPU, multiplier is a widely studied computer architecture which take the responsbility of most of the calculation operation in computer. Currently widely used multiplier inculding Booth multiplier, Sequential multiplier, combinational multiplier, Wallace tree multiplier \cite{a1}. The performance of the multiplier is a key fact that will greatly affect the performance of processors, so the design of a small, fast and energy efficiency multiplier is a prior problem we need to pay attention to today. + +In this report, we will demostrate the design procedure of the $4 \times 4$ multiplier. In secition \ref{basic}, we will introduce the design of basic components including NAND gate, AND gate, XOR gate and invertor then we assemble them into main componet of a multiplier, half adder and full adder. In section \ref{Assemble} we will build the multiplier and the performance of the multiplier will be tested in section \ref{test}. + +\section{Our Problem and design idea} + +% Explain briefly the objectives of the project. For example the design of low power array multiplier, with minimum delay and minimum silicon area. Explain how you achieve these objectives. + +In this project we are assigned to design a classcial $ 4 \times 4 $ bit multiplier as small and fast as possible, and we also wish we could use high level design to increase the design speed. To achieve our goal, we will focus on the following design principles. Firstly, we will minimize the width of each components and the space between them under the constrain of design rule, that will help us achiveve the minimum space. Secondly, we need to aviod using high layer of metal which is the main cause of delay. Finally we can find the minimun kinds of components we need by apply top-to-down design. + +To design the multiplier start from the high level structure of the multiplier, as shown in Figure \ref{High level structure of 4x4 multiplier}, a multiplier consists of half adder, full adder, and AND Gate, and a step futher, we can move our attention to the structure of full adder and half adder. In Fig \ref{Half adder} and \ref{Full adder}, we can see the two differnt kinds of adders are consist of NAND Gate, XOR Gete, and AND Gate, while and gate can be divided into NAND Gate and invertor, so what we need is NAND Gate, Inverter and XOR Gate, though XOR Gate can be divided into more simple gates, but to reduce the space, we will design the XOR Gate as a single component. + +\begin{figure}[h] + \centering + \includegraphics[width=0.9\linewidth]{4x4_multiplier.png} + \caption{High level structure of 4x4 multiplier} + \label{High level structure of 4x4 multiplier} +\end{figure} + +\begin{figure}[h] + \centering + \includegraphics[width=0.45\linewidth]{half_adder.png} + \caption{Half adder} + \label{Half adder} +\end{figure} + +\begin{figure}[h] + \centering + \includegraphics[width=0.6\linewidth]{full_adder.jpeg} + \caption{Full adder} + \label{Full adder} +\end{figure} + +% In this section students should first start by describing the global architecture with clear drawing(s). A top - down description is encouraged. In this section students are encouraged to go through the different circuit diagrams as well as the sizing of the transistors, simulation layout and post-layout simulation. Students are encouraged to put more emphasis on how they are taking care of the objectives set. This section should also include the analysis of the critical delay, study of the floor-planning for the different blocks, and the final circuit together with the physical layout and its verification. The details that should be covered in this section include the following parts with tables and descriptions. + +\section{Design and verication of basic components} + +% You need to develop a library of basic (standard) cells that are used for the multiplier design. All the components in the library (inverters and more complex gates that are needed for the final multiplier design) must be briefly introduced. Prepare a Table with the transistors sizes (both width and length in micrometers), output low-to-high propagation delay, and output high-to-low propagation delay of each basic cell that is used in the multiplier design. If you have different sizes of the same type of logic gate, you need to report the size and delay of each different sized gate in your library. Produce the delay data using post-layout simulation for each type of gate. Add the Table in your report. Apply an input signal with rise and fall times of 0.2 ns (10% to 90% signal transition time) for measuring the delays. For each basic gate, report three different delays with three different extrinsic load capacitors: C1 = 15 fF, C2 = 8*C1, and C3 = 64*C1. Discuss the relationship between delay and extrinsic load capacitance in the report. How does this relationship change as you go from a CMOS inverter to more complex gates with more than one input? Provide your answers in the report. + +\label{basic} + +\subsection{Inverter} + +The simpliest structure is Inverter consists of a pmos and a nmos as shown in Fig \ref{Schematic of Inverter}, they all have 0.18um in length, which is the minimun length of gate under 0.18 um TSMC technology, and after a balence between space and speed, we choose 4um as the width of pmos and 1.6um as the width of the nmos, to make sure all the gates perform well, the size of other gates will equivlent the inverter. + +\begin{figure}[H] + \centering + \includegraphics[width = 0.6\linewidth]{inv_schematic} + \caption{Schematic of Inverter} + \label{Schematic of Inverter} +\end{figure} + +Then we will test the performance of the inverter, we add three different extrinsic load capacitors: C1 = 15 fF, C2 = 8*C1, and C3 = 64*C1 to the output of the inverter and test its delay, the result is listed in Table \ref{The delay of inverter}. To measure the propagation delay, we will + +\begin{table}[h] + \caption{The delay of inverter} + \begin{center} + \begin{tabular}{|c|c|c|c|c|c|c|} + \hline + \textbf{Cap} & \multicolumn{2}{|c|}{15f F} & \multicolumn{2}{|c|}{120f F} & \multicolumn{2}{|c|}{960f F} \\ + \hline + \textbf{State} & Up & Down & Up & Down & Up & Down \\ + \hline + + \textbf{Delay(ns)} & 0.125 & 0.068 & 0.553 & 0.263 & 3.918 & 1.792 \\ + \hline + \end{tabular} + \end{center} + \label{The delay of inverter} +\end{table} + +\subsection{NAND Gate} + +NAND Gate is one of the most important basic gates, to make the gate equivlent to inverter we choose 4um as the width of the PMOS, and 3.2um as the width of NMOS. + +\begin{figure}[H] + \centering + \includegraphics[width = 0.7\linewidth]{nand2_schematic.png} + \caption{Schematic of NAND Gate} + \label{Schematic of NAND Gate} +\end{figure} + +The performance of NAND Gate will be tested under the same method as Inverter. + +\begin{table}[h] + \caption{The delay of NAND Gate} + \begin{center} + \begin{tabular}{|c|c|c|c|c|c|c|} + \hline + \textbf{Cap} & \multicolumn{2}{|c|}{15f F} & \multicolumn{2}{|c|}{120f F} & \multicolumn{2}{|c|}{960f F} \\ + \hline + \textbf{State} & Up & Down & Up & Down & Up & Down \\ + \hline + + \textbf{Delay(ns)} & 0.134 & 0.095 & 0.558 & 0.383 & 4.931 & 2.589 \\ + \hline + \end{tabular} + \end{center} + \label{The delay of NAND} +\end{table} + +\subsection{AND Gate} + +To make things more simplfied, we use a inverter and a NAND Gate to assemble an AND Gate, so the size of MOS transistors in AND Gate can be refered from the size of NAND Gate and Inverter. + +\begin{figure}[H] + \centering + \includegraphics[width = 0.9\linewidth]{and2_schematic.png} + \caption{Schematic of AND Gate} + \label{Schematic of AND Gate} +\end{figure} + +The performance of AND Gate will be tested under the same method as Inverter. + +\begin{table}[h] + \caption{The delay of AND Gate} + \begin{center} + \begin{tabular}{|c|c|c|c|c|c|c|} + \hline + \textbf{Cap} & \multicolumn{2}{|c|}{15f F} & \multicolumn{2}{|c|}{120f F} & \multicolumn{2}{|c|}{960f F} \\ + \hline + \textbf{State} & Up & Down & Up & Down & Up & Down \\ + \hline + + \textbf{Delay(ns)} & 0.161 & 0.147 & 0.591 & 0.344 & 3.955 & 1.870 \\ + \hline + \end{tabular} + \end{center} + \label{The delay of AND} +\end{table} + +\subsection{XOR Gate} + +For XOR Gate, we have same MOS size as Inverter, as all the PMOSs have width 4um and NMOSs have width 1.6nm. + +\begin{figure}[H] + \centering + \includegraphics[width = 0.9\linewidth]{xor2_schematic.png} + \caption{Schematic of XOR Gate} + \label{Schematic of XOR Gate} +\end{figure} + +\begin{figure}[H] + \centering + \includegraphics[width = 0.6\linewidth]{xor2_layout.png} + \caption{Layout of XOR Gate} + \label{Layout of XOR Gate} +\end{figure} + +The performance of XOR Gate is shown in Table \ref{The delay of XOR}. + +\begin{table}[h] + \caption{The delay of XOR Gate} + \begin{center} + \begin{tabular}{|c|c|c|c|c|c|c|} + \hline + \textbf{Cap} & \multicolumn{2}{|c|}{15f F} & \multicolumn{2}{|c|}{120f F} & \multicolumn{2}{|c|}{960f F} \\ + \hline + \textbf{State} & Up & Down & Up & Down & Up & Down \\ + \hline + \textbf{Delay(ns)} & 0.259 & 0.101 & 1.088 & 0.392 & 7.689 & 2.496 \\ + \hline + \end{tabular} + \end{center} + \label{The delay of XOR} +\end{table} + +\section{Adder} + +For adder, more horizontal wire are required, it is hard to avoid using high level metal wire and the area will be big if we put all the MOS pairs in a line. To solve this problem, we put all the pairs in to two layers, and we also use poly and metal1 as wire as many as possible so we can reduce the area and delay. More importantly we put the pairs in two row, so wiring vertally is possible, which greatly shorten the length of wire. + +\subsection{Half Adder} + +% Explain the circuit structure and operation of the half adder that is used in multiplier design. Provide the circuit schematic in the report. Provide the sizes (both width and length in micrometers) of all the transistors. + +A half adder is a conbination of a AND Gate and a XOR Gate, each of their input A and B are connected together and the outout of XOR Gate is defined as Sum, the outpt of AND is defined as Carry. The size of the transistors can be refered from XOR Gate and AND Gate introduced before. + +\begin{figure}[H] + \centering + \includegraphics[width = 0.9\linewidth]{half_adder_schematic.png} + \caption{Schematic of Half Adder} + \label{Schematic of Half Adder} +\end{figure} + +\begin{figure}[H] + \centering + \includegraphics[width = 0.3\linewidth]{half_adder_layout.png} + \caption{Layout of Half Adder} + \label{Layout of Half Adder} +\end{figure} + +\subsection{Full Adder} + +% Explain the circuit structure and operation of the full adder that is used in multiplier design. Provide the circuit schematic in the report. Provide the sizes (both width and length in micrometers) of all the transistors. + +As shown in Fig \ref{Schematic of Full Adder}, a full adder is a combination of XOR Gates and NAND gates, the structure here is simplified from the classical design in which a full adder contains two half adder and AND Gate, so we can save a lot of area. + +\begin{figure}[H] + \centering + \includegraphics[width = 0.9\linewidth]{full_adder_schematic.png} + \caption{Schematic of Full Adder} + \label{Schematic of Full Adder} +\end{figure} + +\begin{figure}[H] + \centering + \includegraphics[width = 0.5\linewidth]{full_adder_layout.png} + \caption{Layout of Full Adder} + \label{Layout of Full Adder} +\end{figure} + + +\section{Assemble of the multiplier} +\label{Assemble} + +% Explain the structure and operation of the array multiplier. Provide the circuit structure in the report. Clearly label all the inputs and outputs. Clearly show all the connections among various components. Determine the number of critical (longest) delay paths in the 4x4-bit array multiplier. Identify and report the input vectors that excite these critical propagation delay paths. Show one of these critical delay paths on the figure. Measure the propagation delay of the multiplier with schematic level simulation. Assume each product output drives 50 fF extrinsic load capacitor. Report the delays. + +\subsection{Schemetic} + +The schematic of the multiplier is shown in Fig \ref{4X4_Multiplier_schematic}, it has contians many full adders half adders and and gates. we connect them together as the design shown before. + +\begin{figure}[H] + \centering + \includegraphics[width=0.9\linewidth]{4X4_Multiplier_schematic.png} + \caption{Schematic of $4 \times 4$ bit multiplier} + \label{4X4_Multiplier_schematic} +\end{figure} + +\subsection{Layout} + +In the layout, we use the low level layer as wire to reduce the delay time. We use poly, metal1, metal2, and some metal3 as the connection wire between each components. + +\begin{figure}[H] + \centering + \includegraphics[width=0.9\linewidth]{4X4_Multiplier_layout.png} + \caption{Layout of $4 \times 4$ bit multiplier} + \label{4X4_Multiplier_layout} +\end{figure} + +\section{Varication and benckmark of the multiplier} +\label{test} + +% Show the layout of your array multiplier in the report. Report the area of your layout. Measure the post-layout propagation delay and report it in your report. Assume each product output drives 50 fF extrinsic load capacitor. Compare the post-layout delay measurements with the schematic level delay measurement. Explain the differences. Discuss the limitations of the schematic level circuit simulation tool. Discuss the importance of accurate resistance and capacitance extraction for correct delay estimation with CADENCE tools. + +After we finish the design of the multiplier we need to test the performance of the multiplier. + +\subsection{Area of the Layout} + +As we tested, the area of the layout is \textbf{((0.39, -52)(62, 0)), 3276$\mu m^2$} + +\subsection{propagation delay} + +Here we will compare the post-layout delay measurements with the schematic level delay measurement 50f F cap is attached to the output. We apply two set of input to the multiplier so we can get the transfer data of all output. The first set is $0000 \times 1111 = 11100001$ and the second set is $0010 \times 1111 = 00011110$. As we measure, the maxmun down-to-up delay is \textbf{1.915ns} and uo-to-down delay is \textbf{0.96ns}, the plots are shown in Appendix. + +\section{Conclusion} + +In this project, we experience the procedure of Top to Down design and Down to Top Develop, we first design the multiplier in hignest level, then we gradually split each of the component so we can get the basic logic gate we need. The development procedure start form the bisic logic gate, we design half adder and full adder based on these logic gates, finally the multiplier will be constructed by adders. In each level a serises of test were done to make sure the design functions well. During the layout procedure, we change the way transistors were put, so the size and delay is reduced. + + +% \input{tutorial.tex} + +\input{reference.tex} + + +\newpage +\section{Appendix} + +\subsection{Delay of basic Gates} + +% ------------------------------------------------------------- +\subsubsection{Inverter} +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{inv_C1.png} + \caption{Delay of Inverter with output capacitance 15f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{inv_C2.png} + \caption{Delay of Inverter with output capacitance 120f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{inv_C3.png} + \caption{Delay of Inverter with output capacitance 960f F} +\end{figure} +% ------------------------------------------------------------- +\subsubsection{NAND Gate} +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{nand2_C1.png} + \caption{Delay of NAND Gate with output capacitance 15f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{nand2_C2.png} + \caption{Delay of NAND Gate with output capacitance 120f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{nand2_C3.png} + \caption{Delay of NAND Gate with output capacitance 960f F} +\end{figure} +% ------------------------------------------------------------- +\subsubsection{AND Gate} +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{and2_C1.png} + \caption{Delay of AND Gate with output capacitance 15f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{and2_C2.png} + \caption{Delay of AND Gate with output capacitance 120f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{and2_C3.png} + \caption{Delay of AND Gate with output capacitance 960f F} +\end{figure} +% ------------------------------------------------------------- +\subsubsection{XOR Gate} +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{xor2_C1.png} + \caption{Delay of XOR Gate with output capacitance 15f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{xor2_C2.png} + \caption{Delay of XOR Gate with output capacitance 120f F} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{xor2_C3.png} + \caption{Delay of XOR Gate with output capacitance 960f F} +\end{figure} +% ------------------------------------------------------------- + +\subsection{Delay of the multiplier} + + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{mul_11100001_up_all.png} + \caption{Low to high delay of 11100001} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{mul_11100001_up_max.png} + \caption{Low to high delay of 11100001} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{mul_11100001_down_all.png} + \caption{High to low delay of 11100001} +\end{figure} + +\begin{figure}[h!] + \centering + \includegraphics[width=0.9\linewidth]{mul_11100001_down_max.png} + \caption{High to low delay of 11100001} +\end{figure} + + + +\end{document} diff --git a/involution/Report/IEEE_report/4x4_multiplier_design.xdv b/involution/Report/IEEE_report/4x4_multiplier_design.xdv new file mode 100644 index 0000000000000000000000000000000000000000..408fecabd4d34b19ae5b7244ecfc4df1e86e367d Binary files /dev/null and b/involution/Report/IEEE_report/4x4_multiplier_design.xdv differ diff --git a/Report/IEEE_report/IEEEtran.cls b/involution/Report/IEEE_report/IEEEtran.cls similarity index 100% rename from Report/IEEE_report/IEEEtran.cls rename to involution/Report/IEEE_report/IEEEtran.cls diff --git a/Report/IEEE_report/IEEEtran_HOWTO.pdf b/involution/Report/IEEE_report/IEEEtran_HOWTO.pdf similarity index 100% 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from Design/multiplier/and2_ass/layout/layout.oa.cdslck rename to standard/Design/multiplier/and2_ass/layout/layout.oa.cdslck diff --git a/standard/Design/multiplier/and2_ass/layout/master.tag b/standard/Design/multiplier/and2_ass/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/standard/Design/multiplier/and2_ass/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/and2_ass/layout/thumbnail_128x128.png b/standard/Design/multiplier/and2_ass/layout/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/and2_ass/layout/thumbnail_128x128.png rename to standard/Design/multiplier/and2_ass/layout/thumbnail_128x128.png diff --git a/standard/Design/multiplier/cdsinfo.tag b/standard/Design/multiplier/cdsinfo.tag new file mode 100644 index 0000000000000000000000000000000000000000..a8dcdcb44a684665752d276e04098c00ae423cd3 --- /dev/null +++ b/standard/Design/multiplier/cdsinfo.tag @@ -0,0 +1,40 @@ +# +# This is a cdsinfo.tag file. +# +# See the "Cadence Application Infrastructure Reference Manual" for +# details on the format of this file, its semantics, and its use. +# +# The `#' character denotes a comment. Removing the leading `#' +# character from any of the entries below will activate them. +# +# CDSLIBRARY entry - add this entry if the directory containing +# this cdsinfo.tag file is the root of a Cadence library. +# CDSLIBRARY +# +# CDSLIBCHECK - set this entry to require that libraries have +# a cdsinfo.tag file with a CDSLIBRARY entry. Legal values are +# ON and OFF. By default (OFF), directories named in a cds.lib file +# do not have to have a cdsinfo.tag file with a CDSLIBRARY entry. +# CDSLIBCHECK ON +# +# DMTYPE - set this entry to define the DM system for Cadence's +# Generic DM facility. Values will be shifted to lower case. +# DMTYPE none +# DMTYPE crcs +# DMTYPE tdm +# DMTYPE sync +# +# NAMESPACE - set this entry to define the library namespace according +# to the type of machine on which the data is stored. Legal values are +# `LibraryNT' and +# `LibraryUnix'. +# NAMESPACE LibraryUnix +# +# Other entries may be added for use by specific applications as +# name-value pairs. Application documentation will describe the +# use and behaviour of these entries when appropriate. +# +# Current Settings: +# +CDSLIBRARY +NAMESPACE LibraryUnix diff --git a/standard/Design/multiplier/data.dm b/standard/Design/multiplier/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..c88ce1d063f7697091de015df89086f580a4b9cd Binary files /dev/null and b/standard/Design/multiplier/data.dm differ diff --git a/standard/Design/multiplier/full_adder_2/av_extracted/CCLFile b/standard/Design/multiplier/full_adder_2/av_extracted/CCLFile new file mode 100644 index 0000000000000000000000000000000000000000..97c016135db048bf9cf6a5cdc73366de41aed614 --- /dev/null +++ b/standard/Design/multiplier/full_adder_2/av_extracted/CCLFile @@ -0,0 +1,43 @@ +# +# OPTION COMMAND FILE created by Cadence Quantus QRC Extraction Version 14.1.5-s182 from CCL +# +device_reduction \ + -m_factor infinite +extract \ + -selection "all" \ + -type "r_only" +extraction_setup \ + -array_vias_spacing auto \ + -max_fracture_length infinite \ + -max_fracture_length_unit "MICRONS" \ + -max_via_array_size \ + "auto" \ + -net_name_space "LAYOUT" +filter_res \ + -min_res 0.001 +input_db -type assura \ + -design_cell_name "full_adder_2 layout multiplier" \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -format "DFII" \ + -run_name "full_adder_2" +log_file \ + -file_name "/home/SME_VLSI/VLSI_57/306cadence/LVS/qrc.full_adder_2.log" +output_db -type extracted_view \ + -enable_cellview_check false \ + -include_cap_model "false" \ + -include_parasitic_cap_model "true" \ + -include_parasitic_res_model "comment" \ + -include_res_model "false" \ + -res_component "presistor" \ + -res_property_name "r" \ + -view_name "av_extracted" +output_setup \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -temporary_directory_name "full_adder_2" +process_technology \ + -technology_library_file "/home/SME_VLSI/306cadence/assuraTech/oa_2014/assura_tech.lib" \ + -technology_name "assura_gpdk_tech" \ + -temperature \ + 25.0 + + diff --git a/standard/Design/multiplier/full_adder_2/av_extracted/data.dm b/standard/Design/multiplier/full_adder_2/av_extracted/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..2896fa811079674a4365ff1fa61e7bc66982c8f6 Binary files /dev/null and b/standard/Design/multiplier/full_adder_2/av_extracted/data.dm differ diff --git a/Design/multiplier/full_adder_2/av_extracted/layout.oa b/standard/Design/multiplier/full_adder_2/av_extracted/layout.oa similarity index 100% rename from Design/multiplier/full_adder_2/av_extracted/layout.oa rename to standard/Design/multiplier/full_adder_2/av_extracted/layout.oa diff --git a/standard/Design/multiplier/full_adder_2/av_extracted/master.tag b/standard/Design/multiplier/full_adder_2/av_extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ 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index 100% rename from Design/multiplier/full_adder_2/layout/layout.oa- rename to standard/Design/multiplier/full_adder_2/layout/layout.oa- diff --git a/standard/Design/multiplier/full_adder_2/layout/master.tag b/standard/Design/multiplier/full_adder_2/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/standard/Design/multiplier/full_adder_2/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/full_adder_2/layout/thumbnail_128x128.png b/standard/Design/multiplier/full_adder_2/layout/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/full_adder_2/layout/thumbnail_128x128.png rename to standard/Design/multiplier/full_adder_2/layout/thumbnail_128x128.png diff --git a/Design/multiplier/full_adder_2/schematic/data.dm b/standard/Design/multiplier/full_adder_2/schematic/data.dm similarity index 100% rename from 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b/standard/Design/multiplier/full_adder_2/symbol/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..8c9cc7f0efd3f9e8b1d092a852413a5d21b3a4c4 Binary files /dev/null and b/standard/Design/multiplier/full_adder_2/symbol/thumbnail_128x128.png differ diff --git a/Design/multiplier/full_adder_2_ass/layout/layout.oa b/standard/Design/multiplier/full_adder_2_ass/layout/layout.oa similarity index 100% rename from Design/multiplier/full_adder_2_ass/layout/layout.oa rename to standard/Design/multiplier/full_adder_2_ass/layout/layout.oa diff --git a/Design/multiplier/full_adder_2_ass/layout/layout.oa- b/standard/Design/multiplier/full_adder_2_ass/layout/layout.oa- similarity index 100% rename from Design/multiplier/full_adder_2_ass/layout/layout.oa- rename to standard/Design/multiplier/full_adder_2_ass/layout/layout.oa- diff --git a/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck b/standard/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck similarity index 100% rename from Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck rename to standard/Design/multiplier/full_adder_2_ass/layout/layout.oa.cdslck diff --git a/standard/Design/multiplier/full_adder_2_ass/layout/master.tag b/standard/Design/multiplier/full_adder_2_ass/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/standard/Design/multiplier/full_adder_2_ass/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/full_adder_2_ass/layout/thumbnail_128x128.png b/standard/Design/multiplier/full_adder_2_ass/layout/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/full_adder_2_ass/layout/thumbnail_128x128.png rename to standard/Design/multiplier/full_adder_2_ass/layout/thumbnail_128x128.png diff --git a/standard/Design/multiplier/half_adder_2/av_extracted/CCLFile b/standard/Design/multiplier/half_adder_2/av_extracted/CCLFile new file mode 100644 index 0000000000000000000000000000000000000000..01c0e53cddfabaa1ff87017c6b2d3bbe0601a930 --- /dev/null +++ b/standard/Design/multiplier/half_adder_2/av_extracted/CCLFile @@ -0,0 +1,43 @@ +# +# OPTION COMMAND FILE created by Cadence Quantus QRC Extraction Version 14.1.5-s182 from CCL +# +device_reduction \ + -m_factor infinite +extract \ + -selection "all" \ + -type "r_only" +extraction_setup \ + -array_vias_spacing auto \ + -max_fracture_length infinite \ + -max_fracture_length_unit "MICRONS" \ + -max_via_array_size \ + "auto" \ + -net_name_space "LAYOUT" +filter_res \ + -min_res 0.001 +input_db -type assura \ + -design_cell_name "half_adder_2 layout multiplier" \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -format "DFII" \ + -run_name "full_adder_2" +log_file \ + -file_name "/home/SME_VLSI/VLSI_57/306cadence/LVS/qrc.full_adder_2.log" +output_db -type extracted_view \ + -enable_cellview_check false \ + -include_cap_model "false" \ + -include_parasitic_cap_model "true" \ + -include_parasitic_res_model "comment" \ + -include_res_model "false" \ + -res_component "presistor" \ + -res_property_name "r" \ + -view_name "av_extracted" +output_setup \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -temporary_directory_name "full_adder_2" +process_technology \ + -technology_library_file "/home/SME_VLSI/306cadence/assuraTech/oa_2014/assura_tech.lib" \ + -technology_name "assura_gpdk_tech" \ + -temperature \ + 25.0 + + diff --git a/standard/Design/multiplier/half_adder_2/av_extracted/data.dm b/standard/Design/multiplier/half_adder_2/av_extracted/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..0c59810ae28f0961bcea27537c6cd43eb10ae067 Binary files /dev/null and b/standard/Design/multiplier/half_adder_2/av_extracted/data.dm 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a/Design/multiplier/half_adder_2_ass/layout/layout.oa b/standard/Design/multiplier/half_adder_2_ass/layout/layout.oa similarity index 100% rename from Design/multiplier/half_adder_2_ass/layout/layout.oa rename to standard/Design/multiplier/half_adder_2_ass/layout/layout.oa diff --git a/Design/multiplier/half_adder_2_ass/layout/layout.oa- b/standard/Design/multiplier/half_adder_2_ass/layout/layout.oa- similarity index 100% rename from Design/multiplier/half_adder_2_ass/layout/layout.oa- rename to standard/Design/multiplier/half_adder_2_ass/layout/layout.oa- diff --git a/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck b/standard/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck similarity index 100% rename from Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck rename to standard/Design/multiplier/half_adder_2_ass/layout/layout.oa.cdslck diff --git a/standard/Design/multiplier/half_adder_2_ass/layout/master.tag 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b/standard/Design/multiplier/inv/av_extracted/data.dm similarity index 100% rename from Design/multiplier/inv/av_extracted/data.dm rename to standard/Design/multiplier/inv/av_extracted/data.dm diff --git a/Design/multiplier/inv/av_extracted/layout.oa b/standard/Design/multiplier/inv/av_extracted/layout.oa similarity index 100% rename from Design/multiplier/inv/av_extracted/layout.oa rename to standard/Design/multiplier/inv/av_extracted/layout.oa diff --git a/standard/Design/multiplier/inv/av_extracted/master.tag b/standard/Design/multiplier/inv/av_extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/standard/Design/multiplier/inv/av_extracted/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/standard/Design/multiplier/inv/data.dm b/standard/Design/multiplier/inv/data.dm new file mode 100644 index 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b/standard/Design/multiplier/inv/layout/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/inv/layout/thumbnail_128x128.png rename to standard/Design/multiplier/inv/layout/thumbnail_128x128.png diff --git a/Design/multiplier/inv/schematic/data.dm b/standard/Design/multiplier/inv/schematic/data.dm similarity index 100% rename from Design/multiplier/inv/schematic/data.dm rename to standard/Design/multiplier/inv/schematic/data.dm diff --git a/standard/Design/multiplier/inv/schematic/master.tag b/standard/Design/multiplier/inv/schematic/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..26be1bef2ea7f883db0d50576c31cb244b3b0d9f --- /dev/null +++ b/standard/Design/multiplier/inv/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Design/multiplier/inv/schematic/sch.oa b/standard/Design/multiplier/inv/schematic/sch.oa similarity index 100% rename from Design/multiplier/inv/schematic/sch.oa rename to standard/Design/multiplier/inv/schematic/sch.oa diff --git a/standard/Design/multiplier/inv/schematic/thumbnail_128x128.png b/standard/Design/multiplier/inv/schematic/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..a06d54d758de56100e3417ed4d419f78335a6eb4 Binary files /dev/null and b/standard/Design/multiplier/inv/schematic/thumbnail_128x128.png differ diff --git a/standard/Design/multiplier/inv/symbol/master.tag b/standard/Design/multiplier/inv/symbol/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..e1024da05678ababdb17d8f8ef60d53e9761add0 --- /dev/null +++ b/standard/Design/multiplier/inv/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/standard/Design/multiplier/inv/symbol/symbol.oa b/standard/Design/multiplier/inv/symbol/symbol.oa new file mode 100644 index 0000000000000000000000000000000000000000..68887101f1288b440db7c58f391b07f5a2be8d07 Binary files /dev/null and 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-max_fracture_length_unit "MICRONS" \ + -max_via_array_size \ + "auto" \ + -net_name_space "LAYOUT" +filter_res \ + -min_res 0.001 +input_db -type assura \ + -design_cell_name "nand2 layout 306Lib" \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -format "DFII" \ + -run_name "buffer" +log_file \ + -file_name "/home/SME_VLSI/VLSI_57/306cadence/LVS/qrc.buffer.log" +output_db -type extracted_view \ + -enable_cellview_check false \ + -include_cap_model "false" \ + -include_parasitic_cap_model "true" \ + -include_parasitic_res_model "comment" \ + -include_res_model "false" \ + -res_component "presistor" \ + -res_property_name "r" \ + -view_name "av_extracted" +output_setup \ + -directory_name "/home/SME_VLSI/VLSI_57/306cadence/LVS" \ + -temporary_directory_name "buffer" +process_technology \ + -technology_library_file "/home/SME_VLSI/306cadence/assuraTech/oa_2014/assura_tech.lib" \ + -technology_name "assura_gpdk_tech" \ + -temperature \ + 25.0 + + diff --git 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/dev/null +++ b/standard/Design/multiplier/nand2/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/nand2/layout/thumbnail_128x128.png b/standard/Design/multiplier/nand2/layout/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/nand2/layout/thumbnail_128x128.png rename to standard/Design/multiplier/nand2/layout/thumbnail_128x128.png diff --git a/Design/multiplier/nand2/schematic/data.dm b/standard/Design/multiplier/nand2/schematic/data.dm similarity index 100% rename from Design/multiplier/nand2/schematic/data.dm rename to standard/Design/multiplier/nand2/schematic/data.dm diff --git a/standard/Design/multiplier/nand2/schematic/master.tag b/standard/Design/multiplier/nand2/schematic/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..26be1bef2ea7f883db0d50576c31cb244b3b0d9f --- /dev/null +++ b/standard/Design/multiplier/nand2/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Design/multiplier/nand2/schematic/sch.oa b/standard/Design/multiplier/nand2/schematic/sch.oa similarity index 100% rename from Design/multiplier/nand2/schematic/sch.oa rename to standard/Design/multiplier/nand2/schematic/sch.oa diff --git a/standard/Design/multiplier/nand2/schematic/thumbnail_128x128.png b/standard/Design/multiplier/nand2/schematic/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..bef12046ce82093a069bc8a216c04756acaec77f Binary files /dev/null and b/standard/Design/multiplier/nand2/schematic/thumbnail_128x128.png differ diff --git a/standard/Design/multiplier/nand2/symbol/master.tag b/standard/Design/multiplier/nand2/symbol/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..e1024da05678ababdb17d8f8ef60d53e9761add0 --- /dev/null +++ b/standard/Design/multiplier/nand2/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git 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b/standard/Design/multiplier/xor2/av_extracted/CCLFile similarity index 100% rename from Design/multiplier/xor2/av_extracted/CCLFile rename to standard/Design/multiplier/xor2/av_extracted/CCLFile diff --git a/Design/multiplier/xor2/av_extracted/data.dm b/standard/Design/multiplier/xor2/av_extracted/data.dm similarity index 100% rename from Design/multiplier/xor2/av_extracted/data.dm rename to standard/Design/multiplier/xor2/av_extracted/data.dm diff --git a/Design/multiplier/xor2/av_extracted/layout.oa b/standard/Design/multiplier/xor2/av_extracted/layout.oa similarity index 100% rename from Design/multiplier/xor2/av_extracted/layout.oa rename to standard/Design/multiplier/xor2/av_extracted/layout.oa diff --git a/standard/Design/multiplier/xor2/av_extracted/master.tag b/standard/Design/multiplier/xor2/av_extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/standard/Design/multiplier/xor2/av_extracted/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/standard/Design/multiplier/xor2/data.dm b/standard/Design/multiplier/xor2/data.dm new file mode 100644 index 0000000000000000000000000000000000000000..a4b12e433c67d0c4be984c6f86228c86aca5fbe1 Binary files /dev/null and b/standard/Design/multiplier/xor2/data.dm differ diff --git a/standard/Design/multiplier/xor2/extracted/layout.oa b/standard/Design/multiplier/xor2/extracted/layout.oa new file mode 100644 index 0000000000000000000000000000000000000000..902a7421fa39188cd5b57900034e246385b94a72 Binary files /dev/null and b/standard/Design/multiplier/xor2/extracted/layout.oa differ diff --git a/standard/Design/multiplier/xor2/extracted/master.tag b/standard/Design/multiplier/xor2/extracted/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ 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a/standard/Design/multiplier/xor2/layout/master.tag b/standard/Design/multiplier/xor2/layout/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..431d8f043dced1a43a8f3662f1dfac94b229a641 --- /dev/null +++ b/standard/Design/multiplier/xor2/layout/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +layout.oa diff --git a/Design/multiplier/xor2/layout/thumbnail_128x128.png b/standard/Design/multiplier/xor2/layout/thumbnail_128x128.png similarity index 100% rename from Design/multiplier/xor2/layout/thumbnail_128x128.png rename to standard/Design/multiplier/xor2/layout/thumbnail_128x128.png diff --git a/Design/multiplier/xor2/schematic/data.dm b/standard/Design/multiplier/xor2/schematic/data.dm similarity index 100% rename from Design/multiplier/xor2/schematic/data.dm rename to standard/Design/multiplier/xor2/schematic/data.dm diff --git a/standard/Design/multiplier/xor2/schematic/master.tag b/standard/Design/multiplier/xor2/schematic/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..26be1bef2ea7f883db0d50576c31cb244b3b0d9f --- /dev/null +++ b/standard/Design/multiplier/xor2/schematic/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +sch.oa diff --git a/Design/multiplier/xor2/schematic/sch.oa b/standard/Design/multiplier/xor2/schematic/sch.oa similarity index 100% rename from Design/multiplier/xor2/schematic/sch.oa rename to standard/Design/multiplier/xor2/schematic/sch.oa diff --git a/Design/multiplier/xor2/schematic/sch.oa- b/standard/Design/multiplier/xor2/schematic/sch.oa- similarity index 100% rename from Design/multiplier/xor2/schematic/sch.oa- rename to standard/Design/multiplier/xor2/schematic/sch.oa- diff --git a/Design/multiplier/xor2/schematic/sch.oa.cdslck b/standard/Design/multiplier/xor2/schematic/sch.oa.cdslck similarity index 100% rename from Design/multiplier/xor2/schematic/sch.oa.cdslck rename to standard/Design/multiplier/xor2/schematic/sch.oa.cdslck diff --git a/standard/Design/multiplier/xor2/schematic/thumbnail_128x128.png b/standard/Design/multiplier/xor2/schematic/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..f7f3fefcb5be3ba83599ea916a3e9073c0023f70 Binary files /dev/null and b/standard/Design/multiplier/xor2/schematic/thumbnail_128x128.png differ diff --git a/standard/Design/multiplier/xor2/symbol/master.tag b/standard/Design/multiplier/xor2/symbol/master.tag new file mode 100644 index 0000000000000000000000000000000000000000..e1024da05678ababdb17d8f8ef60d53e9761add0 --- /dev/null +++ b/standard/Design/multiplier/xor2/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/standard/Design/multiplier/xor2/symbol/symbol.oa b/standard/Design/multiplier/xor2/symbol/symbol.oa new file mode 100644 index 0000000000000000000000000000000000000000..24d70b0bb42246af3eefbe91e31a9449204762f0 Binary files /dev/null and b/standard/Design/multiplier/xor2/symbol/symbol.oa differ diff --git a/standard/Design/multiplier/xor2/symbol/thumbnail_128x128.png b/standard/Design/multiplier/xor2/symbol/thumbnail_128x128.png new file mode 100644 index 0000000000000000000000000000000000000000..8e4f4fb4a56334bab9bb03a47fb352aeff29c48e Binary files /dev/null and b/standard/Design/multiplier/xor2/symbol/thumbnail_128x128.png differ diff --git a/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.control b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.control similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.control rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.control diff --git a/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.controlStatements b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.controlStatements new file mode 100644 index 0000000000000000000000000000000000000000..0f7e971d3963051d5ea68a80d77498dae352a08f --- /dev/null +++ b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.controlStatements @@ -0,0 +1,14 @@ +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.definitionFiles b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.definitionFiles similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.definitionFiles rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.definitionFiles diff --git a/Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.designVariables b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.designVariables similarity index 100% rename from Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.designVariables rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.designVariables diff --git a/Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.includedModels b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.includedModels similarity index 100% rename from Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.includedModels rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.includedModels diff --git a/Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.modelFiles b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.modelFiles similarity index 100% rename from Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.modelFiles rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.modelFiles diff --git a/Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.specialFilesInclude b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/.specialFilesInclude similarity index 100% rename from Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/.specialFilesInclude rename to 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Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/amap/top_level_map.port rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/amap/top_level_map.port diff --git a/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/artSimEnvLog b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/artSimEnvLog new file mode 100644 index 0000000000000000000000000000000000000000..1ee9ff5cc30e79777c3b49b6bc24f329576489af --- /dev/null +++ b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/netlist/artSimEnvLog @@ -0,0 +1,9 @@ +generate netlist... + ...successful. +compose simulator input file... + ...successful. +start simulator if needed... + ...successful. +simulate... +reading simulation data... + ...successful. diff --git a/Design/simulation/ADE_output/xor2_C1/xor2/spectre/extracted/netlist/control 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to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/extracted/psf/variables_file diff --git a/Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.and2.parameters b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.and2.parameters similarity index 100% rename from Design/simulation/ADE_output/and2_C3/and2/spectre/extracted/netlist/.and2.parameters rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.and2.parameters diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.control b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.control similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.control rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.control diff --git a/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.controlStatements b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.controlStatements new file mode 100644 index 0000000000000000000000000000000000000000..0f7e971d3963051d5ea68a80d77498dae352a08f --- /dev/null +++ b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.controlStatements @@ -0,0 +1,14 @@ +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +tran tran stop=30n write="spectre.ic" writefinal="spectre.fc" \ + annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.definitionFiles b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.definitionFiles similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.definitionFiles rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.definitionFiles diff --git a/Design/simulation/ADE_output/xor2_C2/xor2/spectre/extracted/netlist/.designVariables b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/.designVariables similarity index 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from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/xor2.inst rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/xor2.inst diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/xor2.net b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/xor2.net similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/xor2.net rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/amap/xor2.net diff --git a/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/artSimEnvLog b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/netlist/artSimEnvLog new file mode 100644 index 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standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.0.sig.tmp diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.1.sig.tmp b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.1.sig.tmp similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.1.sig.tmp rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.1.sig.tmp diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.dat b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.dat similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.dat rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.dat diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.sig b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.sig similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.sig rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.sig diff --git a/Design/simulation/ADE_output/xor2_C2/xor2/spectre/extracted/psf/tran.tran.sig.tmp b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.sig.tmp similarity index 100% rename from Design/simulation/ADE_output/xor2_C2/xor2/spectre/extracted/psf/tran.tran.sig.tmp rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/tran.tran.sig.tmp diff --git a/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/variables_file b/standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/variables_file similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/variables_file rename to standard/Design/simulation/ADE_output/4x4_multiplier/4X4_multiplier/spectre/schematic/psf/variables_file diff --git a/Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters b/standard/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters similarity index 100% rename from Design/simulation/ADE_output/4x4_multiplier_11100001/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters rename to standard/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/.4X4_multiplier.parameters diff --git a/standard/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/.control b/standard/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/.control new file mode 100755 index 0000000000000000000000000000000000000000..1beb90f7f38f765096259ec214ede2192c8d975e --- /dev/null +++ b/standard/Design/simulation/ADE_output/4x4_multiplier_00011110/4X4_multiplier/spectre/extracted/netlist/.control @@ -0,0 +1,4 @@ + #!/bin/sh +xargs cat > netlist < netlist < netlist < netlist < netlist < netlist < netlist < netlist < netlist < + +Transient Analysis `tran': time = (0 s -> 30 ns) +Generated with Qt + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + diff --git a/Design/simulation/trans_result/xor2_C1.grf b/standard/Design/simulation/trans_result/xor2_C1.grf similarity index 100% rename from Design/simulation/trans_result/xor2_C1.grf rename to standard/Design/simulation/trans_result/xor2_C1.grf diff --git a/Design/simulation/trans_result/xor2_C1.png b/standard/Design/simulation/trans_result/xor2_C1.png similarity index 100% rename from Design/simulation/trans_result/xor2_C1.png rename to standard/Design/simulation/trans_result/xor2_C1.png diff --git a/Design/simulation/trans_result/xor2_C2.grf b/standard/Design/simulation/trans_result/xor2_C2.grf similarity index 100% rename from Design/simulation/trans_result/xor2_C2.grf rename to standard/Design/simulation/trans_result/xor2_C2.grf diff --git a/Design/simulation/trans_result/xor2_C2.png b/standard/Design/simulation/trans_result/xor2_C2.png similarity index 100% rename from Design/simulation/trans_result/xor2_C2.png rename to standard/Design/simulation/trans_result/xor2_C2.png diff --git a/Design/simulation/trans_result/xor2_C3.grf b/standard/Design/simulation/trans_result/xor2_C3.grf similarity index 100% rename from Design/simulation/trans_result/xor2_C3.grf rename to standard/Design/simulation/trans_result/xor2_C3.grf diff --git a/Design/simulation/trans_result/xor2_C3.png b/standard/Design/simulation/trans_result/xor2_C3.png similarity index 100% rename from Design/simulation/trans_result/xor2_C3.png rename to standard/Design/simulation/trans_result/xor2_C3.png diff --git a/Report/IEEE_report/4x4_multiplier_design.aux b/standard/Report/IEEE_report/4x4_multiplier_design.aux similarity index 100% rename from Report/IEEE_report/4x4_multiplier_design.aux rename to standard/Report/IEEE_report/4x4_multiplier_design.aux diff --git a/Report/IEEE_report/4x4_multiplier_design.fdb_latexmk b/standard/Report/IEEE_report/4x4_multiplier_design.fdb_latexmk similarity index 84% rename from Report/IEEE_report/4x4_multiplier_design.fdb_latexmk rename to standard/Report/IEEE_report/4x4_multiplier_design.fdb_latexmk index 644e87e5674a88be58b9f147c007101f9757f46d..7ece13616ea59a9918b932d038f8b4980f6a098a 100644 --- a/Report/IEEE_report/4x4_multiplier_design.fdb_latexmk +++ b/standard/Report/IEEE_report/4x4_multiplier_design.fdb_latexmk @@ -1,9 +1,11 @@ # Fdb version 3 -["xdvipdfmx"] 1621788325 "/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/Report/IEEE_report/4x4_multiplier_design.xdv" "/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/Report/IEEE_report/4x4_multiplier_design.pdf" "/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/Report/IEEE_report/4x4_multiplier_design" 1621788373 - "/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS 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Design/Project/ee306-digital-cmos-design-project/standard/Report/IEEE_report/4x4_multiplier_design.xdv" "4x4_multiplier_design" 1622059586 "../../Design/Design_figures/4X4_Multiplier_layout.png" 1621771408 59550 e38cd0bd456ea03de05f45acded77903 "" "../../Design/Design_figures/4X4_Multiplier_schematic.png" 1621770783 45576 8bbd9ccb9003e8c93f652da2c64568f2 "" "../../Design/Design_figures/and2_schematic.png" 1621504991 16972 d595f2c31506f8f2e1bb83bf159ba1c2 "" @@ -34,8 +36,8 @@ "../figures/4x4_multiplier.png" 1621525808 139102 4a00213d9284ec36c10df21deca8bdbc "" "../figures/full_adder.jpeg" 1621527456 7090 942a2e701f6bf1a731c992bee183010d "" "../figures/half_adder.png" 1621526486 11442 c5e36ce07d8b51126ab5692a3837a47f "" - "/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/Report/IEEE_report/4x4_multiplier_design.aux" 1621788325 8719 874ddeb6a45f280285670604e1816f79 "" - "/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS 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LaTeX Font Info: Checking defaults for OML/cmm/m/it on input line 19. @@ -503,7 +503,7 @@ LaTeX Font Warning: Font shape `TU/ptm/b/n' undefined LaTeX Font Warning: Font shape `TU/ptm/b/n' undefined (Font) using `TU/ptm/bx/n' instead on input line 302. -[4] (/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/Report/IEEE_report/reference.tex) +[4] (/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/standard/Report/IEEE_report/reference.tex) File: ../../Design/simulation/trans_result/inv_C1.png Graphic file (type bmp) <../../Design/simulation/trans_result/inv_C1.png> File: ../../Design/simulation/trans_result/inv_C2.png Graphic file (type bmp) @@ -588,18 +588,18 @@ Before submitting the final camera ready copy, remember to: [6] [7 -] (/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/Report/IEEE_report/4x4_multiplier_design.aux) +] (/Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/standard/Report/IEEE_report/4x4_multiplier_design.aux) LaTeX Font Warning: Some font shapes were not available, defaults substituted. ) Here is how much of TeX's memory you used: 5375 strings out of 476919 - 93615 string characters out of 5821840 + 93759 string characters out of 5821840 401774 words of memory out of 5000000 25273 multiletter control sequences out of 15000+600000 415789 words of font info for 88 fonts, out of 8000000 for 9000 1348 hyphenation exceptions out of 8191 - 71i,11n,79p,1353b,295s stack positions out of 5000i,500n,10000p,200000b,80000s + 71i,11n,79p,1362b,295s stack positions out of 5000i,500n,10000p,200000b,80000s -Output written on /Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/Report/IEEE_report/4x4_multiplier_design.xdv (7 pages, 120964 bytes). +Output written on /Users/tongyuan/Documents/Study/S6_Spring_2021/CMOS Design/Project/ee306-digital-cmos-design-project/standard/Report/IEEE_report/4x4_multiplier_design.xdv (7 pages, 120964 bytes). diff --git a/Report/IEEE_report/4x4_multiplier_design.pdf b/standard/Report/IEEE_report/4x4_multiplier_design.pdf similarity index 99% rename from Report/IEEE_report/4x4_multiplier_design.pdf rename to standard/Report/IEEE_report/4x4_multiplier_design.pdf index 73cbf80ee85f543b9a761550d8f91998531f7104..6cab3ffbc556c08991ea154acab26bcb317fca6e 100644 Binary files a/Report/IEEE_report/4x4_multiplier_design.pdf and b/standard/Report/IEEE_report/4x4_multiplier_design.pdf differ diff --git a/standard/Report/IEEE_report/4x4_multiplier_design.synctex.gz b/standard/Report/IEEE_report/4x4_multiplier_design.synctex.gz new file mode 100644 index 0000000000000000000000000000000000000000..4e62c20c5f990f0c574cb5dce6911bd4d46b0f76 Binary files /dev/null and b/standard/Report/IEEE_report/4x4_multiplier_design.synctex.gz differ diff --git a/Report/IEEE_report/4x4_multiplier_design.tex b/standard/Report/IEEE_report/4x4_multiplier_design.tex similarity index 99% rename from Report/IEEE_report/4x4_multiplier_design.tex rename to standard/Report/IEEE_report/4x4_multiplier_design.tex index e9a01d6b0518c307e8bac7a74c2207399648f3d0..f507d5af18f1695ef3253d375c840edd82daedc3 100644 --- a/Report/IEEE_report/4x4_multiplier_design.tex +++ b/standard/Report/IEEE_report/4x4_multiplier_design.tex @@ -12,7 +12,7 @@ \usepackage{subfig} % \graphicspath{{../figures/}{../../Design/Design_figures}} \graphicspath{{../figures}{../../Design/Design_figures}{../../Design/simulation/trans_result}} - + \def\BibTeX{{\rm B\kern-.05em{\sc i\kern-.025em b}\kern-.08em T\kern-.1667em\lower.7ex\hbox{E}\kern-.125emX}} diff --git a/Report/IEEE_report/4x4_multiplier_design.xdv b/standard/Report/IEEE_report/4x4_multiplier_design.xdv similarity index 99% rename from Report/IEEE_report/4x4_multiplier_design.xdv rename to standard/Report/IEEE_report/4x4_multiplier_design.xdv index f5d46d0525637bef1fd4566d77b7702cae86da48..f943ad2707abe358a2eacab42d9401af82be7cf4 100644 Binary files a/Report/IEEE_report/4x4_multiplier_design.xdv and b/standard/Report/IEEE_report/4x4_multiplier_design.xdv differ diff --git a/standard/Report/IEEE_report/IEEEtran.cls b/standard/Report/IEEE_report/IEEEtran.cls new file mode 100644 index 0000000000000000000000000000000000000000..905a10cfa64cce2455923cd1989157405dca5f0d --- /dev/null +++ b/standard/Report/IEEE_report/IEEEtran.cls @@ -0,0 +1,6347 @@ +%% +%% IEEEtran.cls 2015/08/26 version V1.8b +%% +%% This is the IEEEtran LaTeX class for authors of the Institute of +%% Electrical and Electronics Engineers (IEEE) Transactions journals and +%% conferences. +%% +%% Support sites: +%% http://www.michaelshell.org/tex/ieeetran/ +%% http://www.ctan.org/pkg/ieeetran +%% and +%% http://www.ieee.org/ +%% +%% Based on the original 1993 IEEEtran.cls, but with many bug fixes +%% and enhancements (from both JVH and MDS) over the 1996/7 version. +%% +%% +%% Contributors: +%% Gerry Murray (1993), Silvano Balemi (1993), +%% Jon Dixon (1996), Peter N"uchter (1996), +%% Juergen von Hagen (2000), and Michael Shell (2001-2014) +%% +%% +%% Copyright (c) 1993-2000 by Gerry Murray, Silvano Balemi, +%% Jon Dixon, Peter N"uchter, +%% Juergen von Hagen +%% and +%% Copyright (c) 2001-2015 by Michael Shell +%% +%% Current maintainer (V1.3 to V1.8b): Michael Shell +%% See: +%% http://www.michaelshell.org/ +%% for current contact information. +%% +%% Special thanks to Peter Wilson (CUA) and Donald Arseneau +%% for allowing the inclusion of the \@ifmtarg command +%% from their ifmtarg LaTeX package. +%% +%%************************************************************************* +%% Legal Notice: +%% This code is offered as-is without any warranty either expressed or +%% implied; without even the implied warranty of MERCHANTABILITY or +%% FITNESS FOR A PARTICULAR PURPOSE! +%% User assumes all risk. +%% In no event shall the IEEE or any contributor to this code be liable for +%% any damages or losses, including, but not limited to, incidental, +%% consequential, or any other damages, resulting from the use or misuse +%% of any information contained here. +%% +%% All comments are the opinions of their respective authors and are not +%% necessarily endorsed by the IEEE. +%% +%% This work is distributed under the LaTeX Project Public License (LPPL) +%% ( http://www.latex-project.org/ ) version 1.3, and may be freely used, +%% distributed and modified. A copy of the LPPL, version 1.3, is included +%% in the base LaTeX documentation of all distributions of LaTeX released +%% 2003/12/01 or later. +%% Retain all contribution notices and credits. +%% ** Modified files should be clearly indicated as such, including ** +%% ** renaming them and changing author support contact information. ** +%% +%% File list of work: IEEEtran.cls, IEEEtran_HOWTO.pdf, bare_adv.tex, +%% bare_conf.tex, bare_jrnl.tex, bare_conf_compsoc.tex, +%% bare_jrnl_compsoc.tex +%% +%% Major changes to the user interface should be indicated by an +%% increase in the version numbers. If a version is a beta, it will +%% be indicated with a BETA suffix, i.e., 1.4 BETA. +%% Small changes can be indicated by appending letters to the version +%% such as "IEEEtran_v14a.cls". +%% In all cases, \Providesclass, any \typeout messages to the user, +%% \IEEEtransversionmajor and \IEEEtransversionminor must reflect the +%% correct version information. +%% The changes should also be documented via source comments. +%%************************************************************************* +%% +% +% Available class options +% e.g., \documentclass[10pt,conference]{IEEEtran} +% +% *** choose only one from each category *** +% +% 9pt, 10pt, 11pt, 12pt +% Sets normal font size. The default is 10pt. +% +% conference, journal, technote, peerreview, peerreviewca +% determines format mode - conference papers, journal papers, +% correspondence papers (technotes), or peer review papers. The user +% should also select 9pt when using technote. peerreview is like +% journal mode, but provides for a single-column "cover" title page for +% anonymous peer review. The paper title (without the author names) is +% repeated at the top of the page after the cover page. For peer review +% papers, the \IEEEpeerreviewmaketitle command must be executed (will +% automatically be ignored for non-peerreview modes) at the place the +% cover page is to end, usually just after the abstract (keywords are +% not normally used with peer review papers). peerreviewca is like +% peerreview, but allows the author names to be entered and formatted +% as with conference mode so that author affiliation and contact +% information can be easily seen on the cover page. +% The default is journal. +% +% draft, draftcls, draftclsnofoot, final +% determines if paper is formatted as a widely spaced draft (for +% handwritten editor comments) or as a properly typeset final version. +% draftcls restricts draft mode to the class file while all other LaTeX +% packages (i.e., \usepackage{graphicx}) will behave as final - allows +% for a draft paper with visible figures, etc. draftclsnofoot is like +% draftcls, but does not display the date and the word "DRAFT" at the foot +% of the pages. If using one of the draft modes, the user will probably +% also want to select onecolumn. +% The default is final. +% +% letterpaper, a4paper, cspaper +% determines paper size: 8.5in X 11in, 210mm X 297mm or 7.875in X 10.75in. +% Changing the paper size in the standard journal and conference modes +% will not alter the typesetting of the document - only the margins will +% be affected. In particular, documents using the a4paper option will +% have reduced side margins (A4 is narrower than US letter) and a longer +% bottom margin (A4 is longer than US letter). For both cases, the top +% margins will be the same and the text will be horizontally centered. +% For the compsoc conference and draft modes, it is the margins that will +% remain constant, and thus the text area size will vary, with changes in +% the paper size. +% The cspaper option is the special ``trim'' paper size (7.875in x 10.75in) +% used in the actual publication of Computer Society journals. Under +% compsoc journal mode, this option does not alter the typesetting of the +% document. Authors should invoke the cspaper option only if requested to +% do so by the editors of the specific journal they are submitting to. +% For final submission to the IEEE, authors should generally use US letter +% (8.5 X 11in) paper unless otherwise instructed. Note that authors should +% ensure that all post-processing (ps, pdf, etc.) uses the same paper +% specificiation as the .tex document. Problems here are by far the number +% one reason for incorrect margins. IEEEtran will automatically set the +% default paper size under pdflatex (without requiring any change to +% pdftex.cfg), so this issue is more important to dvips users. Fix +% config.ps, config.pdf, or ~/.dvipsrc for dvips, or use the +% dvips -t papersize option instead as needed. For the cspaper option, +% the corresponding dvips paper name is "ieeecs". +% See the testflow documentation +% http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/testflow +% for more details on dvips paper size configuration. +% The default is letterpaper. +% +% oneside, twoside +% determines if layout follows single sided or two sided (duplex) +% printing. The only notable change is with the headings at the top of +% the pages. +% The default is oneside. +% +% onecolumn, twocolumn +% determines if text is organized into one or two columns per page. One +% column mode is usually used only with draft papers. +% The default is twocolumn. +% +% comsoc, compsoc, transmag +% Use the format of the IEEE Communications Society, IEEE Computer Society +% or IEEE Transactions on Magnetics, respectively. +% +% romanappendices +% Use the "Appendix I" convention when numbering appendices. IEEEtran.cls +% now defaults to Alpha "Appendix A" convention - the opposite of what +% v1.6b and earlier did. +% +% captionsoff +% disables the display of the figure/table captions. Some IEEE journals +% request that captions be removed and figures/tables be put on pages +% of their own at the end of an initial paper submission. The endfloat +% package can be used with this class option to achieve this format. +% +% nofonttune +% turns off tuning of the font interword spacing. Maybe useful to those +% not using the standard Times fonts or for those who have already "tuned" +% their fonts. +% The default is to enable IEEEtran to tune font parameters. +% +% +%---------- +% Available CLASSINPUTs provided (all are macros unless otherwise noted): +% \CLASSINPUTbaselinestretch +% \CLASSINPUTinnersidemargin +% \CLASSINPUToutersidemargin +% \CLASSINPUTtoptextmargin +% \CLASSINPUTbottomtextmargin +% +% Available CLASSINFOs provided: +% \ifCLASSINFOpdf (TeX if conditional) +% \CLASSINFOpaperwidth (macro) +% \CLASSINFOpaperheight (macro) +% \CLASSINFOnormalsizebaselineskip (length) +% \CLASSINFOnormalsizeunitybaselineskip (length) +% +% Available CLASSOPTIONs provided: +% all class option flags (TeX if conditionals) unless otherwise noted, +% e.g., \ifCLASSOPTIONcaptionsoff +% point size options provided as a single macro: +% \CLASSOPTIONpt +% which will be defined as 9, 10, 11, or 12 depending on the document's +% normalsize point size. +% also, class option peerreviewca implies the use of class option peerreview +% and classoption draft implies the use of class option draftcls + + + + + +\ProvidesClass{IEEEtran}[2015/08/26 V1.8b by Michael Shell] +\typeout{-- See the "IEEEtran_HOWTO" manual for usage information.} +\typeout{-- http://www.michaelshell.org/tex/ieeetran/} +\NeedsTeXFormat{LaTeX2e} + +% IEEEtran.cls version numbers, provided as of V1.3 +% These values serve as a way a .tex file can +% determine if the new features are provided. +% The version number of this IEEEtrans.cls can be obtained from +% these values. i.e., V1.4 +% KEEP THESE AS INTEGERS! i.e., NO {4a} or anything like that- +% (no need to enumerate "a" minor changes here) +\def\IEEEtransversionmajor{1} +\def\IEEEtransversionminor{8} + + +% hook to allow easy changeover to IEEEtran.cls/tools.sty error reporting +\def\@IEEEclspkgerror{\ClassError{IEEEtran}} + + +% These do nothing, but provide them like in article.cls +\newif\if@restonecol +\newif\if@titlepage + + +% class option conditionals +\newif\ifCLASSOPTIONonecolumn \CLASSOPTIONonecolumnfalse +\newif\ifCLASSOPTIONtwocolumn \CLASSOPTIONtwocolumntrue + +\newif\ifCLASSOPTIONoneside \CLASSOPTIONonesidetrue +\newif\ifCLASSOPTIONtwoside \CLASSOPTIONtwosidefalse + +\newif\ifCLASSOPTIONfinal \CLASSOPTIONfinaltrue +\newif\ifCLASSOPTIONdraft \CLASSOPTIONdraftfalse +\newif\ifCLASSOPTIONdraftcls \CLASSOPTIONdraftclsfalse +\newif\ifCLASSOPTIONdraftclsnofoot \CLASSOPTIONdraftclsnofootfalse + +\newif\ifCLASSOPTIONpeerreview \CLASSOPTIONpeerreviewfalse +\newif\ifCLASSOPTIONpeerreviewca \CLASSOPTIONpeerreviewcafalse + +\newif\ifCLASSOPTIONjournal \CLASSOPTIONjournaltrue +\newif\ifCLASSOPTIONconference \CLASSOPTIONconferencefalse +\newif\ifCLASSOPTIONtechnote \CLASSOPTIONtechnotefalse + +\newif\ifCLASSOPTIONnofonttune \CLASSOPTIONnofonttunefalse + +\newif\ifCLASSOPTIONcaptionsoff \CLASSOPTIONcaptionsofffalse + +\newif\ifCLASSOPTIONcomsoc \CLASSOPTIONcomsocfalse +\newif\ifCLASSOPTIONcompsoc \CLASSOPTIONcompsocfalse +\newif\ifCLASSOPTIONtransmag \CLASSOPTIONtransmagfalse + +\newif\ifCLASSOPTIONromanappendices \CLASSOPTIONromanappendicesfalse + + +% class info conditionals + +% indicates if pdf (via pdflatex) output +\newif\ifCLASSINFOpdf \CLASSINFOpdffalse + + +% V1.6b internal flag to show if using a4paper +\newif\if@IEEEusingAfourpaper \@IEEEusingAfourpaperfalse +% V1.6b internal flag to show if using cspaper +\newif\if@IEEEusingcspaper \@IEEEusingcspaperfalse + + +% IEEEtran class scratch pad registers +% dimen +\newdimen\@IEEEtrantmpdimenA +\newdimen\@IEEEtrantmpdimenB +\newdimen\@IEEEtrantmpdimenC +% count +\newcount\@IEEEtrantmpcountA +\newcount\@IEEEtrantmpcountB +\newcount\@IEEEtrantmpcountC +% token list +\newtoks\@IEEEtrantmptoksA + +% we use \CLASSOPTIONpt so that we can ID the point size (even for 9pt docs) +% as well as LaTeX's \@ptsize to retain some compatability with some +% external packages +\def\@ptsize{0} +% LaTeX does not support 9pt, so we set \@ptsize to 0 - same as that of 10pt +\DeclareOption{9pt}{\def\CLASSOPTIONpt{9}\def\@ptsize{0}} +\DeclareOption{10pt}{\def\CLASSOPTIONpt{10}\def\@ptsize{0}} +\DeclareOption{11pt}{\def\CLASSOPTIONpt{11}\def\@ptsize{1}} +\DeclareOption{12pt}{\def\CLASSOPTIONpt{12}\def\@ptsize{2}} + + + +\DeclareOption{letterpaper}{\setlength{\paperwidth}{8.5in}% + \setlength{\paperheight}{11in}% + \@IEEEusingAfourpaperfalse + \@IEEEusingcspaperfalse + \def\CLASSOPTIONpaper{letter}% + \def\CLASSINFOpaperwidth{8.5in}% + \def\CLASSINFOpaperheight{11in}} + + +\DeclareOption{a4paper}{\setlength{\paperwidth}{210mm}% + \setlength{\paperheight}{297mm}% + \@IEEEusingAfourpapertrue + \@IEEEusingcspaperfalse + \def\CLASSOPTIONpaper{a4}% + \def\CLASSINFOpaperwidth{210mm}% + \def\CLASSINFOpaperheight{297mm}} + +% special paper option for compsoc journals +\DeclareOption{cspaper}{\setlength{\paperwidth}{7.875in}% + \setlength{\paperheight}{10.75in}% + \@IEEEusingcspapertrue + \@IEEEusingAfourpaperfalse + \def\CLASSOPTIONpaper{ieeecs}% + \def\CLASSINFOpaperwidth{7.875in}% + \def\CLASSINFOpaperheight{10.75in}} + +\DeclareOption{oneside}{\@twosidefalse\@mparswitchfalse + \CLASSOPTIONonesidetrue\CLASSOPTIONtwosidefalse} +\DeclareOption{twoside}{\@twosidetrue\@mparswitchtrue + \CLASSOPTIONtwosidetrue\CLASSOPTIONonesidefalse} + +\DeclareOption{onecolumn}{\CLASSOPTIONonecolumntrue\CLASSOPTIONtwocolumnfalse} +\DeclareOption{twocolumn}{\CLASSOPTIONtwocolumntrue\CLASSOPTIONonecolumnfalse} + +% If the user selects draft, then this class AND any packages +% will go into draft mode. +\DeclareOption{draft}{\CLASSOPTIONdrafttrue\CLASSOPTIONdraftclstrue + \CLASSOPTIONdraftclsnofootfalse} +% draftcls is for a draft mode which will not affect any packages +% used by the document. +\DeclareOption{draftcls}{\CLASSOPTIONdraftfalse\CLASSOPTIONdraftclstrue + \CLASSOPTIONdraftclsnofootfalse} +% draftclsnofoot is like draftcls, but without the footer. +\DeclareOption{draftclsnofoot}{\CLASSOPTIONdraftfalse\CLASSOPTIONdraftclstrue + \CLASSOPTIONdraftclsnofoottrue} +\DeclareOption{final}{\CLASSOPTIONdraftfalse\CLASSOPTIONdraftclsfalse + \CLASSOPTIONdraftclsnofootfalse} + +\DeclareOption{journal}{\CLASSOPTIONpeerreviewfalse\CLASSOPTIONpeerreviewcafalse + \CLASSOPTIONjournaltrue\CLASSOPTIONconferencefalse\CLASSOPTIONtechnotefalse} + +\DeclareOption{conference}{\CLASSOPTIONpeerreviewfalse\CLASSOPTIONpeerreviewcafalse + \CLASSOPTIONjournalfalse\CLASSOPTIONconferencetrue\CLASSOPTIONtechnotefalse} + +\DeclareOption{technote}{\CLASSOPTIONpeerreviewfalse\CLASSOPTIONpeerreviewcafalse + \CLASSOPTIONjournalfalse\CLASSOPTIONconferencefalse\CLASSOPTIONtechnotetrue} + +\DeclareOption{peerreview}{\CLASSOPTIONpeerreviewtrue\CLASSOPTIONpeerreviewcafalse + \CLASSOPTIONjournalfalse\CLASSOPTIONconferencefalse\CLASSOPTIONtechnotefalse} + +\DeclareOption{peerreviewca}{\CLASSOPTIONpeerreviewtrue\CLASSOPTIONpeerreviewcatrue + \CLASSOPTIONjournalfalse\CLASSOPTIONconferencefalse\CLASSOPTIONtechnotefalse} + +\DeclareOption{nofonttune}{\CLASSOPTIONnofonttunetrue} + +\DeclareOption{captionsoff}{\CLASSOPTIONcaptionsofftrue} + +\DeclareOption{comsoc}{\CLASSOPTIONcomsoctrue\CLASSOPTIONcompsocfalse\CLASSOPTIONtransmagfalse} + +\DeclareOption{compsoc}{\CLASSOPTIONcomsocfalse\CLASSOPTIONcompsoctrue\CLASSOPTIONtransmagfalse} + +\DeclareOption{transmag}{\CLASSOPTIONtransmagtrue\CLASSOPTIONcomsocfalse\CLASSOPTIONcompsocfalse} + +\DeclareOption{romanappendices}{\CLASSOPTIONromanappendicestrue} + + +% default to US letter paper, 10pt, twocolumn, one sided, final, journal +\ExecuteOptions{letterpaper,10pt,twocolumn,oneside,final,journal} +% overrride these defaults per user requests +\ProcessOptions + + + +%% -- Command Argument Scanning Support Functions -- + +% Sets the category codes for punctuation to their normal values. +% For local use with argument scanning. +\def\IEEEnormalcatcodespunct{\catcode`\!=12 \catcode`\,=12 \catcode`\:=12 +\catcode`\;=12 \catcode`\`=12 \catcode`\'=12 \catcode`\"=12 \catcode`\.=12 +\catcode`\/=12 \catcode`\?=12 \catcode`\*=12 \catcode`\+=12 \catcode`\-=12 +\catcode`\<=12 \catcode`\>=12 \catcode`\(=12 \catcode`\)=12 \catcode`\[=12 +\catcode`\]=12 \catcode`\==12 \catcode`\|=12} +% Sets the category codes for numbers to their normal values. +% For local use with argument scanning. +\def\IEEEnormalcatcodesnum{\catcode`\0=12 \catcode`\1=12 \catcode`\2=12 +\catcode`\3=12 \catcode`\4=12 \catcode`\5=12 \catcode`\6=12 \catcode`\7=12 +\catcode`\8=12 \catcode`\9=12} +% combined action of \IEEEnormalcatcodespunct and \IEEEnormalcatcodesnum +\def\IEEEnormalcatcodes{\IEEEnormalcatcodespunct\IEEEnormalcatcodesnum} + + +% usage: \@IEEEextracttoken*{} +% \@IEEEextracttoken fully expands its argument (which it then stores in +% \@IEEEextracttokenarg) via \edef and then the meaning of the first +% nonbrace (but including the empty group) token found is assigned via \let +% to \@IEEEextractedtoken as well as stored in the macro +% \@IEEEextractedtokenmacro. Tokens that would otherwise be discarded during +% the acquisition of the first are stored in \@IEEEextractedtokensdiscarded, +% however their original relative brace nesting depths are not guaranteed to +% be preserved. +% If the argument is empty, or if a first nonbrace token does not exist (or +% is an empty group), \@IEEEextractedtoken will be \relax and +% \@IEEEextractedtokenmacro and \@IEEEextractedtokensdiscarded will be empty. +% +% For example: +% \@IEEEextracttoken{{{ab}{cd}}{{ef}g}} +% results in: +% +% \@IEEEextracttokenarg ==> a macro containing {{ab}{cd}}{{ef}g} +% \@IEEEextractedtoken ==> the letter a +% \@IEEEextractedtokenmacro ==> a macro containing a +% \@IEEEextractedtokensdiscarded ==> a macro containing bcd{ef}g +% +% the *-star form, \@IEEEextracttoken*, does not expand its argument +% contents during processing. +\def\@IEEEextracttoken{\@ifstar{\let\@IEEEextracttokendef=\def\@@IEEEextracttoken}{\let\@IEEEextracttokendef=\edef\@@IEEEextracttoken}} + +\def\@@IEEEextracttoken#1{\@IEEEextracttokendef\@IEEEextracttokenarg{#1}\relax +\def\@IEEEextractedtokensdiscarded{}\relax % initialize to empty +% if the macro is unchanged after being acquired as a single undelimited argument +% with anything after it being stripped off as a delimited argument +% we know we have one token without any enclosing braces. loop until this is true. +\let\@IEEEextracttokencurgroup\@IEEEextracttokenarg +\loop + % trap case of an empty argument as this would cause a problem with + % \@@@IEEEextracttoken's first (nondelimited) argument acquisition + \ifx\@IEEEextracttokencurgroup\@empty + \def\@IEEEextractedtokenmacro{}\relax + \else + \expandafter\@@@IEEEextracttoken\@IEEEextracttokencurgroup\@IEEEgeneralsequenceDELIMITER\relax + \fi + \ifx\@IEEEextractedtokenmacro\@IEEEextracttokencurgroup + \else + \let\@IEEEextracttokencurgroup=\@IEEEextractedtokenmacro +\repeat +% we can safely do a \let= here because there should be at most one token +% the relax is needed to handle the case of no token found +\expandafter\let\expandafter\@IEEEextractedtoken\@IEEEextractedtokenmacro\relax} + +\def\@@@IEEEextracttoken#1#2\@IEEEgeneralsequenceDELIMITER{\def\@IEEEextractedtokenmacro{#1}\relax +\def\@@IEEEextractedtokensdiscarded{#2}\expandafter\expandafter\expandafter\def\expandafter\expandafter\expandafter +\@IEEEextractedtokensdiscarded\expandafter\expandafter\expandafter +{\expandafter\@@IEEEextractedtokensdiscarded\@IEEEextractedtokensdiscarded}} +%% +%% -- End of Command Argument Scanning Support Functions -- + + + +% Computer Society conditional execution command +\long\def\@IEEEcompsoconly#1{\relax\ifCLASSOPTIONcompsoc\relax#1\relax\fi\relax} +% inverse +\long\def\@IEEEnotcompsoconly#1{\relax\ifCLASSOPTIONcompsoc\else\relax#1\relax\fi\relax} +% compsoc conference +\long\def\@IEEEcompsocconfonly#1{\relax\ifCLASSOPTIONcompsoc\ifCLASSOPTIONconference\relax#1\relax\fi\fi\relax} +% compsoc not conference +\long\def\@IEEEcompsocnotconfonly#1{\relax\ifCLASSOPTIONcompsoc\ifCLASSOPTIONconference\else\relax#1\relax\fi\fi\relax} + + +% comsoc verify that newtxmath, mtpro2, mt11p or mathtime has been loaded +\def\@IEEEcomsocverifymathfont{\typeout{-- Verifying Times compatible math font.}\relax + \@ifpackageloaded{newtxmath}{\typeout{-- newtxmath loaded, OK.}}{\@@IEEEcomsocverifymathfont}} +\def\@@IEEEcomsocverifymathfont{\@ifpackageloaded{mtpro2}{\typeout{-- mtpro2 loaded, OK.}}{\@@@IEEEcomsocverifymathfont}} +\def\@@@IEEEcomsocverifymathfont{\@ifpackageloaded{mt11p}{\typeout{-- mt11p2 loaded, OK.}}{\@@@@IEEEcomsocverifymathfont}} +\def\@@@@IEEEcomsocverifymathfont{\@ifpackageloaded{mathtime}{\typeout{-- mathtime loaded, OK.}}{\@IEEEcomsocenforcemathfont}} + +% comsoc, if a Times math font was not loaded by user, enforce it +\def\@IEEEcomsocenforcemathfont{\typeout{** Times compatible math font not found, forcing.}\relax +\IfFileExists{newtxmath.sty}{\typeout{-- Found newtxmath, loading.}\RequirePackage{newtxmath}}{\@@IEEEcomsocenforcemathfont}} +\def\@@IEEEcomsocenforcemathfont{\IfFileExists{mtpro2.sty}{\typeout{-- Found mtpro2, loading.}\RequirePackage{mtpro2}}{\@@@IEEEcomsocenforcemathfont}} +\def\@@@IEEEcomsocenforcemathfont{\IfFileExists{mt11p.sty}{\typeout{-- Found mt11p, loading.}\RequirePackage{mt11p}}{\@@@@IEEEcomsocenforcemathfont}} +\def\@@@@IEEEcomsocenforcemathfont{\IfFileExists{mathtime.sty}{\typeout{-- Found mathtime, loading.}\RequirePackage{mathtime}}{\@@@@@IEEEcomsocenforcemathfont}} +% if no acceptable Times math font package found, error with newtxmath requirement +\def\@@@@@IEEEcomsocenforcemathfont{\typeout{** No Times compatible math font package found. newtxmath is required.}\RequirePackage{newtxmath}} + + +\ifCLASSOPTIONcomsoc + % ensure that if newtxmath is used, the cmintegrals option is also invoked + \PassOptionsToPackage{cmintegrals}{newtxmath} + % comsoc requires a Times like math font + % ensure this requirement is satisfied at document start + \AtBeginDocument{\@IEEEcomsocverifymathfont} +\fi + + + +% The IEEE uses Times Roman font, so we'll default to Times. +% These three commands make up the entire times.sty package. +\renewcommand{\sfdefault}{phv} +\renewcommand{\rmdefault}{ptm} +\renewcommand{\ttdefault}{pcr} + +% V1.7 compsoc nonconference papers, use Palatino/Palladio as the main text font, +% not Times Roman. +\@IEEEcompsocnotconfonly{\renewcommand{\rmdefault}{ppl}} + +% enable the selected main text font +\normalfont\selectfont + + +\ifCLASSOPTIONcomsoc + \typeout{-- Using IEEE Communications Society mode.} +\fi + +\ifCLASSOPTIONcompsoc + \typeout{-- Using IEEE Computer Society mode.} +\fi + + +% V1.7 conference notice message hook +\def\@IEEEconsolenoticeconference{\typeout{}% +\typeout{** Conference Paper **}% +\typeout{Before submitting the final camera ready copy, remember to:}% +\typeout{}% +\typeout{ 1. Manually equalize the lengths of two columns on the last page}% +\typeout{ of your paper;}% +\typeout{}% +\typeout{ 2. Ensure that any PostScript and/or PDF output post-processing}% +\typeout{ uses only Type 1 fonts and that every step in the generation}% +\typeout{ process uses the appropriate paper size.}% +\typeout{}} + + +% we can send console reminder messages to the user here +\AtEndDocument{\ifCLASSOPTIONconference\@IEEEconsolenoticeconference\fi} + + +% warn about the use of single column other than for draft mode +\ifCLASSOPTIONtwocolumn\else% + \ifCLASSOPTIONdraftcls\else% + \typeout{** ATTENTION: Single column mode is not typically used with IEEE publications.}% + \fi% +\fi + + +% V1.7 improved paper size setting code. +% Set pdfpage and dvips paper sizes. Conditional tests are similar to that +% of ifpdf.sty. Retain within {} to ensure tested macros are never altered, +% even if only effect is to set them to \relax. +% if \pdfoutput is undefined or equal to relax, output a dvips special +{\@ifundefined{pdfoutput}{\AtBeginDvi{\special{papersize=\CLASSINFOpaperwidth,\CLASSINFOpaperheight}}}{% +% pdfoutput is defined and not equal to \relax +% check for pdfpageheight existence just in case someone sets pdfoutput +% under non-pdflatex. If exists, set them regardless of value of \pdfoutput. +\@ifundefined{pdfpageheight}{\relax}{\global\pdfpagewidth\paperwidth +\global\pdfpageheight\paperheight}% +% if using \pdfoutput=0 under pdflatex, send dvips papersize special +\ifcase\pdfoutput +\AtBeginDvi{\special{papersize=\CLASSINFOpaperwidth,\CLASSINFOpaperheight}}% +\else +% we are using pdf output, set CLASSINFOpdf flag +\global\CLASSINFOpdftrue +\fi}} + +% let the user know the selected papersize +\typeout{-- Using \CLASSINFOpaperwidth\space x \CLASSINFOpaperheight\space +(\CLASSOPTIONpaper)\space paper.} + +\ifCLASSINFOpdf +\typeout{-- Using PDF output.} +\else +\typeout{-- Using DVI output.} +\fi + + +% The idea hinted here is for LaTeX to generate markleft{} and markright{} +% automatically for you after you enter \author{}, \journal{}, +% \journaldate{}, journalvol{}, \journalnum{}, etc. +% However, there may be some backward compatibility issues here as +% well as some special applications for IEEEtran.cls and special issues +% that may require the flexible \markleft{}, \markright{} and/or \markboth{}. +% We'll leave this as an open future suggestion. +%\newcommand{\journal}[1]{\def\@journal{#1}} +%\def\@journal{} + + + +% pointsize values +% used with ifx to determine the document's normal size +\def\@IEEEptsizenine{9} +\def\@IEEEptsizeten{10} +\def\@IEEEptsizeeleven{11} +\def\@IEEEptsizetwelve{12} + + + +% FONT DEFINITIONS (No sizexx.clo file needed) +% V1.6 revised font sizes, displayskip values and +% revised normalsize baselineskip to reduce underfull vbox problems +% on the 58pc = 696pt = 9.5in text height we want +% normalsize #lines/column baselineskip (aka leading) +% 9pt 63 11.0476pt (truncated down) +% 10pt 58 12pt (exact) +% 11pt 52 13.3846pt (truncated down) +% 12pt 50 13.92pt (exact) +% + +% we need to store the nominal baselineskip for the given font size +% in case baselinestretch ever changes. +% this is a dimen, so it will not hold stretch or shrink +\newdimen\@IEEEnormalsizeunitybaselineskip +\@IEEEnormalsizeunitybaselineskip\baselineskip + + + +%% ******* WARNING! ******* +%% +%% Authors should not alter font sizes, baselineskip ("leading"), +%% margins or other spacing values in an attempt to squeeze more +%% material on each page. +%% +%% The IEEE's own typesetting software will restore the correct +%% values when re-typesetting/proofing the submitted document, +%% possibly resulting in unexpected article over length charges. +%% +%% ******* WARNING! ******* + + +% 9pt option defaults +\ifx\CLASSOPTIONpt\@IEEEptsizenine +\typeout{-- This is a 9 point document.} +\def\normalsize{\@setfontsize{\normalsize}{9}{11.0476pt}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{11.0476pt} +\normalsize +\abovedisplayskip 1.5ex plus 3pt minus 1pt +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 3pt +\belowdisplayshortskip 1.5ex plus 3pt minus 1pt +\def\small{\@setfontsize{\small}{8.5}{10pt}} +\def\footnotesize{\@setfontsize{\footnotesize}{8}{9pt}} +\def\scriptsize{\@setfontsize{\scriptsize}{7}{8pt}} +\def\tiny{\@setfontsize{\tiny}{5}{6pt}} +% sublargesize is the same as large - 10pt +\def\sublargesize{\@setfontsize{\sublargesize}{10}{12pt}} +\def\large{\@setfontsize{\large}{10}{12pt}} +\def\Large{\@setfontsize{\Large}{12}{14pt}} +\def\LARGE{\@setfontsize{\LARGE}{14}{17pt}} +\def\huge{\@setfontsize{\huge}{17}{20pt}} +\def\Huge{\@setfontsize{\Huge}{20}{24pt}} +\fi +% +% 10pt option defaults +\ifx\CLASSOPTIONpt\@IEEEptsizeten +\typeout{-- This is a 10 point document.} +\def\normalsize{\@setfontsize{\normalsize}{10}{12.00pt}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{12pt} +\normalsize +\abovedisplayskip 1.5ex plus 4pt minus 2pt +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 4pt +\belowdisplayshortskip 1.5ex plus 4pt minus 2pt +\def\small{\@setfontsize{\small}{9}{10pt}} +\def\footnotesize{\@setfontsize{\footnotesize}{8}{9pt}} +\def\scriptsize{\@setfontsize{\scriptsize}{7}{8pt}} +\def\tiny{\@setfontsize{\tiny}{5}{6pt}} +% sublargesize is a tad smaller than large - 11pt +\def\sublargesize{\@setfontsize{\sublargesize}{11}{13.4pt}} +\def\large{\@setfontsize{\large}{12}{14pt}} +\def\Large{\@setfontsize{\Large}{14}{17pt}} +\def\LARGE{\@setfontsize{\LARGE}{17}{20pt}} +\def\huge{\@setfontsize{\huge}{20}{24pt}} +\def\Huge{\@setfontsize{\Huge}{24}{28pt}} +\fi +% +% 11pt option defaults +\ifx\CLASSOPTIONpt\@IEEEptsizeeleven +\typeout{-- This is an 11 point document.} +\def\normalsize{\@setfontsize{\normalsize}{11}{13.3846pt}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{13.3846pt} +\normalsize +\abovedisplayskip 1.5ex plus 5pt minus 3pt +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 5pt +\belowdisplayshortskip 1.5ex plus 5pt minus 3pt +\def\small{\@setfontsize{\small}{10}{12pt}} +\def\footnotesize{\@setfontsize{\footnotesize}{9}{10.5pt}} +\def\scriptsize{\@setfontsize{\scriptsize}{8}{9pt}} +\def\tiny{\@setfontsize{\tiny}{6}{7pt}} +% sublargesize is the same as large - 12pt +\def\sublargesize{\@setfontsize{\sublargesize}{12}{14pt}} +\def\large{\@setfontsize{\large}{12}{14pt}} +\def\Large{\@setfontsize{\Large}{14}{17pt}} +\def\LARGE{\@setfontsize{\LARGE}{17}{20pt}} +\def\huge{\@setfontsize{\huge}{20}{24pt}} +\def\Huge{\@setfontsize{\Huge}{24}{28pt}} +\fi +% +% 12pt option defaults +\ifx\CLASSOPTIONpt\@IEEEptsizetwelve +\typeout{-- This is a 12 point document.} +\def\normalsize{\@setfontsize{\normalsize}{12}{13.92pt}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{13.92pt} +\normalsize +\abovedisplayskip 1.5ex plus 6pt minus 4pt +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 6pt +\belowdisplayshortskip 1.5ex plus 6pt minus 4pt +\def\small{\@setfontsize{\small}{10}{12pt}} +\def\footnotesize{\@setfontsize{\footnotesize}{9}{10.5pt}} +\def\scriptsize{\@setfontsize{\scriptsize}{8}{9pt}} +\def\tiny{\@setfontsize{\tiny}{6}{7pt}} +% sublargesize is the same as large - 14pt +\def\sublargesize{\@setfontsize{\sublargesize}{14}{17pt}} +\def\large{\@setfontsize{\large}{14}{17pt}} +\def\Large{\@setfontsize{\Large}{17}{20pt}} +\def\LARGE{\@setfontsize{\LARGE}{20}{24pt}} +\def\huge{\@setfontsize{\huge}{22}{26pt}} +\def\Huge{\@setfontsize{\Huge}{24}{28pt}} +\fi + + + +% V1.8a compsoc font sizes +% compsoc font sizes use bp "Postscript" point units (1/72in) +% rather than the traditional pt (1/72.27) +\ifCLASSOPTIONcompsoc +% -- compsoc defaults -- +% ** will override some of these values later ** +% 9pt +\ifx\CLASSOPTIONpt\@IEEEptsizenine +\def\normalsize{\@setfontsize{\normalsize}{9bp}{11bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{11bp} +\normalsize +\abovedisplayskip 1.5ex plus 3bp minus 1bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0bp plus 3bp +\belowdisplayshortskip 1.5ex plus 3bp minus 1bp +\def\small{\@setfontsize{\small}{8.5bp}{10bp}} +\def\footnotesize{\@setfontsize{\footnotesize}{8bp}{9bp}} +\def\scriptsize{\@setfontsize{\scriptsize}{7bp}{8bp}} +\def\tiny{\@setfontsize{\tiny}{5bp}{6bp}} +% sublargesize is the same as large - 10bp +\def\sublargesize{\@setfontsize{\sublargesize}{10bp}{12bp}} +\def\large{\@setfontsize{\large}{10bp}{12bp}} +\def\Large{\@setfontsize{\Large}{12bp}{14bp}} +\def\LARGE{\@setfontsize{\LARGE}{14bp}{17bp}} +\def\huge{\@setfontsize{\huge}{17bp}{20bp}} +\def\Huge{\@setfontsize{\Huge}{20bp}{24bp}} +\fi +% +% 10pt +\ifx\CLASSOPTIONpt\@IEEEptsizeten +\def\normalsize{\@setfontsize{\normalsize}{10bp}{12bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{12bp} +\normalsize +\abovedisplayskip 1.5ex plus 4bp minus 2bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 4bp +\belowdisplayshortskip 1.5ex plus 4bp minus 2bp +\def\small{\@setfontsize{\small}{9bp}{10bp}} +\def\footnotesize{\@setfontsize{\footnotesize}{8bp}{9bp}} +\def\scriptsize{\@setfontsize{\scriptsize}{7bp}{8bp}} +\def\tiny{\@setfontsize{\tiny}{5bp}{6bp}} +% sublargesize is a tad smaller than large - 11bp +\def\sublargesize{\@setfontsize{\sublargesize}{11bp}{13.5bp}} +\def\large{\@setfontsize{\large}{12bp}{14bp}} +\def\Large{\@setfontsize{\Large}{14bp}{17bp}} +\def\LARGE{\@setfontsize{\LARGE}{17bp}{20bp}} +\def\huge{\@setfontsize{\huge}{20bp}{24bp}} +\def\Huge{\@setfontsize{\Huge}{24bp}{28bp}} +\fi +% +% 11pt +\ifx\CLASSOPTIONpt\@IEEEptsizeeleven +\def\normalsize{\@setfontsize{\normalsize}{11bp}{13.5bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{13.5bp} +\normalsize +\abovedisplayskip 1.5ex plus 5bp minus 3bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 5bp +\belowdisplayshortskip 1.5ex plus 5bp minus 3bp +\def\small{\@setfontsize{\small}{10bp}{12bp}} +\def\footnotesize{\@setfontsize{\footnotesize}{9bp}{10.5bp}} +\def\scriptsize{\@setfontsize{\scriptsize}{8bp}{9bp}} +\def\tiny{\@setfontsize{\tiny}{6bp}{7bp}} +% sublargesize is the same as large - 12bp +\def\sublargesize{\@setfontsize{\sublargesize}{12bp}{14bp}} +\def\large{\@setfontsize{\large}{12bp}{14bp}} +\def\Large{\@setfontsize{\Large}{14bp}{17bp}} +\def\LARGE{\@setfontsize{\LARGE}{17bp}{20bp}} +\def\huge{\@setfontsize{\huge}{20bp}{24bp}} +\def\Huge{\@setfontsize{\Huge}{24bp}{28bp}} +\fi +% +% 12pt +\ifx\CLASSOPTIONpt\@IEEEptsizetwelve +\def\normalsize{\@setfontsize{\normalsize}{12bp}{14bp}}% +\setlength{\@IEEEnormalsizeunitybaselineskip}{14bp}% +\normalsize +\abovedisplayskip 1.5ex plus 6bp minus 4bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 6bp +\belowdisplayshortskip 1.5ex plus 6bp minus 4bp +\def\small{\@setfontsize{\small}{10bp}{12bp}} +\def\footnotesize{\@setfontsize{\footnotesize}{9bp}{10.5bp}} +\def\scriptsize{\@setfontsize{\scriptsize}{8bp}{9bp}} +\def\tiny{\@setfontsize{\tiny}{6bp}{7bp}} +% sublargesize is the same as large - 14bp +\def\sublargesize{\@setfontsize{\sublargesize}{14bp}{17bp}} +\def\large{\@setfontsize{\large}{14bp}{17bp}} +\def\Large{\@setfontsize{\Large}{17bp}{20bp}} +\def\LARGE{\@setfontsize{\LARGE}{20bp}{24bp}} +\def\huge{\@setfontsize{\huge}{22bp}{26bp}} +\def\Huge{\@setfontsize{\Huge}{24bp}{28bp}} +\fi +% +% -- override defaults: compsoc journals use special normalsizes -- +\ifCLASSOPTIONconference +% +% compsoc conferences +% 9pt +\ifx\CLASSOPTIONpt\@IEEEptsizenine +\def\normalsize{\@setfontsize{\normalsize}{9bp}{10.8bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{10.8bp} +\normalsize +\abovedisplayskip 1.5ex plus 3bp minus 1bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0bp plus 3bp +\belowdisplayshortskip 1.5ex plus 3bp minus 1bp +\fi +% 10pt +\ifx\CLASSOPTIONpt\@IEEEptsizeten +\def\normalsize{\@setfontsize{\normalsize}{10bp}{11.2bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{11.2bp} +\normalsize +\abovedisplayskip 1.5ex plus 4bp minus 2bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 4bp +\belowdisplayshortskip 1.5ex plus 4bp minus 2bp +\fi +% 11pt +\ifx\CLASSOPTIONpt\@IEEEptsizeeleven +\def\normalsize{\@setfontsize{\normalsize}{11bp}{13.2bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{13.2bp} +\normalsize +\abovedisplayskip 1.5ex plus 5bp minus 3bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 5bp +\belowdisplayshortskip 1.5ex plus 5bp minus 3bp +\fi +% 12pt +\ifx\CLASSOPTIONpt\@IEEEptsizetwelve +\def\normalsize{\@setfontsize{\normalsize}{12bp}{14.4bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{14.4bp} +\normalsize +\abovedisplayskip 1.5ex plus 6bp minus 4bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 6bp +\belowdisplayshortskip 1.5ex plus 6bp minus 4bp +\fi +% +% compsoc nonconferences +\else +% 9pt +\ifx\CLASSOPTIONpt\@IEEEptsizenine +\def\normalsize{\@setfontsize{\normalsize}{9bp}{10.8bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{10.8bp} +\normalsize +\abovedisplayskip 1.5ex plus 3bp minus 1bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0bp plus 3bp +\belowdisplayshortskip 1.5ex plus 3bp minus 1bp +\fi +% 10pt +\ifx\CLASSOPTIONpt\@IEEEptsizeten +% the official spec is 9.5bp with 11.4bp leading for 10pt, +% but measurements of proofs suggest upto 11.723bp leading +% here we'll use 11.54bp which gives 61 lines per column +% with the standard compsoc margins +\def\normalsize{\@setfontsize{\normalsize}{9.5bp}{11.54bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{11.54bp} +\normalsize +\abovedisplayskip 1.5ex plus 4bp minus 2bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 4bp +\belowdisplayshortskip 1.5ex plus 4bp minus 2bp +\fi +% 11pt +\ifx\CLASSOPTIONpt\@IEEEptsizeeleven +\def\normalsize{\@setfontsize{\normalsize}{11bp}{13.2bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{13.2bp} +\normalsize +\abovedisplayskip 1.5ex plus 5bp minus 3bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 5bp +\belowdisplayshortskip 1.5ex plus 5bp minus 3bp +\fi +% 12pt +\ifx\CLASSOPTIONpt\@IEEEptsizetwelve +\def\normalsize{\@setfontsize{\normalsize}{12bp}{14.4bp}} +\setlength{\@IEEEnormalsizeunitybaselineskip}{14.4bp} +\normalsize +\abovedisplayskip 1.5ex plus 6bp minus 4bp +\belowdisplayskip \abovedisplayskip +\abovedisplayshortskip 0pt plus 6bp +\belowdisplayshortskip 1.5ex plus 6bp minus 4bp +\fi +\fi\fi + + + + +% V1.6 The Computer Modern Fonts will issue a substitution warning for +% 24pt titles (24.88pt is used instead, but the default and correct +% Times font will scale exactly as needed) increase the substitution +% tolerance to turn off this warning. +% +% V1.8a, the compsoc bp font sizes can also cause bogus font substitution +% warnings with footnote or scriptsize math and the $\bullet$ itemized +% list of \IEEEcompsocitemizethanks. So, increase this to 1.5pt or more. +\def\fontsubfuzz{1.7bp} + + +% warn the user in case they forget to use the 9pt option with +% technote +\ifCLASSOPTIONtechnote% + \ifx\CLASSOPTIONpt\@IEEEptsizenine\else% + \typeout{** ATTENTION: Technotes are normally 9pt documents.}% + \fi% +\fi + + +% V1.7 +% Improved \textunderscore to provide a much better fake _ when used with +% OT1 encoding. Under OT1, detect use of pcr or cmtt \ttfamily and use +% available true _ glyph for those two typewriter fonts. +\def\@IEEEstringptm{ptm} % Times Roman family +\def\@IEEEstringppl{ppl} % Palatino Roman family +\def\@IEEEstringphv{phv} % Helvetica Sans Serif family +\def\@IEEEstringpcr{pcr} % Courier typewriter family +\def\@IEEEstringcmtt{cmtt} % Computer Modern typewriter family +\DeclareTextCommandDefault{\textunderscore}{\leavevmode +\ifx\f@family\@IEEEstringpcr\string_\else +\ifx\f@family\@IEEEstringcmtt\string_\else +\ifx\f@family\@IEEEstringptm\kern 0em\vbox{\hrule\@width 0.5em\@height 0.5pt\kern -0.3ex}\else +\ifx\f@family\@IEEEstringppl\kern 0em\vbox{\hrule\@width 0.5em\@height 0.5pt\kern -0.3ex}\else +\ifx\f@family\@IEEEstringphv\kern -0.03em\vbox{\hrule\@width 0.62em\@height 0.52pt\kern -0.33ex}\kern -0.03em\else +\kern 0.09em\vbox{\hrule\@width 0.6em\@height 0.44pt\kern -0.63pt\kern -0.42ex}\kern 0.09em\fi\fi\fi\fi\fi\relax} + + + + +% set the default \baselinestretch +\def\baselinestretch{1} +\ifCLASSOPTIONdraftcls + \def\baselinestretch{1.5}% default baselinestretch for draft modes +\fi + + +% process CLASSINPUT baselinestretch +\ifx\CLASSINPUTbaselinestretch\@IEEEundefined +\else + \edef\baselinestretch{\CLASSINPUTbaselinestretch} % user CLASSINPUT override + \typeout{** ATTENTION: Overriding \string\baselinestretch\space to + \baselinestretch\space via \string\CLASSINPUT.} +\fi + +\small\normalsize % make \baselinestretch take affect + + + + +% store the normalsize baselineskip +\newdimen\CLASSINFOnormalsizebaselineskip +\CLASSINFOnormalsizebaselineskip=\baselineskip\relax +% and the normalsize unity (baselinestretch=1) baselineskip +% we could save a register by giving the user access to +% \@IEEEnormalsizeunitybaselineskip. However, let's protect +% its read only internal status +\newdimen\CLASSINFOnormalsizeunitybaselineskip +\CLASSINFOnormalsizeunitybaselineskip=\@IEEEnormalsizeunitybaselineskip\relax +% store the nominal value of jot +\newdimen\IEEEnormaljot +\IEEEnormaljot=0.25\baselineskip\relax + +% set \jot +\jot=\IEEEnormaljot\relax + + + + +% V1.6, we are now going to fine tune the interword spacing +% The default interword glue for Times under TeX appears to use a +% nominal interword spacing of 25% (relative to the font size, i.e., 1em) +% a maximum of 40% and a minimum of 19%. +% For example, 10pt text uses an interword glue of: +% +% 2.5pt plus 1.49998pt minus 0.59998pt +% +% However, the IEEE allows for a more generous range which reduces the need +% for hyphenation, especially for two column text. Furthermore, the IEEE +% tends to use a little bit more nominal space between the words. +% The IEEE's interword spacing percentages appear to be: +% 35% nominal +% 23% minimum +% 50% maximum +% (They may even be using a tad more for the largest fonts such as 24pt.) +% +% for bold text, the IEEE increases the spacing a little more: +% 37.5% nominal +% 23% minimum +% 55% maximum + +% here are the interword spacing ratios we'll use +% for medium (normal weight) +\def\@IEEEinterspaceratioM{0.35} +\def\@IEEEinterspaceMINratioM{0.23} +\def\@IEEEinterspaceMAXratioM{0.50} + +% for bold +\def\@IEEEinterspaceratioB{0.375} +\def\@IEEEinterspaceMINratioB{0.23} +\def\@IEEEinterspaceMAXratioB{0.55} + + +% compsoc nonconference papers use Palatino, +% tweak settings to better match the proofs +\ifCLASSOPTIONcompsoc +\ifCLASSOPTIONconference\else +% for medium (normal weight) +\def\@IEEEinterspaceratioM{0.28} +\def\@IEEEinterspaceMINratioM{0.21} +\def\@IEEEinterspaceMAXratioM{0.47} +% for bold +\def\@IEEEinterspaceratioB{0.305} +\def\@IEEEinterspaceMINratioB{0.21} +\def\@IEEEinterspaceMAXratioB{0.52} +\fi\fi + + +% command to revise the interword spacing for the current font under TeX: +% \fontdimen2 = nominal interword space +% \fontdimen3 = interword stretch +% \fontdimen4 = interword shrink +% since all changes to the \fontdimen are global, we can enclose these commands +% in braces to confine any font attribute or length changes +\def\@@@IEEEsetfontdimens#1#2#3{{% +\setlength{\@IEEEtrantmpdimenB}{\f@size pt}% grab the font size in pt, could use 1em instead. +\setlength{\@IEEEtrantmpdimenA}{#1\@IEEEtrantmpdimenB}% +\fontdimen2\font=\@IEEEtrantmpdimenA\relax +\addtolength{\@IEEEtrantmpdimenA}{-#2\@IEEEtrantmpdimenB}% +\fontdimen3\font=-\@IEEEtrantmpdimenA\relax +\setlength{\@IEEEtrantmpdimenA}{#1\@IEEEtrantmpdimenB}% +\addtolength{\@IEEEtrantmpdimenA}{-#3\@IEEEtrantmpdimenB}% +\fontdimen4\font=\@IEEEtrantmpdimenA\relax}} + +% revise the interword spacing for each font weight +\def\@@IEEEsetfontdimens{{% +\mdseries +\@@@IEEEsetfontdimens{\@IEEEinterspaceratioM}{\@IEEEinterspaceMAXratioM}{\@IEEEinterspaceMINratioM}% +\bfseries +\@@@IEEEsetfontdimens{\@IEEEinterspaceratioB}{\@IEEEinterspaceMAXratioB}{\@IEEEinterspaceMINratioB}% +}} + +% revise the interword spacing for each font shape +% \slshape is not often used for IEEE work and is not altered here. The \scshape caps are +% already a tad too large in the free LaTeX fonts (as compared to what the IEEE uses) so we +% won't alter these either. +\def\@IEEEsetfontdimens{{% +\normalfont +\@@IEEEsetfontdimens +\normalfont\itshape +\@@IEEEsetfontdimens +}} + +% command to revise the interword spacing for each font size (and shape +% and weight). Only the \rmfamily is done here as \ttfamily uses a +% fixed spacing and \sffamily is not used as the main text of IEEE papers. +\def\@IEEEtunefonts{{\selectfont\rmfamily +\tiny\@IEEEsetfontdimens +\scriptsize\@IEEEsetfontdimens +\footnotesize\@IEEEsetfontdimens +\small\@IEEEsetfontdimens +\normalsize\@IEEEsetfontdimens +\sublargesize\@IEEEsetfontdimens +\large\@IEEEsetfontdimens +\LARGE\@IEEEsetfontdimens +\huge\@IEEEsetfontdimens +\Huge\@IEEEsetfontdimens}} + +% if the nofonttune class option is not given, revise the interword spacing +% now - in case IEEEtran makes any default length measurements, and make +% sure all the default fonts are loaded +\ifCLASSOPTIONnofonttune\else +\@IEEEtunefonts +\fi + +% and again at the start of the document in case the user loaded different fonts +\AtBeginDocument{\ifCLASSOPTIONnofonttune\else\@IEEEtunefonts\fi} + + + + + +% -- V1.8a page setup commands -- + +% The default sample text for calculating margins +% Note that IEEE publications use \scriptsize for headers and footers. +\def\IEEEdefaultsampletext{\normalfont\normalsize gT} +\def\IEEEdefaultheadersampletext{\normalfont\scriptsize T}% IEEE headers default to uppercase +\def\IEEEdefaultfootersampletext{\normalfont\scriptsize gT} + + + +% usage: \IEEEsettextwidth{inner margin}{outer margin} +% Sets \textwidth to allow the specified inner and outer margins +% for the current \paperwidth. +\def\IEEEsettextwidth#1#2{\@IEEEtrantmpdimenA\paperwidth +\@IEEEtrantmpdimenB#1\relax +\advance\@IEEEtrantmpdimenA by -\@IEEEtrantmpdimenB +\@IEEEtrantmpdimenB#2\relax +\advance\@IEEEtrantmpdimenA by -\@IEEEtrantmpdimenB +\textwidth\@IEEEtrantmpdimenA} + + + +% usage: \IEEEsetsidemargin{mode: i, o, c, a}{margin/offset} +% Sets \oddsidemargin and \evensidemargin to yield the specified margin +% of the given mode. +% The available modes are: +% i = inner margin +% o = outer margin +% c = centered, with the given offset +% a = adjust the margins using the given offset +% For the offsets, positive values increase the inner margin. +% \textwidth should be set properly for the given margins before calling this +% function. +\def\IEEEsetsidemargin#1#2{\@IEEEtrantmpdimenA #2\relax +\@IEEEextracttoken{#1}\relax +% check for mode errors +\ifx\@IEEEextractedtokenmacro\@empty + \@IEEEclspkgerror{Empty mode type in \string\IEEEsetsidemargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `i'}{Valid modes for \string\IEEEsetsidemargin\space are: i, o, c and a.}\relax + \let\@IEEEextractedtoken=i\relax + \def\@IEEEextractedtokenmacro{i}\relax +\else + \ifx\@IEEEextractedtokensdiscarded\@empty\else + \typeout{** WARNING: \string\IEEEsetsidemargin\space mode specifiers after the first in `\@IEEEextracttokenarg' ignored (line \the\inputlineno).}\relax + \fi +\fi +% handle each mode +\if\@IEEEextractedtoken a\relax + \advance\oddsidemargin by \@IEEEtrantmpdimenA\relax +\else +\if\@IEEEextractedtoken c\relax + \oddsidemargin\paperwidth + \advance\oddsidemargin by -\textwidth + \divide\oddsidemargin by 2\relax + \advance\oddsidemargin by -1in\relax + \advance\oddsidemargin by \@IEEEtrantmpdimenA\relax +\else +\if\@IEEEextractedtoken o\relax + \oddsidemargin\paperwidth + \advance\oddsidemargin by -\textwidth + \advance\oddsidemargin by -\@IEEEtrantmpdimenA + \advance\oddsidemargin by -1in\relax +\else + \if\@IEEEextractedtoken i\relax + \else + \@IEEEclspkgerror{Unknown mode type `\@IEEEextractedtokenmacro' in \string\IEEEsetsidemargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `i'}% + {Valid modes for \string\IEEEsetsidemargin\space are: i, o, c and a.}% + \fi + \oddsidemargin\@IEEEtrantmpdimenA + \advance\oddsidemargin by -1in\relax +\fi\fi\fi +% odd and even side margins both mean "inner" for single sided pages +\evensidemargin\oddsidemargin +% but are mirrors of each other when twosided is in effect +\if@twoside + \evensidemargin\paperwidth + \advance\evensidemargin by -\textwidth + \advance\evensidemargin by -\oddsidemargin + % have to compensate for both the builtin 1in LaTex offset + % and the fact we already subtracted this offset from \oddsidemargin + \advance\evensidemargin -2in\relax +\fi} + + + +% usage: \IEEEsettextheight[sample text]{top text margin}{bottom text margin} +% Sets \textheight based on the specified top margin and bottom margin. +% Takes into consideration \paperheight, \topskip, and (by default) the +% the actual height and depth of the \IEEEdefaultsampletext text. +\def\IEEEsettextheight{\@ifnextchar [{\@IEEEsettextheight}{\@IEEEsettextheight[\IEEEdefaultsampletext]}} +\def\@IEEEsettextheight[#1]#2#3{\textheight\paperheight\relax + \@IEEEtrantmpdimenA #2\relax + \advance \textheight by -\@IEEEtrantmpdimenA% subtract top margin + \@IEEEtrantmpdimenA #3\relax + \advance \textheight by -\@IEEEtrantmpdimenA% subtract bottom margin + \advance \textheight by \topskip% add \topskip + % subtract off everything above the top, and below the bottom, baselines + \settoheight{\@IEEEtrantmpdimenA}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance \textheight by -\@IEEEtrantmpdimenA + \settodepth{\@IEEEtrantmpdimenA}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance \textheight by -\@IEEEtrantmpdimenA} + + + +\newdimen\IEEEquantizedlength +\IEEEquantizedlength 0sp\relax +\newdimen\IEEEquantizedlengthdiff +\IEEEquantizedlengthdiff 0sp\relax +\def\IEEEquantizedlengthint{0} + +% usage: \IEEEquantizelength{mode: d, c, i}{base unit}{length} +% Sets the length \IEEEquantizedlength to be an integer multiple of the given +% (nonzero) base unit such that \IEEEquantizedlength approximates the given +% length. +% \IEEEquantizedlengthdiff is a length equal to the difference between the +% \IEEEquantizedlength and the given length. +% \IEEEquantizedlengthint is a macro containing the integer number of base units +% in \IEEEquantizedlength. +% i.e., \IEEEquantizedlength = \IEEEquantizedlengthint * base unit +% The mode determines how \IEEEquantizedlength is quantized: +% d = always decrease (always round down \IEEEquantizeint) +% c = use the closest match +% i = always increase (always round up \IEEEquantizeint) +% In anycase, if the given length is already quantized, +% \IEEEquantizedlengthdiff will be set to zero. +\def\IEEEquantizelength#1#2#3{\begingroup +% work in isolation so as not to externally disturb the \@IEEEtrantmp +% variables +% load the argument values indirectly via \IEEEquantizedlengthdiff +% in case the user refers to our \@IEEEtrantmpdimenX, \IEEEquantizedlength, +% etc. in the arguments. we also will work with these as counters, +% i.e., in sp units +% A has the base unit +\IEEEquantizedlengthdiff #2\relax\relax\relax\relax +\@IEEEtrantmpcountA\IEEEquantizedlengthdiff +% B has the input length +\IEEEquantizedlengthdiff #3\relax\relax\relax\relax +\@IEEEtrantmpcountB\IEEEquantizedlengthdiff +\@IEEEtrantmpdimenA\the\@IEEEtrantmpcountA sp\relax +\@IEEEtrantmpdimenB\the\@IEEEtrantmpcountB sp\relax +% \@IEEEtrantmpcountC will have the quantized int +% \IEEEquantizedlength will have the quantized length +% \@IEEEtrantmpdimenC will have the quantized diff +% initialize them to zero as this is what will be +% exported if an error occurs +\@IEEEtrantmpcountC 0\relax +\IEEEquantizedlength 0sp\relax +\@IEEEtrantmpdimenC 0sp\relax +% extract mode +\@IEEEextracttoken{#1}\relax +% check for mode errors +\ifx\@IEEEextractedtokenmacro\@empty + \@IEEEclspkgerror{Empty mode type in \string\IEEEquantizelength\space (line \the\inputlineno).\MessageBreak + Defaulting to `d'}{Valid modes for \string\IEEEquantizelength\space are: d, c and i.}\relax + \let\@IEEEextractedtoken=d\relax + \def\@IEEEextractedtokenmacro{d}\relax +\else + \ifx\@IEEEextractedtokensdiscarded\@empty\else + \typeout{** WARNING: \string\IEEEquantizelength\space mode specifiers after the first in `\@IEEEextracttokenarg' ignored (line \the\inputlineno).}\relax + \fi +\fi +% check for base unit is zero error +\ifnum\@IEEEtrantmpcountA=0\relax +\@IEEEclspkgerror{Base unit is zero in \string\IEEEquantizelength\space (line \the\inputlineno).\MessageBreak + \string\IEEEquantizedlength\space and \string\IEEEquantizedlengthdiff\space are set to zero}{Division by zero is not allowed.}\relax +\else% base unit is nonzero + % \@IEEEtrantmpcountC carries the number of integer units + % in the quantized length (integer length \ base) + \@IEEEtrantmpcountC\@IEEEtrantmpcountB\relax + \divide\@IEEEtrantmpcountC by \@IEEEtrantmpcountA\relax + % \IEEEquantizedlength has the (rounded down) quantized length + % = base * int + \IEEEquantizedlength\@IEEEtrantmpdimenA\relax + \multiply\IEEEquantizedlength by \@IEEEtrantmpcountC\relax + % \@IEEEtrantmpdimenC has the difference + % = quantized length - length + \@IEEEtrantmpdimenC\IEEEquantizedlength\relax + \advance\@IEEEtrantmpdimenC by -\@IEEEtrantmpdimenB\relax + % trap special case of length being already quantized + % to avoid a roundup under i option + \ifdim\@IEEEtrantmpdimenC=0sp\relax + \else % length not is already quantized + % set dimenA to carry the upper quantized (absolute value) difference: + % quantizedlength + base - length + \advance\@IEEEtrantmpdimenA by \IEEEquantizedlength\relax + \advance\@IEEEtrantmpdimenA by -\@IEEEtrantmpdimenB\relax + % set dimenB to carry the lower quantized (absolute value) difference: + % length - quantizedlength + \advance\@IEEEtrantmpdimenB by -\IEEEquantizedlength\relax + % handle each mode + \if\@IEEEextractedtoken c\relax + % compare upper and lower amounts, select upper if lower > upper + \ifdim\@IEEEtrantmpdimenB>\@IEEEtrantmpdimenA\relax + % use upper + \advance\IEEEquantizedlength by \the\@IEEEtrantmpcountA sp\relax + \advance\@IEEEtrantmpcountC by 1\relax + \@IEEEtrantmpdimenC\@IEEEtrantmpdimenA + \else% <=. uselower + % no need to do anything for lower, use output values already setup + \fi + \else% not mode c + \if\@IEEEextractedtoken i\relax + % always round up under i mode + \advance\IEEEquantizedlength by \the\@IEEEtrantmpcountA sp\relax + \advance\@IEEEtrantmpcountC by 1\relax + \@IEEEtrantmpdimenC\@IEEEtrantmpdimenA + \else + \if\@IEEEextractedtoken d\relax + \else + \@IEEEclspkgerror{Unknown mode type `\@IEEEextractedtokenmacro' in \string\IEEEquantizelength\space (line \the\inputlineno).\MessageBreak + Defaulting to `d'}% + {Valid modes for \string\IEEEquantizelength\space are: d, c, and i.}\relax + \fi % if d + % no need to do anything for d, use output values already setup + \fi\fi % if i, c + \fi % if length is already quantized +\fi% if base unit is zero +% globally assign the results to macros we use here to escape the enclosing +% group without needing to call \global on any of the \@IEEEtrantmp variables. +% \@IEEEtrantmpcountC has the quantized int +% \IEEEquantizedlength has the quantized length +% \@IEEEtrantmpdimenC has the quantized diff +\xdef\@IEEEquantizedlengthintmacro{\the\@IEEEtrantmpcountC}\relax +\@IEEEtrantmpcountC\IEEEquantizedlength\relax +\xdef\@IEEEquantizedlengthmacro{\the\@IEEEtrantmpcountC}\relax +\@IEEEtrantmpcountC\@IEEEtrantmpdimenC\relax +\xdef\@IEEEquantizedlengthdiffmacro{\the\@IEEEtrantmpcountC}\relax +\endgroup +% locally assign the outputs here from the macros +\expandafter\IEEEquantizedlength\@IEEEquantizedlengthmacro sp\relax +\expandafter\IEEEquantizedlengthdiff\@IEEEquantizedlengthdiffmacro sp\relax +\edef\IEEEquantizedlengthint{\@IEEEquantizedlengthintmacro}\relax} + + + +\newdimen\IEEEquantizedtextheightdiff +\IEEEquantizedtextheightdiff 0sp\relax + +% usage: \IEEEquantizetextheight[base unit]{mode: d, c, i} +% Sets \textheight to be an integer multiple of the current \baselineskip +% (or the optionally specified base unit) plus the first (\topskip) line. +% \IEEEquantizedtextheightdiff is a length equal to the difference between +% the new quantized and original \textheight. +% \IEEEquantizedtextheightlpc is a macro containing the integer number of +% lines per column under the quantized \textheight. i.e., +% \textheight = \IEEEquantizedtextheightlpc * \baselineskip + \topskip +% The mode determines how \textheight is quantized: +% d = always decrease (always round down the number of lines per column) +% c = use the closest match +% i = always increase (always round up the number of lines per column) +% In anycase, if \textheight is already quantized, it will remain unchanged, +% and \IEEEquantizedtextheightdiff will be set to zero. +% Depends on: \IEEEquantizelength +\def\IEEEquantizetextheight{\@ifnextchar [{\@IEEEquantizetextheight}{\@IEEEquantizetextheight[\baselineskip]}} +\def\@IEEEquantizetextheight[#1]#2{\begingroup +% use our \IEEEquantizedtextheightdiff as a scratch pad +% we need to subtract off \topskip before quantization +\IEEEquantizedtextheightdiff\textheight +\advance\IEEEquantizedtextheightdiff by -\topskip\relax +\IEEEquantizelength{#2}{#1}{\IEEEquantizedtextheightdiff} +% add back \topskip line +\advance\IEEEquantizedlength by \topskip +\@IEEEtrantmpcountC\IEEEquantizedlengthint\relax +\advance\@IEEEtrantmpcountC by 1\relax +% globally assign the results to macros we use here to escape the enclosing +% group without needing to call \global on any of the \@IEEEtrantmp variables. +\xdef\@IEEEquantizedtextheightlpcmacro{\the\@IEEEtrantmpcountC}\relax +\@IEEEtrantmpcountC\IEEEquantizedlength\relax +\xdef\@IEEEquantizedtextheightmacro{\the\@IEEEtrantmpcountC}\relax +\@IEEEtrantmpcountC\IEEEquantizedlengthdiff\relax +\xdef\@IEEEquantizedtextheightdiffmacro{\the\@IEEEtrantmpcountC}\relax +\endgroup +% locally assign the outputs here from the macros +\textheight\@IEEEquantizedtextheightmacro sp\relax +\IEEEquantizedtextheightdiff\@IEEEquantizedtextheightdiffmacro sp\relax +\edef\IEEEquantizedtextheightlpc{\@IEEEquantizedtextheightlpcmacro}} + + + +% usage: \IEEEsettopmargin[sample text]{mode: t, b, c, a, q}{margin/offset} +% Sets \topmargin based on the specified vertical margin. +% Takes into consideration the base 1in offset, \headheight, \headsep, +% \topskip, and (by default) the the actual height (or, for the bottom, depth) +% of the \IEEEdefaultsampletext text. +% The available modes are: +% t = top margin +% b = bottom margin +% c = vertically centered, with the given offset +% a = adjust the vertical margins using the given offset +% q = adjust the margins using \IEEEquantizedtextheightdiff and the given offset +% For the offsets, positive values increase the top margin. +% \headheight, \headsep, \topskip and \textheight should be set properly for the +% given margins before calling this function. +\def\IEEEsettopmargin{\@ifnextchar [{\@IEEEsettopmargin}{\@IEEEsettopmargin[\IEEEdefaultsampletext]}} +\def\@IEEEsettopmargin[#1]#2#3{\@IEEEtrantmpdimenA #3\relax +\@IEEEextracttoken{#2}\relax +% check for mode errors +\ifx\@IEEEextractedtokenmacro\@empty + \@IEEEclspkgerror{Empty mode type in \string\IEEEsettopmargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `t'}{Valid modes for \string\IEEEsettopmargin\space are: t, b, c, a and q.}\relax + \let\@IEEEextractedtoken=t\relax + \def\@IEEEextractedtokenmacro{t}\relax +\else + \ifx\@IEEEextractedtokensdiscarded\@empty\else + \typeout{** WARNING: \string\IEEEsettopmargin\space mode specifiers after the first in `\@IEEEextracttokenarg' ignored (line \the\inputlineno).}\relax + \fi +\fi +% handle each mode +\if\@IEEEextractedtoken a\relax + \advance\topmargin by \@IEEEtrantmpdimenA\relax +\else +\if\@IEEEextractedtoken q\relax + % we need to adjust by half the \IEEEquantizedtextheightdiff value + \@IEEEtrantmpdimenB\IEEEquantizedtextheightdiff\relax + \divide\@IEEEtrantmpdimenB by 2\relax + % a positive \IEEEquantizedtextheightdiff means we need to reduce \topmargin + % because \textheight has been lenghtened + \advance\topmargin by -\@IEEEtrantmpdimenB\relax + \advance\topmargin by \@IEEEtrantmpdimenA\relax +\else +\if\@IEEEextractedtoken c\relax + \topmargin\paperheight + \advance\topmargin by -\textheight + % \textheight includes \topskip, but we should not count topskip whitespace here, backout + \advance \topmargin by \topskip + \settoheight{\@IEEEtrantmpdimenB}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\topmargin by -\@IEEEtrantmpdimenB\relax + \settodepth{\@IEEEtrantmpdimenB}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\topmargin by -\@IEEEtrantmpdimenB\relax + \divide\topmargin by 2\relax + \advance\topmargin by \@IEEEtrantmpdimenA\relax +\else +\if\@IEEEextractedtoken b\relax + \topmargin\paperheight + \advance\topmargin by -\textheight + % \textheight includes \topskip, but we should not count topskip whitespace here, backout + \advance \topmargin by \topskip + \settodepth{\@IEEEtrantmpdimenB}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\topmargin by -\@IEEEtrantmpdimenB\relax + \advance\topmargin by -\@IEEEtrantmpdimenA\relax +\else + \if\@IEEEextractedtoken t\relax + \else + \@IEEEclspkgerror{Unknown mode type `\@IEEEextractedtokenmacro' in \string\IEEEsettopmargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `t'}% + {Valid modes for \string\IEEEsettopmargin\space are: t, b, c, a and q.}\relax + \fi + \topmargin\@IEEEtrantmpdimenA\relax + \settoheight{\@IEEEtrantmpdimenB}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\topmargin by \@IEEEtrantmpdimenB\relax +\fi\fi % if t, b, c +% convert desired top margin into actual \topmargin +% this is not done for the q or a modes because they are only adjustments +\advance \topmargin by -\topskip +\advance \topmargin by -1in +\advance \topmargin by -\headheight +\advance \topmargin by -\headsep +\fi\fi % if q, a +} + + + +% usage: \IEEEsetheadermargin[header sample][text sample]{mode: t, b, c, a}{margin/offset} +% Differentially adjusts \topmargin and \headsep (such that their sum is unchanged) +% based on the specified header margin. +% Takes into consideration the base 1in offset, \headheight, \topskip, and (by default) +% the actual height (or depth) of the \IEEEdefaultheadersampletext and +% \IEEEdefaultsampletext text. +% The available modes are: +% t = top margin (top of the header text to the top of the page) +% b = bottom margin (bottom of the header text to the top of the main text) +% c = vertically centered between the main text and the top of the page, +% with the given offset +% a = adjust the vertical position using the given offset +% For the offsets, positive values move the header downward. +% \headheight, \headsep, \topskip and \topmargin should be set properly before +% calling this function. +\def\IEEEsetheadermargin{\@ifnextchar [{\@IEEEsetheadermargin}{\@IEEEsetheadermargin[\IEEEdefaultheadersampletext]}} +\def\@IEEEsetheadermargin[#1]{\@ifnextchar [{\@@IEEEsetheadermargin[#1]}{\@@IEEEsetheadermargin[#1][\IEEEdefaultsampletext]}} +\def\@@IEEEsetheadermargin[#1][#2]#3#4{\@IEEEtrantmpdimenA #4\relax +\@IEEEextracttoken{#3}\relax +% check for mode errors +\ifx\@IEEEextractedtokenmacro\@empty + \@IEEEclspkgerror{Empty mode type in \string\IEEEsetheadermargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `t'}{Valid modes for \string\IEEEsetheadermargin\space are: t, b, c, and a.}\relax + \let\@IEEEextractedtoken=t\relax + \def\@IEEEextractedtokenmacro{t}\relax +\else + \ifx\@IEEEextractedtokensdiscarded\@empty\else + \typeout{** WARNING: \string\IEEEsetheadermargin\space mode specifiers after the first in `\@IEEEextracttokenarg' ignored (line \the\inputlineno).}\relax + \fi +\fi +% handle each mode +\if\@IEEEextractedtoken a\relax + % No need to do anything here and can pass through the adjustment + % value as is. The end adjustment of \topmargin and \headsep will + % do all that is needed +\else +\if\@IEEEextractedtoken c\relax + % get the bottom margin + \@IEEEtrantmpdimenB\headsep\relax + \settodepth{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + \advance\@IEEEtrantmpdimenB by \topskip + \settoheight{\@IEEEtrantmpdimenC}{\begingroup #2\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the actual header bottom margin + % subtract from it the top header margin + \advance\@IEEEtrantmpdimenB -1in\relax % take into consideration the system 1in offset of the top margin + \advance\@IEEEtrantmpdimenB by -\topmargin + \advance\@IEEEtrantmpdimenB by -\headheight + \settoheight{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by \@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the difference between the bottom and top margins + % we need to adjust by half this amount to center the header + \divide\@IEEEtrantmpdimenB by 2\relax + % and add to offset + \advance\@IEEEtrantmpdimenA by \@IEEEtrantmpdimenB +\else +\if\@IEEEextractedtoken b\relax + \@IEEEtrantmpdimenB\headsep\relax + \settodepth{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + \advance\@IEEEtrantmpdimenB by \topskip + \settoheight{\@IEEEtrantmpdimenC}{\begingroup #2\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the actual header bottom margin + % get the difference between the actual and the desired + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenA + \@IEEEtrantmpdimenA\@IEEEtrantmpdimenB +\else + \if\@IEEEextractedtoken t\relax + \else + \@IEEEclspkgerror{Unknown mode type `\@IEEEextractedtokenmacro' in \string\IEEEsetheadermargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `t'}% + {Valid modes for \string\IEEEsetheadermargin\space are: t, b, c and a.}\relax + \fi + \@IEEEtrantmpdimenB 1in\relax % take into consideration the system 1in offset of the top margin + \advance\@IEEEtrantmpdimenB by \topmargin + \advance\@IEEEtrantmpdimenB by \headheight + \settoheight{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the actual header top margin + % get the difference between the desired and the actual + \advance\@IEEEtrantmpdimenA by -\@IEEEtrantmpdimenB +\fi\fi % if t, b, c +\fi % if a +% advance \topmargin by the needed amount and reduce \headsep by the same +% so as not to disturb the location of the main text +\advance\topmargin by \@IEEEtrantmpdimenA\relax +\advance\headsep by -\@IEEEtrantmpdimenA\relax +} + + + +% usage: \IEEEsetfootermargin[footer sample][text sample]{mode: t, b, c, a}{margin/offset} +% Adjusts \footskip based on the specified footer margin. +% Takes into consideration the base 1in offset, \paperheight, \headheight, +% \headsep, \textheight and (by default) the actual height (or depth) of the +% \IEEEdefaultfootersampletext and \IEEEdefaultsampletext text. +% The available modes are: +% t = top margin (top of the footer text to the bottom of the main text) +% b = bottom margin (bottom of the footer text to the bottom of page) +% c = vertically centered between the main text and the bottom of the page, +% with the given offset +% a = adjust the vertical position using the given offset +% For the offsets, positive values move the footer downward. +% \headheight, \headsep, \topskip, \topmargin, and \textheight should be set +% properly before calling this function. +\def\IEEEsetfootermargin{\@ifnextchar [{\@IEEEsetfootermargin}{\@IEEEsetfootermargin[\IEEEdefaultfootersampletext]}} +\def\@IEEEsetfootermargin[#1]{\@ifnextchar [{\@@IEEEsetfootermargin[#1]}{\@@IEEEsetfootermargin[#1][\IEEEdefaultsampletext]}} +\def\@@IEEEsetfootermargin[#1][#2]#3#4{\@IEEEtrantmpdimenA #4\relax +\@IEEEextracttoken{#3}\relax +% check for mode errors +\ifx\@IEEEextractedtokenmacro\@empty + \@IEEEclspkgerror{Empty mode type in \string\IEEEsetfootermargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `t'}{Valid modes for \string\IEEEsetfootermargin\space are: t, b, c, and a.}\relax + \let\@IEEEextractedtoken=t\relax + \def\@IEEEextractedtokenmacro{t}\relax +\else + \ifx\@IEEEextractedtokensdiscarded\@empty\else + \typeout{** WARNING: \string\IEEEsetfootermargin\space mode specifiers after the first in `\@IEEEextracttokenarg' ignored (line \the\inputlineno).}\relax + \fi +\fi +% handle each mode +\if\@IEEEextractedtoken a\relax + % No need to do anything here and can pass through the adjustment + % value as is. The end adjustment of \footskip will do all that + % is needed +\else +\if\@IEEEextractedtoken c\relax + % calculate the bottom margin + \@IEEEtrantmpdimenB 1in\relax % system 1in offset + \advance\@IEEEtrantmpdimenB\topmargin\relax + \advance\@IEEEtrantmpdimenB\headheight\relax + \advance\@IEEEtrantmpdimenB\headsep\relax + \advance\@IEEEtrantmpdimenB\textheight\relax + \advance\@IEEEtrantmpdimenB\footskip\relax + \settodepth{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenC by \@IEEEtrantmpdimenB + \@IEEEtrantmpdimenB\paperheight + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the actual footer bottom margin + % now subtract off the footer top margin + \advance\@IEEEtrantmpdimenB -\footskip\relax + \settodepth{\@IEEEtrantmpdimenC}{\begingroup #2\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by \@IEEEtrantmpdimenC + \settoheight{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by \@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the difference between the bottom + % and top footer margins + % our adjustment must be half this value to center the footer + \divide\@IEEEtrantmpdimenB by 2\relax + % add to the offset + \advance\@IEEEtrantmpdimenA by \@IEEEtrantmpdimenB +\else +\if\@IEEEextractedtoken b\relax + % calculate the bottom margin + \@IEEEtrantmpdimenB 1in\relax % system 1in offset + \advance\@IEEEtrantmpdimenB\topmargin\relax + \advance\@IEEEtrantmpdimenB\headheight\relax + \advance\@IEEEtrantmpdimenB\headsep\relax + \advance\@IEEEtrantmpdimenB\textheight\relax + \advance\@IEEEtrantmpdimenB\footskip\relax + \settodepth{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenC by \@IEEEtrantmpdimenB + \@IEEEtrantmpdimenB\paperheight + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the actual footer bottom margin + % get the difference between the actual and the desired + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenA + \@IEEEtrantmpdimenA\@IEEEtrantmpdimenB +\else + \if\@IEEEextractedtoken t\relax + \else + \@IEEEclspkgerror{Unknown mode type `\@IEEEextractedtokenmacro' in \string\IEEEsetfootermargin\space (line \the\inputlineno).\MessageBreak + Defaulting to `t'}% + {Valid modes for \string\IEEEsetfootermargin\space are: t, b, c and a.}\relax + \fi + \@IEEEtrantmpdimenB\footskip\relax + \settodepth{\@IEEEtrantmpdimenC}{\begingroup #2\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + \settoheight{\@IEEEtrantmpdimenC}{\begingroup #1\relax\relax\relax\endgroup}\relax + \advance\@IEEEtrantmpdimenB by -\@IEEEtrantmpdimenC + % at this point \@IEEEtrantmpdimenB has the actual footer top margin + % get the difference between the desired and the actual + \advance\@IEEEtrantmpdimenA by -\@IEEEtrantmpdimenB +\fi\fi % if t, b, c +\fi % if a +% advance \footskip by the needed amount +\advance\footskip by \@IEEEtrantmpdimenA\relax +} + +% -- End V1.8a page setup commands -- + + + + + +% V1.6 +% LaTeX is a little to quick to use hyphenations +% So, we increase the penalty for their use and raise +% the badness level that triggers an underfull hbox +% warning. The author may still have to tweak things, +% but the appearance will be much better "right out +% of the box" than that under V1.5 and prior. +% TeX default is 50 +\hyphenpenalty=750 +\ifCLASSOPTIONcompsoc +\hyphenpenalty 500 +\fi +% If we didn't adjust the interword spacing, 2200 might be better. +% The TeX default is 1000 +\hbadness=1350 +% The IEEE does not use extra spacing after punctuation +\frenchspacing + +% V1.7 increase this a tad to discourage equation breaks +\binoppenalty=1000 % default 700 +\relpenalty=800 % default 500 + +% v1.8a increase these to discourage widows and orphans +\clubpenalty=1000 % default 150 +\widowpenalty=1000 % default 150 +\displaywidowpenalty=1000 % default 50 + + +% margin note stuff +\marginparsep 10pt +\marginparwidth 20pt +\marginparpush 25pt + + +% if things get too close, go ahead and let them touch +\lineskip 0pt +\normallineskip 0pt +\lineskiplimit 0pt +\normallineskiplimit 0pt + +% The distance from the lower edge of the text body to the +% footline +\footskip 0.4in + +% normally zero, should be relative to font height. +% put in a little rubber to help stop some bad breaks (underfull vboxes) +\parskip 0ex plus 0.2ex minus 0.1ex + +\parindent 1.0em +\ifCLASSOPTIONcompsoc + \parindent 1.5em +\fi + +\headheight 12pt +\headsep 18pt +% use the normal font baselineskip +% so that \topskip is unaffected by changes in \baselinestretch +\topskip=\@IEEEnormalsizeunitybaselineskip + + +% V1.8 \maxdepth defaults to 4pt, but should be font size dependent +\maxdepth=0.5\@IEEEnormalsizeunitybaselineskip +\textheight 58pc % 9.63in, 696pt + +% set the default top margin to 58pt +% which results in a \topmargin of -49.59pt for 10pt documents +\IEEEsettopmargin{t}{58pt} +% tweak textheight to a perfect integer number of lines/column. +% standard is: 9pt/63 lpc; 10pt/58 lpc; 11pt/52 lpc; 12pt/50 lpc +\IEEEquantizetextheight{c} +% tweak top margin so that the error is shared equally at the top and bottom +\IEEEsettopmargin{q}{0sp} + + +\columnsep 1pc +\textwidth 43pc % 2 x 21pc + 1pc = 43pc + +% set the default side margins to center the text +\IEEEsetsidemargin{c}{0pt} + + +% adjust margins for default conference mode +\ifCLASSOPTIONconference + \textheight 9.25in % The standard for conferences (668.4975pt) + \IEEEsettopmargin{t}{0.75in} + % tweak textheight to a perfect integer number of lines/page. + % standard is: 9pt/61 lpc; 10pt/56 lpc; 11pt/50 lpc; 12pt/48 lpc + \IEEEquantizetextheight{c} + % tweak top margin so that the error is shared equally at the top and bottom + \IEEEsettopmargin{q}{0sp} +\fi + + +% compsoc text sizes, margins and spacings +\ifCLASSOPTIONcompsoc + \columnsep 12bp + % CS specs for \textwdith are 6.875in + % \textwidth 6.875in + % however, measurements from proofs show they are using 3.5in columns + \textwidth 7in + \advance\textwidth by \columnsep + % set the side margins to center the text + \IEEEsetsidemargin{c}{0pt} + % top/bottom margins to center + % could just set \textheight to 9.75in for all the different paper sizes + % and then quantize, but we'll do it the long way here to allow for easy + % future per-paper size adjustments + \IEEEsettextheight{0.625in}{0.625in}% 11in - 2 * 0.625in = 9.75in is the standard text height for compsoc journals + \IEEEsettopmargin{t}{0.625in} + \if@IEEEusingcspaper + \IEEEsettextheight{0.5in}{0.5in}% 10.75in - 2 * 0.5in = 9.75in + \IEEEsettopmargin{t}{0.5in} + \fi + \if@IEEEusingAfourpaper + \IEEEsettextheight{24.675mm}{24.675mm}% 297mm - 2 * 24.675mm = 247.650mm (9.75in) + \IEEEsettopmargin{t}{24.675mm} + \fi + % tweak textheight to a perfect integer number of lines/page. + % standard is: 9pt/65 lpc; 10pt/61 lpc; 11pt/53 lpc; 12pt/49 lpc + \IEEEquantizetextheight{c} + % tweak top margin so that the error is shared equally at the top and bottom + \IEEEsettopmargin{q}{0sp} + +% compsoc conference + \ifCLASSOPTIONconference + % compsoc conference use a larger value for columnsep + \columnsep 0.25in + \IEEEsettextwidth{0.75in}{0.75in} + % set the side margins to center the text (0.75in for letterpaper) + \IEEEsetsidemargin{c}{0pt} + % compsoc conferences want 1in top and bottom margin + \IEEEsettextheight{1in}{1in} + \IEEEsettopmargin{t}{1in} + % tweak textheight to a perfect integer number of lines/page. + % standard is: 9pt/58 lpc; 10pt/53 lpc; 11pt/48 lpc; 12pt/46 lpc + \IEEEquantizetextheight{c} + % tweak top margin so that the error is shared equally at the top and bottom + \IEEEsettopmargin{q}{0sp} + \fi +\fi + + + +% draft mode settings override that of all other modes +% provides a nice 1in margin all around the paper and extra +% space between the lines for editor's comments +\ifCLASSOPTIONdraftcls + % we want 1in side margins regardless of paper type + \IEEEsettextwidth{1in}{1in} + \IEEEsetsidemargin{c}{0pt} + % want 1in top and bottom margins + \IEEEsettextheight{1in}{1in} + \IEEEsettopmargin{t}{1in} + % digitize textheight to be an integer number of lines. + % this may cause the top and bottom margins to be off a tad + \IEEEquantizetextheight{c} + % tweak top margin so that the error is shared equally at the top and bottom + \IEEEsettopmargin{q}{0sp} +\fi + + + +% process CLASSINPUT inner/outer margin +% if inner margin defined, but outer margin not, set outer to inner. +\ifx\CLASSINPUTinnersidemargin\@IEEEundefined +\else + \ifx\CLASSINPUToutersidemargin\@IEEEundefined + \edef\CLASSINPUToutersidemargin{\CLASSINPUTinnersidemargin} + \fi +\fi + +\ifx\CLASSINPUToutersidemargin\@IEEEundefined +\else + % if outer margin defined, but inner margin not, set inner to outer. + \ifx\CLASSINPUTinnersidemargin\@IEEEundefined + \edef\CLASSINPUTinnersidemargin{\CLASSINPUToutersidemargin} + \fi + \IEEEsettextwidth{\CLASSINPUTinnersidemargin}{\CLASSINPUToutersidemargin} + \IEEEsetsidemargin{i}{\CLASSINPUTinnersidemargin} + \typeout{** ATTENTION: Overriding inner side margin to \CLASSINPUTinnersidemargin\space and + outer side margin to \CLASSINPUToutersidemargin\space via \string\CLASSINPUT.} +\fi + + + +% process CLASSINPUT top/bottom text margin +% if toptext margin defined, but bottomtext margin not, set bottomtext to toptext margin +\ifx\CLASSINPUTtoptextmargin\@IEEEundefined +\else + \ifx\CLASSINPUTbottomtextmargin\@IEEEundefined + \edef\CLASSINPUTbottomtextmargin{\CLASSINPUTtoptextmargin} + \fi +\fi + +\ifx\CLASSINPUTbottomtextmargin\@IEEEundefined +\else + % if bottomtext margin defined, but toptext margin not, set toptext to bottomtext margin + \ifx\CLASSINPUTtoptextmargin\@IEEEundefined + \edef\CLASSINPUTtoptextmargin{\CLASSINPUTbottomtextmargin} + \fi + \IEEEsettextheight{\CLASSINPUTtoptextmargin}{\CLASSINPUTbottomtextmargin} + \IEEEsettopmargin{t}{\CLASSINPUTtoptextmargin} + \typeout{** ATTENTION: Overriding top text margin to \CLASSINPUTtoptextmargin\space and + bottom text margin to \CLASSINPUTbottomtextmargin\space via \string\CLASSINPUT.} +\fi + + + +% default to center header and footer text in the margins +\IEEEsetheadermargin{c}{0pt} +\IEEEsetfootermargin{c}{0pt} + +% adjust header and footer positions for compsoc journals +\ifCLASSOPTIONcompsoc + \ifCLASSOPTIONjournal + \IEEEsetheadermargin{b}{\@IEEEnormalsizeunitybaselineskip} + \IEEEsetfootermargin{t}{\@IEEEnormalsizeunitybaselineskip} + \fi +\fi + + +% V1.8a display lines per column info message on user's console +\def\IEEEdisplayinfolinespercolumn{\@IEEEtrantmpdimenA=\textheight +% topskip represents only one line even if > baselineskip +\advance\@IEEEtrantmpdimenA by -1\topskip +\@IEEEtrantmpcountA=\@IEEEtrantmpdimenA +\@IEEEtrantmpcountB=\@IEEEtrantmpdimenA +\divide\@IEEEtrantmpcountB by \baselineskip +% need to add one line to include topskip (first) line +\advance\@IEEEtrantmpcountB by 1 +% save lines per column value as text +\edef\@IEEEnumlinespercolumninfotxt{\the\@IEEEtrantmpcountB} +% backout topskip advance to allow direct \@IEEEtrantmpcountA comparison +\advance\@IEEEtrantmpcountB by -1 +% restore value as text height (without topskip) rather than just as number of lines +\multiply\@IEEEtrantmpcountB by \baselineskip +% is the column height an integer number of lines per column? +\ifnum\@IEEEtrantmpcountA=\@IEEEtrantmpcountB +\edef\@IEEEnumlinespercolumnexactinfotxt{exact} +\else +\@IEEEtrantmpdimenA\@IEEEtrantmpcountA sp\relax +\advance\@IEEEtrantmpdimenA by -\@IEEEtrantmpcountB sp\relax +\edef\@IEEEnumlinespercolumnexactinfotxt{approximate, difference = \the\@IEEEtrantmpdimenA} +\fi +\typeout{-- Lines per column: \@IEEEnumlinespercolumninfotxt\space (\@IEEEnumlinespercolumnexactinfotxt).}} +% delay execution till start of document to allow for user changes +\AtBeginDocument{\IEEEdisplayinfolinespercolumn} + + + +% LIST SPACING CONTROLS + +% Controls the amount of EXTRA spacing +% above and below \trivlist +% Both \list and IED lists override this. +% However, \trivlist will use this as will most +% things built from \trivlist like the \center +% environment. +\topsep 0.5\baselineskip + +% Controls the additional spacing around lists preceded +% or followed by blank lines. the IEEE does not increase +% spacing before or after paragraphs so it is set to zero. +% \z@ is the same as zero, but faster. +\partopsep \z@ + +% Controls the spacing between paragraphs in lists. +% The IEEE does not increase spacing before or after paragraphs +% so this is also zero. +% With IEEEtran.cls, global changes to +% this value DO affect lists (but not IED lists). +\parsep \z@ + +% Controls the extra spacing between list items. +% The IEEE does not put extra spacing between items. +% With IEEEtran.cls, global changes to this value DO affect +% lists (but not IED lists). +\itemsep \z@ + +% \itemindent is the amount to indent the FIRST line of a list +% item. It is auto set to zero within the \list environment. To alter +% it, you have to do so when you call the \list. +% However, the IEEE uses this for the theorem environment +% There is an alternative value for this near \leftmargini below +\itemindent -1em + +% \leftmargin, the spacing from the left margin of the main text to +% the left of the main body of a list item is set by \list. +% Hence this statement does nothing for lists. +% But, quote and verse do use it for indention. +\leftmargin 2em + +% we retain this stuff from the older IEEEtran.cls so that \list +% will work the same way as before. However, itemize, enumerate and +% description (IED) could care less about what these are as they +% all are overridden. +\leftmargini 2em +%\itemindent 2em % Alternative values: sometimes used. +%\leftmargini 0em +\leftmarginii 1em +\leftmarginiii 1.5em +\leftmarginiv 1.5em +\leftmarginv 1.0em +\leftmarginvi 1.0em +\labelsep 0.5em +\labelwidth \z@ + + +% The old IEEEtran.cls behavior of \list is retained. +% However, the new V1.3 IED list environments override all the +% @list stuff (\@listX is called within \list for the +% appropriate level just before the user's list_decl is called). +% \topsep is now 2pt as the IEEE puts a little extra space around +% lists - used by those non-IED macros that depend on \list. +% Note that \parsep and \itemsep are not redefined as in +% the sizexx.clo \@listX (which article.cls uses) so global changes +% of these values DO affect \list +% +\def\@listi{\leftmargin\leftmargini \topsep 2pt plus 1pt minus 1pt} +\let\@listI\@listi +\def\@listii{\leftmargin\leftmarginii\labelwidth\leftmarginii% + \advance\labelwidth-\labelsep \topsep 2pt} +\def\@listiii{\leftmargin\leftmarginiii\labelwidth\leftmarginiii% + \advance\labelwidth-\labelsep \topsep 2pt} +\def\@listiv{\leftmargin\leftmarginiv\labelwidth\leftmarginiv% + \advance\labelwidth-\labelsep \topsep 2pt} +\def\@listv{\leftmargin\leftmarginv\labelwidth\leftmarginv% + \advance\labelwidth-\labelsep \topsep 2pt} +\def\@listvi{\leftmargin\leftmarginvi\labelwidth\leftmarginvi% + \advance\labelwidth-\labelsep \topsep 2pt} + + +% The IEEE uses 5) not 5. +\def\labelenumi{\theenumi)} \def\theenumi{\arabic{enumi}} + +% The IEEE uses a) not (a) +\def\labelenumii{\theenumii)} \def\theenumii{\alph{enumii}} + +% The IEEE uses iii) not iii. +\def\labelenumiii{\theenumiii)} \def\theenumiii{\roman{enumiii}} + +% The IEEE uses A) not A. +\def\labelenumiv{\theenumiv)} \def\theenumiv{\Alph{enumiv}} + +% exactly the same as in article.cls +\def\p@enumii{\theenumi} +\def\p@enumiii{\theenumi(\theenumii)} +\def\p@enumiv{\p@enumiii\theenumiii} + +% itemized list label styles +\def\labelitemi{$\scriptstyle\bullet$} +\def\labelitemii{\textbf{--}} +\def\labelitemiii{$\ast$} +\def\labelitemiv{$\cdot$} + + + +% **** V1.3 ENHANCEMENTS **** +% Itemize, Enumerate and Description (IED) List Controls +% *************************** +% +% +% The IEEE seems to use at least two different values by +% which ITEMIZED list labels are indented to the right +% For The Journal of Lightwave Technology (JLT) and The Journal +% on Selected Areas in Communications (JSAC), they tend to use +% an indention equal to \parindent. For Transactions on Communications +% they tend to indent ITEMIZED lists a little more--- 1.3\parindent. +% We'll provide both values here for you so that you can choose +% which one you like in your document using a command such as: +% setlength{\IEEEilabelindent}{\IEEEilabelindentB} +\newdimen\IEEEilabelindentA +\IEEEilabelindentA \parindent + +\newdimen\IEEEilabelindentB +\IEEEilabelindentB 1.3\parindent +% However, we'll default to using \parindent +% which makes more sense to me +\newdimen\IEEEilabelindent +\IEEEilabelindent \IEEEilabelindentA + + +% This controls the default amount the enumerated list labels +% are indented to the right. +% Normally, this is the same as the paragraph indention +\newdimen\IEEEelabelindent +\IEEEelabelindent \parindent + +% This controls the default amount the description list labels +% are indented to the right. +% Normally, this is the same as the paragraph indention +\newdimen\IEEEdlabelindent +\IEEEdlabelindent \parindent + +% This is the value actually used within the IED lists. +% The IED environments automatically set its value to +% one of the three values above, so global changes do +% not have any effect +\newdimen\IEEElabelindent +\IEEElabelindent \parindent + +% The actual amount labels will be indented is +% \IEEElabelindent multiplied by the factor below +% corresponding to the level of nesting depth +% This provides a means by which the user can +% alter the effective \IEEElabelindent for deeper +% levels +% There may not be such a thing as correct "standard IEEE" +% values. What the IEEE actually does may depend on the specific +% circumstances. +% The first list level almost always has full indention. +% The second levels I've seen have only 75% of the normal indentation +% Three level or greater nestings are very rare. I am guessing +% that they don't use any indentation. +\def\IEEElabelindentfactori{1.0} % almost always one +\def\IEEElabelindentfactorii{0.75} % 0.0 or 1.0 may be used in some cases +\def\IEEElabelindentfactoriii{0.0} % 0.75? 0.5? 0.0? +\def\IEEElabelindentfactoriv{0.0} +\def\IEEElabelindentfactorv{0.0} +\def\IEEElabelindentfactorvi{0.0} + +% value actually used within IED lists, it is auto +% set to one of the 6 values above +% global changes here have no effect +\def\IEEElabelindentfactor{1.0} + +% This controls the default spacing between the end of the IED +% list labels and the list text, when normal text is used for +% the labels. +% compsoc uses a larger value here, but we'll set that later +% in the class so that this code block area can be extracted +% as-is for IEEEtrantools.sty +\newdimen\IEEEiednormlabelsep +\IEEEiednormlabelsep 0.6em + +% This controls the default spacing between the end of the IED +% list labels and the list text, when math symbols are used for +% the labels (nomenclature lists). The IEEE usually increases the +% spacing in these cases +\newdimen\IEEEiedmathlabelsep +\IEEEiedmathlabelsep 1.2em + +% This controls the extra vertical separation put above and +% below each IED list. the IEEE usually puts a little extra spacing +% around each list. However, this spacing is barely noticeable. +% compsoc uses a larger value here, but we'll set that later +% in the class so that this code block area can be extracted +% as-is for IEEEtrantools.sty +\newskip\IEEEiedtopsep +\IEEEiedtopsep 2pt plus 1pt minus 1pt + + +% This command is executed within each IED list environment +% at the beginning of the list. You can use this to set the +% parameters for some/all your IED list(s) without disturbing +% global parameters that affect things other than lists. +% i.e., renewcommand{\IEEEiedlistdecl}{\setlength{\labelsep}{5em}} +% will alter the \labelsep for the next list(s) until +% \IEEEiedlistdecl is redefined. +\def\IEEEiedlistdecl{\relax} + +% This command provides an easy way to set \leftmargin based +% on the \labelwidth, \labelsep and the argument \IEEElabelindent +% Usage: \IEEEcalcleftmargin{width-to-indent-the-label} +% output is in the \leftmargin variable, i.e., effectively: +% \leftmargin = argument + \labelwidth + \labelsep +% Note controlled spacing here, shield end of lines with % +\def\IEEEcalcleftmargin#1{\setlength{\leftmargin}{#1}% +\addtolength{\leftmargin}{\labelwidth}% +\addtolength{\leftmargin}{\labelsep}} + +% This command provides an easy way to set \labelwidth to the +% width of the given text. It is the same as +% \settowidth{\labelwidth}{label-text} +% and useful as a shorter alternative. +% Typically used to set \labelwidth to be the width +% of the longest label in the list +\def\IEEEsetlabelwidth#1{\settowidth{\labelwidth}{#1}} + +% When this command is executed, IED lists will use the +% IEEEiedmathlabelsep label separation rather than the normal +% spacing. To have an effect, this command must be executed via +% the \IEEEiedlistdecl or within the option of the IED list +% environments. +\def\IEEEusemathlabelsep{\setlength{\labelsep}{\IEEEiedmathlabelsep}} + +% A flag which controls whether the IED lists automatically +% calculate \leftmargin from \IEEElabelindent, \labelwidth and \labelsep +% Useful if you want to specify your own \leftmargin +% This flag must be set (\IEEEnocalcleftmargintrue or \IEEEnocalcleftmarginfalse) +% via the \IEEEiedlistdecl or within the option of the IED list +% environments to have an effect. +\newif\ifIEEEnocalcleftmargin +\IEEEnocalcleftmarginfalse + +% A flag which controls whether \IEEElabelindent is multiplied by +% the \IEEElabelindentfactor for each list level. +% This flag must be set via the \IEEEiedlistdecl or within the option +% of the IED list environments to have an effect. +\newif\ifIEEEnolabelindentfactor +\IEEEnolabelindentfactorfalse + + +% internal variable to indicate type of IED label +% justification +% 0 - left; 1 - center; 2 - right +\def\@IEEEiedjustify{0} + + +% commands to allow the user to control IED +% label justifications. Use these commands within +% the IED environment option or in the \IEEEiedlistdecl +% Note that changing the normal list justifications +% is nonstandard and the IEEE may not like it if you do so! +% I include these commands as they may be helpful to +% those who are using these enhanced list controls for +% other non-IEEE related LaTeX work. +% itemize and enumerate automatically default to right +% justification, description defaults to left. +\def\IEEEiedlabeljustifyl{\def\@IEEEiedjustify{0}}%left +\def\IEEEiedlabeljustifyc{\def\@IEEEiedjustify{1}}%center +\def\IEEEiedlabeljustifyr{\def\@IEEEiedjustify{2}}%right + + + + +% commands to save to and restore from the list parameter copies +% this allows us to set all the list parameters within +% the list_decl and prevent \list (and its \@list) +% from overriding any of our parameters +% V1.6 use \edefs instead of dimen's to conserve dimen registers +% Note controlled spacing here, shield end of lines with % +\def\@IEEEsavelistparams{\edef\@IEEEiedtopsep{\the\topsep}% +\edef\@IEEEiedlabelwidth{\the\labelwidth}% +\edef\@IEEEiedlabelsep{\the\labelsep}% +\edef\@IEEEiedleftmargin{\the\leftmargin}% +\edef\@IEEEiedpartopsep{\the\partopsep}% +\edef\@IEEEiedparsep{\the\parsep}% +\edef\@IEEEieditemsep{\the\itemsep}% +\edef\@IEEEiedrightmargin{\the\rightmargin}% +\edef\@IEEEiedlistparindent{\the\listparindent}% +\edef\@IEEEieditemindent{\the\itemindent}} + +% Note controlled spacing here +\def\@IEEErestorelistparams{\topsep\@IEEEiedtopsep\relax% +\labelwidth\@IEEEiedlabelwidth\relax% +\labelsep\@IEEEiedlabelsep\relax% +\leftmargin\@IEEEiedleftmargin\relax% +\partopsep\@IEEEiedpartopsep\relax% +\parsep\@IEEEiedparsep\relax% +\itemsep\@IEEEieditemsep\relax% +\rightmargin\@IEEEiedrightmargin\relax% +\listparindent\@IEEEiedlistparindent\relax% +\itemindent\@IEEEieditemindent\relax} + + +% v1.6b provide original LaTeX IED list environments +% note that latex.ltx defines \itemize and \enumerate, but not \description +% which must be created by the base classes +% save original LaTeX itemize and enumerate +\let\LaTeXitemize\itemize +\let\endLaTeXitemize\enditemize +\let\LaTeXenumerate\enumerate +\let\endLaTeXenumerate\endenumerate + +% provide original LaTeX description environment from article.cls +\newenvironment{LaTeXdescription} + {\list{}{\labelwidth\z@ \itemindent-\leftmargin + \let\makelabel\descriptionlabel}} + {\endlist} +\newcommand*\descriptionlabel[1]{\hspace\labelsep + \normalfont\bfseries #1} + + +% override LaTeX's default IED lists +\def\itemize{\@IEEEitemize} +\def\enditemize{\@endIEEEitemize} +\def\enumerate{\@IEEEenumerate} +\def\endenumerate{\@endIEEEenumerate} +\def\description{\@IEEEdescription} +\def\enddescription{\@endIEEEdescription} + +% provide the user with aliases - may help those using packages that +% override itemize, enumerate, or description +\def\IEEEitemize{\@IEEEitemize} +\def\endIEEEitemize{\@endIEEEitemize} +\def\IEEEenumerate{\@IEEEenumerate} +\def\endIEEEenumerate{\@endIEEEenumerate} +\def\IEEEdescription{\@IEEEdescription} +\def\endIEEEdescription{\@endIEEEdescription} + + +% V1.6 we want to keep the IEEEtran IED list definitions as our own internal +% commands so they are protected against redefinition +\def\@IEEEitemize{\@ifnextchar[{\@@IEEEitemize}{\@@IEEEitemize[\relax]}} +\def\@IEEEenumerate{\@ifnextchar[{\@@IEEEenumerate}{\@@IEEEenumerate[\relax]}} +\def\@IEEEdescription{\@ifnextchar[{\@@IEEEdescription}{\@@IEEEdescription[\relax]}} +\def\@endIEEEitemize{\endlist} +\def\@endIEEEenumerate{\endlist} +\def\@endIEEEdescription{\endlist} + + +% DO NOT ALLOW BLANK LINES TO BE IN THESE IED ENVIRONMENTS +% AS THIS WILL FORCE NEW PARAGRAPHS AFTER THE IED LISTS +% IEEEtran itemized list MDS 1/2001 +% Note controlled spacing here, shield end of lines with % +\def\@@IEEEitemize[#1]{% + \ifnum\@itemdepth>3\relax\@toodeep\else% + \ifnum\@listdepth>5\relax\@toodeep\else% + \advance\@itemdepth\@ne% + \edef\@itemitem{labelitem\romannumeral\the\@itemdepth}% + % get the IEEElabelindentfactor for this level + \advance\@listdepth\@ne% we need to know what the level WILL be + \edef\IEEElabelindentfactor{\csname IEEElabelindentfactor\romannumeral\the\@listdepth\endcsname}% + \advance\@listdepth-\@ne% undo our increment + \def\@IEEEiedjustify{2}% right justified labels are default + % set other defaults + \IEEEnocalcleftmarginfalse% + \IEEEnolabelindentfactorfalse% + \topsep\IEEEiedtopsep% + \IEEElabelindent\IEEEilabelindent% + \labelsep\IEEEiednormlabelsep% + \partopsep 0ex% + \parsep 0ex% + \itemsep 0ex% + \rightmargin 0em% + \listparindent 0em% + \itemindent 0em% + % calculate the label width + % the user can override this later if + % they specified a \labelwidth + \settowidth{\labelwidth}{\csname labelitem\romannumeral\the\@itemdepth\endcsname}% + \@IEEEsavelistparams% save our list parameters + \list{\csname\@itemitem\endcsname}{% + \@IEEErestorelistparams% override any list{} changes + % to our globals + \let\makelabel\@IEEEiedmakelabel% v1.6b setup \makelabel + \IEEEiedlistdecl% let user alter parameters + #1\relax% + % If the user has requested not to use the + % IEEElabelindent factor, don't revise \IEEElabelindent + \ifIEEEnolabelindentfactor\relax% + \else\IEEElabelindent=\IEEElabelindentfactor\IEEElabelindent% + \fi% + % Unless the user has requested otherwise, + % calculate our left margin based + % on \IEEElabelindent, \labelwidth and + % \labelsep + \ifIEEEnocalcleftmargin\relax% + \else\IEEEcalcleftmargin{\IEEElabelindent}% + \fi}\fi\fi}% + + +% DO NOT ALLOW BLANK LINES TO BE IN THESE IED ENVIRONMENTS +% AS THIS WILL FORCE NEW PARAGRAPHS AFTER THE IED LISTS +% IEEEtran enumerate list MDS 1/2001 +% Note controlled spacing here, shield end of lines with % +\def\@@IEEEenumerate[#1]{% + \ifnum\@enumdepth>3\relax\@toodeep\else% + \ifnum\@listdepth>5\relax\@toodeep\else% + \advance\@enumdepth\@ne% + \edef\@enumctr{enum\romannumeral\the\@enumdepth}% + % get the IEEElabelindentfactor for this level + \advance\@listdepth\@ne% we need to know what the level WILL be + \edef\IEEElabelindentfactor{\csname IEEElabelindentfactor\romannumeral\the\@listdepth\endcsname}% + \advance\@listdepth-\@ne% undo our increment + \def\@IEEEiedjustify{2}% right justified labels are default + % set other defaults + \IEEEnocalcleftmarginfalse% + \IEEEnolabelindentfactorfalse% + \topsep\IEEEiedtopsep% + \IEEElabelindent\IEEEelabelindent% + \labelsep\IEEEiednormlabelsep% + \partopsep 0ex% + \parsep 0ex% + \itemsep 0ex% + \rightmargin 0em% + \listparindent 0em% + \itemindent 0em% + % calculate the label width + % We'll set it to the width suitable for all labels using + % normalfont 1) to 9) + % The user can override this later + \settowidth{\labelwidth}{9)}% + \@IEEEsavelistparams% save our list parameters + \list{\csname label\@enumctr\endcsname}{\usecounter{\@enumctr}% + \@IEEErestorelistparams% override any list{} changes + % to our globals + \let\makelabel\@IEEEiedmakelabel% v1.6b setup \makelabel + \IEEEiedlistdecl% let user alter parameters + #1\relax% + % If the user has requested not to use the + % IEEElabelindent factor, don't revise \IEEElabelindent + \ifIEEEnolabelindentfactor\relax% + \else\IEEElabelindent=\IEEElabelindentfactor\IEEElabelindent% + \fi% + % Unless the user has requested otherwise, + % calculate our left margin based + % on \IEEElabelindent, \labelwidth and + % \labelsep + \ifIEEEnocalcleftmargin\relax% + \else\IEEEcalcleftmargin{\IEEElabelindent}% + \fi}\fi\fi}% + + +% DO NOT ALLOW BLANK LINES TO BE IN THESE IED ENVIRONMENTS +% AS THIS WILL FORCE NEW PARAGRAPHS AFTER THE IED LISTS +% IEEEtran description list MDS 1/2001 +% Note controlled spacing here, shield end of lines with % +\def\@@IEEEdescription[#1]{% + \ifnum\@listdepth>5\relax\@toodeep\else% + % get the IEEElabelindentfactor for this level + \advance\@listdepth\@ne% we need to know what the level WILL be + \edef\IEEElabelindentfactor{\csname IEEElabelindentfactor\romannumeral\the\@listdepth\endcsname}% + \advance\@listdepth-\@ne% undo our increment + \def\@IEEEiedjustify{0}% left justified labels are default + % set other defaults + \IEEEnocalcleftmarginfalse% + \IEEEnolabelindentfactorfalse% + \topsep\IEEEiedtopsep% + \IEEElabelindent\IEEEdlabelindent% + % assume normal labelsep + \labelsep\IEEEiednormlabelsep% + \partopsep 0ex% + \parsep 0ex% + \itemsep 0ex% + \rightmargin 0em% + \listparindent 0em% + \itemindent 0em% + % Bogus label width in case the user forgets + % to set it. + % TIP: If you want to see what a variable's width is you + % can use the TeX command \showthe\width-variable to + % display it on the screen during compilation + % (This might be helpful to know when you need to find out + % which label is the widest) + \settowidth{\labelwidth}{Hello}% + \@IEEEsavelistparams% save our list parameters + \list{}{\@IEEErestorelistparams% override any list{} changes + % to our globals + \let\makelabel\@IEEEiedmakelabel% v1.6b setup \makelabel + \IEEEiedlistdecl% let user alter parameters + #1\relax% + % If the user has requested not to use the + % labelindent factor, don't revise \IEEElabelindent + \ifIEEEnolabelindentfactor\relax% + \else\IEEElabelindent=\IEEElabelindentfactor\IEEElabelindent% + \fi% + % Unless the user has requested otherwise, + % calculate our left margin based + % on \IEEElabelindent, \labelwidth and + % \labelsep + \ifIEEEnocalcleftmargin\relax% + \else\IEEEcalcleftmargin{\IEEElabelindent}\relax% + \fi}\fi} + +% v1.6b we use one makelabel that does justification as needed. +\def\@IEEEiedmakelabel#1{\relax\if\@IEEEiedjustify 0\relax +\makebox[\labelwidth][l]{\normalfont #1}\else +\if\@IEEEiedjustify 1\relax +\makebox[\labelwidth][c]{\normalfont #1}\else +\makebox[\labelwidth][r]{\normalfont #1}\fi\fi} + + +% compsoc uses a larger value for the normal labelsep +% and also extra spacing above and below each list +\ifCLASSOPTIONcompsoc + \IEEEiednormlabelsep 1.2em + \IEEEiedtopsep 6pt plus 3pt minus 3pt +\fi + + +% VERSE and QUOTE +% V1.7 define environments with newenvironment +\newenvironment{verse}{\let\\=\@centercr + \list{}{\itemsep\z@ \itemindent -1.5em \listparindent \itemindent + \rightmargin\leftmargin\advance\leftmargin 1.5em}\item\relax} + {\endlist} +\newenvironment{quotation}{\list{}{\listparindent 1.5em \itemindent\listparindent + \rightmargin\leftmargin \parsep 0pt plus 1pt}\item\relax} + {\endlist} +\newenvironment{quote}{\list{}{\rightmargin\leftmargin}\item\relax} + {\endlist} + + +% \titlepage +% provided only for backward compatibility. \maketitle is the correct +% way to create the title page. +\def\titlepage{\@restonecolfalse\if@twocolumn\@restonecoltrue\onecolumn + \else \newpage \fi \thispagestyle{empty}\c@page\z@} +\def\endtitlepage{\if@restonecol\twocolumn \else \newpage \fi} + +% standard values from article.cls +\arraycolsep 5pt +\arrayrulewidth .4pt +\doublerulesep 2pt + +\tabcolsep 6pt +\tabbingsep 0.5em + + +%% FOOTNOTES +% +%\skip\footins 10pt plus 4pt minus 2pt +% V1.6 respond to changes in font size +% space added above the footnotes (if present) +\skip\footins 0.9\baselineskip plus 0.4\baselineskip minus 0.2\baselineskip + +% V1.6, we need to make \footnotesep responsive to changes +% in \baselineskip or strange spacings will result when in +% draft mode. Here is a little LaTeX secret - \footnotesep +% determines the height of an invisible strut that is placed +% *above* the baseline of footnotes after the first. Since +% LaTeX considers the space for characters to be 0.7\baselineskip +% above the baseline and 0.3\baselineskip below it, we need to +% use 0.7\baselineskip as a \footnotesep to maintain equal spacing +% between all the lines of the footnotes. The IEEE often uses a tad +% more, so use 0.8\baselineskip. This slightly larger value also helps +% the text to clear the footnote marks. Note that \thanks in IEEEtran +% uses its own value of \footnotesep which is set in \maketitle. +{\footnotesize +\global\footnotesep 0.8\baselineskip} + + +\skip\@mpfootins = \skip\footins +\fboxsep = 3pt +\fboxrule = .4pt +% V1.6 use 1em, then use LaTeX2e's \@makefnmark +% Note that the IEEE normally *left* aligns the footnote marks, so we don't need +% box resizing tricks here. +\long\def\@makefntext#1{\parindent 1em\indent\hbox{\@makefnmark}#1}% V1.6 use 1em +% V1.7 compsoc does not use superscipts for footnote marks +\ifCLASSOPTIONcompsoc +\def\@IEEEcompsocmakefnmark{\hbox{\normalfont\@thefnmark.\ }} +\long\def\@makefntext#1{\parindent 1em\indent\hbox{\@IEEEcompsocmakefnmark}#1} +\fi + +% The IEEE does not use footnote rules +\def\footnoterule{} + +% V1.7 for compsoc, the IEEE uses a footnote rule only for \thanks. We devise a "one-shot" +% system to implement this. +\newif\if@IEEEenableoneshotfootnoterule +\@IEEEenableoneshotfootnoterulefalse +\ifCLASSOPTIONcompsoc +\def\footnoterule{\relax\if@IEEEenableoneshotfootnoterule +\kern-5pt +\hbox to \columnwidth{\hfill\vrule width 0.5\columnwidth height 0.4pt\hfill} +\kern4.6pt +\global\@IEEEenableoneshotfootnoterulefalse +\else +\relax +\fi} +\fi + +% V1.6 do not allow LaTeX to break a footnote across multiple pages +\interfootnotelinepenalty=10000 + +% V1.6 discourage breaks within equations +% Note that amsmath normally sets this to 10000, +% but LaTeX2e normally uses 100. +\interdisplaylinepenalty=2500 + +% default allows section depth up to /paragraph +\setcounter{secnumdepth}{4} + +% technotes do not allow /paragraph +\ifCLASSOPTIONtechnote + \setcounter{secnumdepth}{3} +\fi +% neither do compsoc conferences +\@IEEEcompsocconfonly{\setcounter{secnumdepth}{3}} + + +\newcounter{section} +\newcounter{subsection}[section] +\newcounter{subsubsection}[subsection] +\newcounter{paragraph}[subsubsection] + +% used only by IEEEtran's IEEEeqnarray as other packages may +% have their own, different, implementations +\newcounter{IEEEsubequation}[equation] + +% as shown when called by user from \ref, \label and in table of contents +\def\theequation{\arabic{equation}} % 1 +\def\theIEEEsubequation{\theequation\alph{IEEEsubequation}} % 1a (used only by IEEEtran's IEEEeqnarray) +\ifCLASSOPTIONcompsoc +% compsoc is all arabic +\def\thesection{\arabic{section}} +\def\thesubsection{\thesection.\arabic{subsection}} +\def\thesubsubsection{\thesubsection.\arabic{subsubsection}} +\def\theparagraph{\thesubsubsection.\arabic{paragraph}} +\else +\def\thesection{\Roman{section}} % I +% V1.7, \mbox prevents breaks around - +\def\thesubsection{\mbox{\thesection-\Alph{subsection}}} % I-A +% V1.7 use I-A1 format used by the IEEE rather than I-A.1 +\def\thesubsubsection{\thesubsection\arabic{subsubsection}} % I-A1 +\def\theparagraph{\thesubsubsection\alph{paragraph}} % I-A1a +\fi + +% From Heiko Oberdiek. Because of the \mbox in \thesubsection, we need to +% tell hyperref to disable the \mbox command when making PDF bookmarks. +% This done already with hyperref.sty version 6.74o and later, but +% it will not hurt to do it here again for users of older versions. +\@ifundefined{pdfstringdefPreHook}{\let\pdfstringdefPreHook\@empty}{}% +\g@addto@macro\pdfstringdefPreHook{\let\mbox\relax} + + +% Main text forms (how shown in main text headings) +% V1.6, using \thesection in \thesectiondis allows changes +% in the former to automatically appear in the latter +\ifCLASSOPTIONcompsoc + \ifCLASSOPTIONconference% compsoc conference + \def\thesectiondis{\thesection.} + \def\thesubsectiondis{\thesectiondis\arabic{subsection}.} + \def\thesubsubsectiondis{\thesubsectiondis\arabic{subsubsection}.} + \def\theparagraphdis{\thesubsubsectiondis\arabic{paragraph}.} + \else% compsoc not conferencs + \def\thesectiondis{\thesection} + \def\thesubsectiondis{\thesectiondis.\arabic{subsection}} + \def\thesubsubsectiondis{\thesubsectiondis.\arabic{subsubsection}} + \def\theparagraphdis{\thesubsubsectiondis.\arabic{paragraph}} + \fi +\else% not compsoc + \def\thesectiondis{\thesection.} % I. + \def\thesubsectiondis{\Alph{subsection}.} % B. + \def\thesubsubsectiondis{\arabic{subsubsection})} % 3) + \def\theparagraphdis{\alph{paragraph})} % d) +\fi + +% just like LaTeX2e's \@eqnnum +\def\theequationdis{{\normalfont \normalcolor (\theequation)}}% (1) +% IEEEsubequation used only by IEEEtran's IEEEeqnarray +\def\theIEEEsubequationdis{{\normalfont \normalcolor (\theIEEEsubequation)}}% (1a) +% redirect LaTeX2e's equation number display and all that depend on +% it, through IEEEtran's \theequationdis +\def\@eqnnum{\theequationdis} + + + +% V1.7 provide string macros as article.cls does +\def\contentsname{Contents} +\def\listfigurename{List of Figures} +\def\listtablename{List of Tables} +\def\refname{References} +\def\indexname{Index} +\def\figurename{Fig.} +\def\tablename{TABLE} +\@IEEEcompsocconfonly{\def\figurename{Figure}} +\def\partname{Part} +\def\appendixname{Appendix} +\def\abstractname{Abstract} +% IEEE specific names +\def\IEEEkeywordsname{Index Terms} +\def\IEEEproofname{Proof} + + +% LIST OF FIGURES AND TABLES AND TABLE OF CONTENTS +% +\def\@pnumwidth{1.55em} +\def\@tocrmarg{2.55em} +\def\@dotsep{4.5} +\setcounter{tocdepth}{3} + +% adjusted some spacings here so that section numbers will not easily +% collide with the section titles. +% VIII; VIII-A; and VIII-A.1 are usually the worst offenders. +% MDS 1/2001 +\def\tableofcontents{\section*{\contentsname}\@starttoc{toc}} +\def\l@section#1#2{\addpenalty{\@secpenalty}\addvspace{1.0em plus 1pt}% + \@tempdima 2.75em \begingroup \parindent \z@ \rightskip \@pnumwidth% + \parfillskip-\@pnumwidth {\bfseries\leavevmode #1}\hfil\hbox to\@pnumwidth{\hss #2}\par% + \endgroup} +% argument format #1:level, #2:labelindent,#3:labelsep +\def\l@subsection{\@dottedtocline{2}{2.75em}{3.75em}} +\def\l@subsubsection{\@dottedtocline{3}{6.5em}{4.5em}} +% must provide \l@ defs for ALL sublevels EVEN if tocdepth +% is such as they will not appear in the table of contents +% these defs are how TOC knows what level these things are! +\def\l@paragraph{\@dottedtocline{4}{6.5em}{5.5em}} +\def\l@subparagraph{\@dottedtocline{5}{6.5em}{6.5em}} +\def\listoffigures{\section*{\listfigurename}\@starttoc{lof}} +\def\l@figure{\@dottedtocline{1}{0em}{2.75em}} +\def\listoftables{\section*{\listtablename}\@starttoc{lot}} +\let\l@table\l@figure + + +% Definitions for floats +% +% Normal Floats +% V1.8 floatsep et al. revised down by 0.15\baselineskip +% to account for the sideeffects of \topskip compensation +\floatsep 0.85\baselineskip plus 0.2\baselineskip minus 0.2\baselineskip +\textfloatsep 1.55\baselineskip plus 0.2\baselineskip minus 0.4\baselineskip +\@fptop 0pt plus 1fil +\@fpsep 0.75\baselineskip plus 2fil +\@fpbot 0pt plus 1fil +\def\topfraction{0.9} +\def\bottomfraction{0.4} +\def\floatpagefraction{0.8} +% V1.7, let top floats approach 90% of page +\def\textfraction{0.1} + +% Double Column Floats +\dblfloatsep 0.85\baselineskip plus 0.2\baselineskip minus 0.2\baselineskip + +\dbltextfloatsep 1.55\baselineskip plus 0.2\baselineskip minus 0.4\baselineskip +% Note that it would be nice if the rubber here actually worked in LaTeX2e. +% There is a long standing limitation in LaTeX, first discovered (to the best +% of my knowledge) by Alan Jeffrey in 1992. LaTeX ignores the stretchable +% portion of \dbltextfloatsep, and as a result, double column figures can and +% do result in an non-integer number of lines in the main text columns with +% underfull vbox errors as a consequence. A post to comp.text.tex +% by Donald Arseneau confirms that this had not yet been fixed in 1998. +% IEEEtran V1.6 will fix this problem for you in the titles, but it doesn't +% protect you from other double floats. Happy vspace'ing. + +\@dblfptop 0pt plus 1fil +\@dblfpsep 0.75\baselineskip plus 2fil +\@dblfpbot 0pt plus 1fil +\def\dbltopfraction{0.8} +\def\dblfloatpagefraction{0.8} +\setcounter{dbltopnumber}{4} + +\intextsep 0.85\baselineskip plus 0.2\baselineskip minus 0.2\baselineskip +\setcounter{topnumber}{2} +\setcounter{bottomnumber}{2} +\setcounter{totalnumber}{4} + + + +% article class provides these, we should too. +\newlength\abovecaptionskip +\newlength\belowcaptionskip +% but only \abovecaptionskip is used above figure captions and *below* table +% captions +\setlength\abovecaptionskip{0.5\baselineskip} +% compsoc journals are a little more generous +\ifCLASSOPTIONcompsoc\ifCLASSOPTIONjournal + \setlength\abovecaptionskip{0.75\baselineskip} +\fi\fi +\setlength\belowcaptionskip{0pt} +% V1.6 create hooks in case the caption spacing ever needs to be +% overridden by a user +\def\@IEEEfigurecaptionsepspace{\vskip\abovecaptionskip\relax}% +\def\@IEEEtablecaptionsepspace{\vskip\abovecaptionskip\relax}% + + +% 1.6b revise caption system so that \@makecaption uses two arguments +% as with LaTeX2e. Otherwise, there will be problems when using hyperref. +\def\@IEEEtablestring{table} + + +% V1.8 compensate for \topskip so top of top figures align with tops of the first lines of main text +% here we calculate a space equal to the amount \topskip exceeds the main text height +% we hook in at \@floatboxreset +\def\@IEEEfiguretopskipspace{\ifdim\prevdepth=-1000pt\relax +\setlength{\@IEEEtrantmpdimenA}{1\topskip}\relax +\addtolength{\@IEEEtrantmpdimenA}{-0.7\@IEEEnormalsizeunitybaselineskip}\relax +\vspace*{\@IEEEtrantmpdimenA}\fi} +% V1.8 compensate for \topskip at the top of top tables so caption text is on main text baseline +% use a strut set on the caption baseline within \@makecaption +\def\@IEEEtabletopskipstrut{\ifdim\prevdepth=-1000pt\rule{0pt}{\topskip}\fi} +% the \ifdim\prevdepth checks are always expected to be true for IEEE style float caption ordering +% because top of figure content and top of captions in tables is the first thing on the vertical +% list of these floats +% thanks to Donald Arseneau for his 2000/11/11 post "Re: caption hacking" with info on this topic. + + +\ifCLASSOPTIONcompsoc +% V1.7 compsoc \@makecaption +\ifCLASSOPTIONconference% compsoc conference +\long\def\@makecaption#1#2{% +% test if is a for a figure or table +\ifx\@captype\@IEEEtablestring% +% if a table, do table caption +\footnotesize\bgroup\par\centering\@IEEEtabletopskipstrut{\normalfont\footnotesize {#1.}\nobreakspace\scshape #2}\par\addvspace{0.5\baselineskip}\egroup% +\@IEEEtablecaptionsepspace +% if not a table, format it as a figure +\else +\@IEEEfigurecaptionsepspace +\setbox\@tempboxa\hbox{\normalfont\footnotesize {#1.}\nobreakspace #2}% +\ifdim \wd\@tempboxa >\hsize% +% if caption is longer than a line, let it wrap around +\setbox\@tempboxa\hbox{\normalfont\footnotesize {#1.}\nobreakspace}% +\parbox[t]{\hsize}{\normalfont\footnotesize \noindent\unhbox\@tempboxa#2}% +% if caption is shorter than a line, center +\else% +\hbox to\hsize{\normalfont\footnotesize\hfil\box\@tempboxa\hfil}% +\fi\fi} +% +\else% nonconference compsoc +\long\def\@makecaption#1#2{% +% test if is a for a figure or table +\ifx\@captype\@IEEEtablestring% +% if a table, do table caption +\footnotesize\bgroup\par\centering\@IEEEtabletopskipstrut{\normalfont\sffamily\footnotesize #1}\\{\normalfont\sffamily\footnotesize #2}\par\addvspace{0.5\baselineskip}\egroup% +\@IEEEtablecaptionsepspace +% if not a table, format it as a figure +\else +\@IEEEfigurecaptionsepspace +\setbox\@tempboxa\hbox{\normalfont\sffamily\footnotesize {#1.}\nobreakspace #2}% +\ifdim \wd\@tempboxa >\hsize% +% if caption is longer than a line, let it wrap around +\setbox\@tempboxa\hbox{\normalfont\sffamily\footnotesize {#1.}\nobreakspace}% +\parbox[t]{\hsize}{\normalfont\sffamily\footnotesize \noindent\unhbox\@tempboxa#2}% +% if caption is shorter than a line, left justify +\else% +\hbox to\hsize{\normalfont\sffamily\footnotesize\box\@tempboxa\hfil}% +\fi\fi} +\fi +% +\else% traditional noncompsoc \@makecaption +\long\def\@makecaption#1#2{% +% test if is a for a figure or table +\ifx\@captype\@IEEEtablestring% +% if a table, do table caption +\footnotesize\bgroup\par\centering\@IEEEtabletopskipstrut{\normalfont\footnotesize #1}\\{\normalfont\footnotesize\scshape #2}\par\addvspace{0.5\baselineskip}\egroup% +\@IEEEtablecaptionsepspace +% if not a table, format it as a figure +\else +\@IEEEfigurecaptionsepspace +% 3/2001 use footnotesize, not small; use two nonbreaking spaces, not one +\setbox\@tempboxa\hbox{\normalfont\footnotesize {#1.}\nobreakspace\nobreakspace #2}% +\ifdim \wd\@tempboxa >\hsize% +% if caption is longer than a line, let it wrap around +\setbox\@tempboxa\hbox{\normalfont\footnotesize {#1.}\nobreakspace\nobreakspace}% +\parbox[t]{\hsize}{\normalfont\footnotesize\noindent\unhbox\@tempboxa#2}% +% if caption is shorter than a line, center if conference, left justify otherwise +\else% +\ifCLASSOPTIONconference \hbox to\hsize{\normalfont\footnotesize\hfil\box\@tempboxa\hfil}% +\else \hbox to\hsize{\normalfont\footnotesize\box\@tempboxa\hfil}% +\fi\fi\fi} +\fi + + + +% V1.7 disable captions class option, do so in a way that retains operation of \label +% within \caption +\ifCLASSOPTIONcaptionsoff +\long\def\@makecaption#1#2{\vspace*{2em}\footnotesize\bgroup\par\addvspace{0.5\baselineskip}\centering{\footnotesize #1}\par\addvspace{0.5\baselineskip}\egroup% +\let\@IEEEtemporiglabeldefsave\label +\let\@IEEEtemplabelargsave\relax +\def\label##1{\gdef\@IEEEtemplabelargsave{##1}}% +\setbox\@tempboxa\hbox{#2}% +\let\label\@IEEEtemporiglabeldefsave +\ifx\@IEEEtemplabelargsave\relax\else\label{\@IEEEtemplabelargsave}\fi} +\fi + + +% V1.7 define end environments with \def not \let so as to work OK with +% preview-latex +\newcounter{figure} +\def\thefigure{\@arabic\c@figure} +\def\fps@figure{tbp} +\def\ftype@figure{1} +\def\ext@figure{lof} +\def\fnum@figure{\figurename\nobreakspace\thefigure} +% V1.8 within figures add \@IEEEfiguretopskipspace compensation to LaTeX2e's \@floatboxreset +\def\figure{\def\@floatboxreset{\reset@font\normalsize\@setminipage\@IEEEfiguretopskipspace}\@float{figure}} +\def\endfigure{\end@float} +% V1.8 also add \@IEEEfiguretopskipspace compensation to \figure* +\@namedef{figure*}{\def\@floatboxreset{\reset@font\normalsize\@setminipage\@IEEEfiguretopskipspace}\@dblfloat{figure}} +\@namedef{endfigure*}{\end@dblfloat} + +\newcounter{table} +\ifCLASSOPTIONcompsoc +\def\thetable{\arabic{table}} +\else +\def\thetable{\@Roman\c@table} +\fi +\def\fps@table{tbp} +\def\ftype@table{2} +\def\ext@table{lot} +\def\fnum@table{\tablename\nobreakspace\thetable} +% V1.6 The IEEE uses 8pt text for tables +% within tables alter LaTeX2e's \@floatboxreset to use \footnotesize +\def\table{\def\@floatboxreset{\reset@font\footnotesize\@setminipage}\@float{table}} +\def\endtable{\end@float} +% v1.6b double column tables need to default to footnotesize as well. +\@namedef{table*}{\def\@floatboxreset{\reset@font\footnotesize\@setminipage}\@dblfloat{table}} +\@namedef{endtable*}{\end@dblfloat} + + + + +%% -- Command Argument Scanning Support Functions -- +%% V1.8a + +% usage: \@IEEEstripouterbraces*{} +% \@IEEEstripouterbraces fully expands its argument (which it then stores +% in \@IEEEstripouterbracesarg) via \edef, then removes any outer enclosing +% braces, and finally stores the result in the macro +% \@IEEEstrippedouterbraces. +% +% For example: +% \@IEEEstripouterbraces{{{{ab}c}}} +% results in: +% +% \@IEEEstripouterbracesarg ==> a macro containing {{{ab}c}} +% \@IEEEstrippedouterbraces ==> a macro containing {ab}c +% +% the *-star form,\@IEEEstripouterbraces*, does not expand the argument +% contents during processing +\def\@IEEEstripouterbraces{\@ifstar{\let\@IEEEstripouterbracesdef=\def\@@IEEEstripouterbraces}{\let\@IEEEstripouterbracesdef=\edef\@@IEEEstripouterbraces}} + +\def\@@IEEEstripouterbraces#1{\@IEEEstripouterbracesdef\@IEEEstripouterbracesarg{#1}\relax +% If the macro is unchanged after being acquired as a single delimited +% argument, we know we have one sequence of tokens without any enclosing +% braces. Loop until this is true. +\loop + \expandafter\@@@IEEEstripouterbraces\@IEEEstripouterbracesarg\@IEEEgeneralsequenceDELIMITER +\ifx\@IEEEstrippedouterbraces\@IEEEstripouterbracesarg +\else + \let\@IEEEstripouterbracesarg\@IEEEstrippedouterbraces +\repeat} + +\def\@@@IEEEstripouterbraces#1\@IEEEgeneralsequenceDELIMITER{\def\@IEEEstrippedouterbraces{#1}} + + + +% usage: \@IEEEextractgroup*{} +% \@IEEEextractgroup fully expands its argument (which it then stores in +% \@IEEEextractgrouparg) via \edef and then assigns the first "brace group" +% of tokens to the macro \@IEEEextractedgroup. +% The remaining groups, if any, are stored in the macro +% \@IEEEextractedgroupremain. If the argument does not contain the requisite +% groups, the respective macros will be defined to be empty. +% There is an asymmetry in that \@IEEEextractedgroup is stripped of its first +% outer grouping while \@IEEEextractedgroupremain retains even the outer +% grouping (if present) that originally identified it as a group. +% +% For example: +% \@IEEEextractgroup{{{ab}}{c{de}}} +% results in: +% +% \@IEEEextractgrouparg ==> a macro containing {{ab}}{c{de}} +% \@IEEEextractedgroup ==> a macro containing {ab} +% \@IEEEextractedgroupremain ==> a macro containing {c{de}} +% +% The *-star form, \@IEEEextractgroup*, does not expand its argument +% contents during processing. +\def\@IEEEextractgroup{\@ifstar{\let\@IEEEextractgroupdef=\def\@@IEEEextractgroup}{\let\@IEEEextractgroupdef=\edef\@@IEEEextractgroup}} + +\def\@@IEEEextractgroup#1{\@IEEEextractgroupdef\@IEEEextractgrouparg{#1}\relax +% trap the case of an empty extracted group as this would cause problems with +% \@IEEEextractgroupremain's argument acquisition +\ifx\@IEEEextractgrouparg\@empty + \def\@IEEEextractedgroup{}\relax + \def\@IEEEextractedgroupremain{}\relax +\else + % We have to use some dirty tricks here. We want to insert {} around + % whatever remains after the first group so that TeX's argument scanner + % will preserve any originally enclosing braces as well as provide an + % empty argument to acquire even if there isn't a second group. + % In this first of two dirty tricks, we put a } at the end of the structure + % we are going to extract from. The \ifnum0=`{\fi keeps TeX happy to allow + % what would otherwise be an unbalanced macro definition for + % \@@IEEEextractgroup to be acceptable to it. + \ifnum0=`{\fi\expandafter\@IEEEextractgroupremain\@IEEEextractgrouparg}\relax +\fi} + +% In the second part of the dirty tricks, we insert a leading { right after +% the first group is acquired, but before the remainder is. Again, the +% \ifnum0=`}\fi keeps TeX happy during definition time, but will disappear +% during run time. +\def\@IEEEextractgroupremain#1{\def\@IEEEextractedgroup{#1}\expandafter\@@IEEEextractgroupremain\expandafter{\ifnum0=`}\fi} + +\def\@@IEEEextractgroupremain#1{\def\@IEEEextractedgroupremain{#1}} + + + +% \@IEEEextracttoken relocated at top because margin setting commands rely on it + + + +% usage: \@IEEEextracttokengroups*{} +% \@IEEEextracttokengroups fully expands its argument (which it then stores +% in \@IEEEextracttokengroupsarg) and then assigns the first "brace group" of +% tokens (with the outermost braces removed) to the macro +% \@IEEEextractedfirstgroup. +% The meaning of the first nonbrace (but including the empty group) token +% within this first group is assigned via \let to \@IEEEextractedfirsttoken +% as well as stored in the macro \@IEEEextractedfirsttokenmacro. If a first +% nonbrace token does not exist (or is an empty group), these will be \relax +% and empty, respectively. Tokens that would otherwise be discarded during +% the acquisition of the first token in the first group are stored in +% \@IEEEextractedfirsttokensdiscarded, however their original relative brace +% nesting depths are not guaranteed to be preserved. +% The first group within this first group is stored in the macro +% \@IEEEextractedfirstfirstgroup. +% Likewise for the next group after the first: \@IEEEextractednextgroup, +% \@IEEEextractednextfirstgroup, \@IEEEextractednextgroupfirsttoken, +% \@IEEEextractednextgroupfirsttokenmacro, and +% \@IEEEextractednextfirsttokensdiscarded. +% All tokens/groups after the first group, including any enclosing braces, +% are stored in the macro \@IEEEextractedafterfirstgroupremain which will +% be empty if none exist. +% +% For example: +% \@IEEEextracttokengroups{{{ab}{cd}}{{ef}g}} +% will result in: +% +% \@IEEEextracttokengroupsarg ==> a macro containing {{ab}{cd}}{{ef}g} +% \@IEEEextractedfirstgroup ==> a macro containing {ab}{cd} +% \@IEEEextractedafterfirstgroupremain ==> a macro containing {{ef}g} +% \@IEEEextractedfirsttoken ==> the letter a +% \@IEEEextractedfirsttokenmacro ==> a macro containing a +% \@IEEEextractedfirsttokensdiscarded ==> a macro containing bcd +% \@IEEEextractedfirstfirstgroup ==> a macro containing ab +% \@IEEEextractednextgroup ==> a macro containing {ef}g +% \@IEEEextractednextfirsttoken ==> the letter e +% \@IEEEextractednextfirsttokenmacro ==> a macro containing e +% \@IEEEextractednextfirsttokensdiscarded ==> a macro containing fg +% \@IEEEextractednextfirstgroup ==> a macro containing ef +% +% If given an empty argument, \@IEEEextractedfirsttoken and +% \@IEEEextractednextfirsttoken will be set to \relax +% and all the macros will be empty. +% the *-star form, \@IEEEextracttokengroups*, does not expand its argument +% contents during processing. +% +% Depends on: \@IEEEextractgroup, \@IEEEextracttoken +\def\@IEEEextracttokengroups{\@ifstar{\let\@IEEEextracttokengroupsdef=\def\@@IEEEextracttokengroups}{\let\@IEEEextracttokengroupsdef=\edef\@@IEEEextracttokengroups}} +\def\@@IEEEextracttokengroups#1{\@IEEEextracttokengroupsdef\@IEEEextracttokengroupsarg{#1}\relax +% begin extraction, these functions are safe with empty arguments +% first group +\expandafter\@IEEEextractgroup\expandafter*\expandafter{\@IEEEextracttokengroupsarg}\relax +\let\@IEEEextractedfirstgroup\@IEEEextractedgroup +\let\@IEEEextractedafterfirstgroupremain\@IEEEextractedgroupremain +\expandafter\@IEEEextracttoken\expandafter*\expandafter{\@IEEEextractedfirstgroup}\relax +\let\@IEEEextractedfirsttoken\@IEEEextractedtoken +\let\@IEEEextractedfirsttokenmacro\@IEEEextractedtokenmacro +\let\@IEEEextractedfirsttokensdiscarded\@IEEEextractedtokensdiscarded +% first first group +\expandafter\@IEEEextractgroup\expandafter*\expandafter{\@IEEEextractedfirstgroup}\relax +\let\@IEEEextractedfirstfirstgroup\@IEEEextractedgroup +% next group +\expandafter\@IEEEextractgroup\expandafter*\expandafter{\@IEEEextractedafterfirstgroupremain}\relax +\let\@IEEEextractednextgroup\@IEEEextractedgroup +\expandafter\@IEEEextracttoken\expandafter*\expandafter{\@IEEEextractednextgroup}\relax +\let\@IEEEextractednextfirsttoken\@IEEEextractedtoken +\let\@IEEEextractednextfirsttokenmacro\@IEEEextractedtokenmacro +\let\@IEEEextractednextfirsttokensdiscarded\@IEEEextractedtokensdiscarded +% next first group +\expandafter\@IEEEextractgroup\expandafter*\expandafter{\@IEEEextractednextgroup}\relax +\let\@IEEEextractednextfirstgroup\@IEEEextractedgroup} + + +%% -- End of Command Argument Scanning Support Functions -- + + + + +%% +%% START OF IEEEeqnarray DEFINITIONS +%% +%% Inspired by the concepts, examples, and previous works of LaTeX +%% coders and developers such as Donald Arseneau, Fred Bartlett, +%% David Carlisle, Tony Liu, Frank Mittelbach, Piet van Oostrum, +%% Roland Winkler and Mark Wooding. +%% I don't make the claim that my work here is even near their calibre. ;) + + +\newif\if@IEEEeqnarrayboxnojot% flag to indicate if the environment was called as the star form +\@IEEEeqnarrayboxnojotfalse + +\newif\if@advanceIEEEeqncolcnt% tracks if the environment should advance the col counter +% allows a way to make an \IEEEeqnarraybox that can be used within an \IEEEeqnarray +% used by IEEEeqnarraymulticol so that it can work properly in both +\@advanceIEEEeqncolcnttrue + +\newcount\@IEEEeqnnumcols % tracks how many IEEEeqnarray cols are defined +\newcount\@IEEEeqncolcnt % tracks how many IEEEeqnarray cols the user actually used + + +% The default math style used by the columns +\def\IEEEeqnarraymathstyle{\displaystyle} +% The default text style used by the columns +% default to using the current font +\def\IEEEeqnarraytextstyle{\relax} + +% like the iedlistdecl but for \IEEEeqnarray +\def\IEEEeqnarraydecl{\relax} +\def\IEEEeqnarrayboxdecl{\relax} + + + +% V1.8 flags to indicate that equation numbering is to persist +\newif\if@IEEEeqnumpersist% +\@IEEEeqnumpersistfalse +\newif\if@IEEEsubeqnumpersist% +\@IEEEsubeqnumpersistfalse +% +% V1.8 flags to indicate if (sub)equation number of last line was preadvanced +\newif\if@IEEEeqnumpreadv% +\@IEEEeqnumpreadvfalse +\newif\if@IEEEsubeqnumpreadv% +\@IEEEsubeqnumpreadvfalse + +\newcount\@IEEEsubeqnnumrollback% saves previous value of IEEEsubequation number in case we need to restore it + +% \yesnumber is the opposite of \nonumber +% a novel concept with the same def as the equationarray package +% However, we give IEEE versions too since some LaTeX packages such as +% the MDWtools mathenv.sty redefine \nonumber to something else. +% This command is intended for use in non-IEEEeqnarray math environments +\providecommand{\yesnumber}{\global\@eqnswtrue} + + +% IEEEyes/nonumber +% V1.8 add persistant * forms +% These commands can alter the type of equation an IEEEeqnarray line is. +\def\IEEEyesnumber{\@ifstar{\global\@IEEEeqnumpersisttrue\global\@IEEEsubeqnumpersistfalse\@IEEEyesnumber}{\@IEEEyesnumber}} + +\def\@IEEEyesnumber{\global\@eqnswtrue +\if@IEEEeqnarrayISinner% alter counters and label only inside an IEEEeqnarray +\ifnum\c@IEEEsubequation>0\relax + \stepcounter{equation}\setcounter{IEEEsubequation}{0}\gdef\@currentlabel{\p@equation\theequation}\relax + \gdef\@currentHref{\@IEEEtheHrefequation}% setup hyperref label +\fi +% even if we reached this eqn num via a preadv, it is legit now +\global\@IEEEeqnumpreadvfalse\global\@IEEEsubeqnumpreadvfalse +\fi} + +\def\IEEEnonumber{\@ifstar{\global\@IEEEeqnumpersistfalse\global\@IEEEsubeqnumpersistfalse\global\@eqnswfalse}{\global\@eqnswfalse}} + + +\def\IEEEyessubnumber{\@ifstar{\global\@IEEEsubeqnumpersisttrue\@IEEEyessubnumber}{\@IEEEyessubnumber}} +% +\def\@IEEEyessubnumber{\if@IEEEeqnarrayISinner% alter counters and label only inside an IEEEeqnarray + \ifnum\c@IEEEsubequation>0\relax% if it already is a subequation, we are good to go as-is + \else% if we are a regular equation we have to watch out for two cases + \if@IEEEeqnumpreadv% if this equation is the result of a preadvance, backout and bump the sub eqnnum + \global\advance\c@equation\m@ne\global\c@IEEEsubequation=\@IEEEsubeqnnumrollback\addtocounter{IEEEsubequation}{1}\relax + \else% non-preadvanced equations just need initialization of their sub eqnnum + \setcounter{IEEEsubequation}{1}\relax + \fi + \fi% fi already is subequation + \gdef\@currentlabel{\p@IEEEsubequation\theIEEEsubequation}\relax + \gdef\@currentHref{\@IEEEtheHrefsubequation}% setup hyperref label + \global\@IEEEeqnumpreadvfalse\global\@IEEEsubeqnumpreadvfalse% no longer a preadv anymore + \global\@eqnswtrue +\fi} + + +\def\IEEEnosubnumber{\@ifstar{\global\@IEEEsubeqnumpersistfalse\@IEEEnosubnumber}{\@IEEEnosubnumber}} +% +\def\@IEEEnosubnumber{\if@IEEEeqnarrayISinner% alter counters and label only inside an IEEEeqnarray + \if@eqnsw % we do nothing unless we know we will display because we play with the counters here + % if it currently is a subequation, bump up to the next equation number and turn off the subequation + \ifnum\c@IEEEsubequation>0\relax\addtocounter{equation}{1}\setcounter{IEEEsubequation}{0}\relax + \fi + \global\@IEEEeqnumpreadvfalse\global\@IEEEsubeqnumpreadvfalse% no longer a preadv anymore + \gdef\@currentlabel{\p@equation\theequation}\relax + \gdef\@currentHref{\@IEEEtheHrefequation}% setup hyperref label + \fi +\fi} + + + +% allows users to "push away" equations that get too close to the equation numbers +\def\IEEEeqnarraynumspace{\hphantom{\ifnum\c@IEEEsubequation>0\relax\theIEEEsubequationdis\else\theequationdis\fi}} + +% provides a way to span multiple columns within IEEEeqnarray environments +% will consider \if@advanceIEEEeqncolcnt before globally advancing the +% column counter - so as to work within \IEEEeqnarraybox +% usage: \IEEEeqnarraymulticol{number cols. to span}{col type}{cell text} +\long\def\IEEEeqnarraymulticol#1#2#3{\multispan{#1}\relax +% check if column is defined for the precolumn definition +% We have to be careful here because TeX scans for & even within an \iffalse +% where it does not expand macros. So, if we used only one \ifx and a #3 +% appeared in the false branch and the user inserted another alignment +% structure that uses & in the \IEEEeqnarraymulticol{}, TeX will not see that +% there is an inner alignment in the false branch yet still will see any & +% there and will think that they apply to the outer alignment resulting in an +% incomplete \ifx error. +% So, here we use separate checks for the pre and post parts in order to keep +% the #3 outside of all conditionals. +\relax\expandafter\ifx\csname @IEEEeqnarraycolDEF#2\endcsname\@IEEEeqnarraycolisdefined\relax +\csname @IEEEeqnarraycolPRE#2\endcsname +\else% if not, error and use default type +\@IEEEclspkgerror{Invalid column type "#2" in \string\IEEEeqnarraymulticol.\MessageBreak +Using a default centering column instead}% +{You must define IEEEeqnarray column types before use.}% +\csname @IEEEeqnarraycolPRE@IEEEdefault\endcsname +\fi +% The ten \relax are to help prevent misleading error messages in case a user +% accidently inserted a macro that tries to acquire additional arguments. +#3\relax\relax\relax\relax\relax\relax\relax\relax\relax\relax +% check if column is defined for the postcolumn definition +\expandafter\ifx\csname @IEEEeqnarraycolDEF#2\endcsname\@IEEEeqnarraycolisdefined\relax +\csname @IEEEeqnarraycolPOST#2\endcsname +\else% if not, use the default type +\csname @IEEEeqnarraycolPOST@IEEEdefault\endcsname +\fi +% advance column counter only if the IEEEeqnarray environment wants it +\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by #1\relax\fi} + +% like \omit, but maintains track of the column counter for \IEEEeqnarray +\def\IEEEeqnarrayomit{\omit\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by 1\relax\fi} + + +% provides a way to define a letter referenced column type +% usage: \IEEEeqnarraydefcol{col. type letter/name}{pre insertion text}{post insertion text} +\def\IEEEeqnarraydefcol#1#2#3{\expandafter\def\csname @IEEEeqnarraycolPRE#1\endcsname{#2}% +\expandafter\def\csname @IEEEeqnarraycolPOST#1\endcsname{#3}% +\expandafter\def\csname @IEEEeqnarraycolDEF#1\endcsname{1}} + + +% provides a way to define a numerically referenced inter-column glue types +% usage: \IEEEeqnarraydefcolsep{col. glue number}{glue definition} +\def\IEEEeqnarraydefcolsep#1#2{\expandafter\def\csname @IEEEeqnarraycolSEP\romannumeral #1\endcsname{#2}% +\expandafter\def\csname @IEEEeqnarraycolSEPDEF\romannumeral #1\endcsname{1}} + + +\def\@IEEEeqnarraycolisdefined{1}% just a macro for 1, used for checking undefined column types + + +% expands and appends the given argument to the \@IEEEtrantmptoksA token list +% used to build up the \halign preamble +\def\@IEEEappendtoksA#1{\edef\@@IEEEappendtoksA{\@IEEEtrantmptoksA={\the\@IEEEtrantmptoksA #1}}% +\@@IEEEappendtoksA} + +% also appends to \@IEEEtrantmptoksA, but does not expand the argument +% uses \toks8 as a scratchpad register +\def\@IEEEappendNOEXPANDtoksA#1{\toks8={#1}% +\edef\@@IEEEappendNOEXPANDtoksA{\@IEEEtrantmptoksA={\the\@IEEEtrantmptoksA\the\toks8}}% +\@@IEEEappendNOEXPANDtoksA} + +% define some common column types for the user +% math +\IEEEeqnarraydefcol{l}{$\IEEEeqnarraymathstyle}{$\hfil} +\IEEEeqnarraydefcol{c}{\hfil$\IEEEeqnarraymathstyle}{$\hfil} +\IEEEeqnarraydefcol{r}{\hfil$\IEEEeqnarraymathstyle}{$} +\IEEEeqnarraydefcol{L}{$\IEEEeqnarraymathstyle{}}{{}$\hfil} +\IEEEeqnarraydefcol{C}{\hfil$\IEEEeqnarraymathstyle{}}{{}$\hfil} +\IEEEeqnarraydefcol{R}{\hfil$\IEEEeqnarraymathstyle{}}{{}$} +% text +\IEEEeqnarraydefcol{s}{\IEEEeqnarraytextstyle}{\hfil} +\IEEEeqnarraydefcol{t}{\hfil\IEEEeqnarraytextstyle}{\hfil} +\IEEEeqnarraydefcol{u}{\hfil\IEEEeqnarraytextstyle}{} + +% vertical rules +\IEEEeqnarraydefcol{v}{}{\vrule width\arrayrulewidth} +\IEEEeqnarraydefcol{vv}{\vrule width\arrayrulewidth\hfil}{\hfil\vrule width\arrayrulewidth} +\IEEEeqnarraydefcol{V}{}{\vrule width\arrayrulewidth\hskip\doublerulesep\vrule width\arrayrulewidth} +\IEEEeqnarraydefcol{VV}{\vrule width\arrayrulewidth\hskip\doublerulesep\vrule width\arrayrulewidth\hfil}% +{\hfil\vrule width\arrayrulewidth\hskip\doublerulesep\vrule width\arrayrulewidth} + +% horizontal rules +\IEEEeqnarraydefcol{h}{}{\leaders\hrule height\arrayrulewidth\hfil} +\IEEEeqnarraydefcol{H}{}{\leaders\vbox{\hrule width\arrayrulewidth\vskip\doublerulesep\hrule width\arrayrulewidth}\hfil} + +% plain +\IEEEeqnarraydefcol{x}{}{} +\IEEEeqnarraydefcol{X}{$}{$} + +% the default column type to use in the event a column type is not defined +\IEEEeqnarraydefcol{@IEEEdefault}{\hfil$\IEEEeqnarraymathstyle}{$\hfil} + + +% a zero tabskip (used for "-" col types) +\def\@IEEEeqnarraycolSEPzero{0pt plus 0pt minus 0pt} +% a centering tabskip (used for "+" col types) +\def\@IEEEeqnarraycolSEPcenter{1000pt plus 0pt minus 1000pt} + +% top level default tabskip glues for the start, end, and inter-column +% may be reset within environments not always at the top level, e.g., \IEEEeqnarraybox +\edef\@IEEEeqnarraycolSEPdefaultstart{\@IEEEeqnarraycolSEPcenter}% default start glue +\edef\@IEEEeqnarraycolSEPdefaultend{\@IEEEeqnarraycolSEPcenter}% default end glue +\edef\@IEEEeqnarraycolSEPdefaultmid{\@IEEEeqnarraycolSEPzero}% default inter-column glue + + + +% creates a vertical rule that extends from the bottom to the top a a cell +% Provided in case other packages redefine \vline some other way. +% usage: \IEEEeqnarrayvrule[rule thickness] +% If no argument is provided, \arrayrulewidth will be used for the rule thickness. +\newcommand\IEEEeqnarrayvrule[1][\arrayrulewidth]{\vrule\@width#1\relax} + +% creates a blank separator row +% usage: \IEEEeqnarrayseprow[separation length][font size commands] +% default is \IEEEeqnarrayseprow[0.25\normalbaselineskip][\relax] +% blank arguments inherit the default values +% uses \skip5 as a scratch register - calls \@IEEEeqnarraystrutsize which uses more scratch registers +\def\IEEEeqnarrayseprow{\relax\@ifnextchar[{\@IEEEeqnarrayseprow}{\@IEEEeqnarrayseprow[0.25\normalbaselineskip]}} +\def\@IEEEeqnarrayseprow[#1]{\relax\@ifnextchar[{\@@IEEEeqnarrayseprow[#1]}{\@@IEEEeqnarrayseprow[#1][\relax]}} +\def\@@IEEEeqnarrayseprow[#1][#2]{\def\@IEEEeqnarrayseprowARGONE{#1}% +\ifx\@IEEEeqnarrayseprowARGONE\@empty% +% get the skip value, based on the font commands +% use skip5 because \IEEEeqnarraystrutsize uses \skip0, \skip2, \skip3 +% assign within a bogus box to confine the font changes +{\setbox0=\hbox{#2\relax\global\skip5=0.25\normalbaselineskip}}% +\else% +{\setbox0=\hbox{#2\relax\global\skip5=#1}}% +\fi% +\@IEEEeqnarrayhoptolastcolumn\IEEEeqnarraystrutsize{\skip5}{0pt}[\relax]\relax} + +% creates a blank separator row, but omits all the column templates +% usage: \IEEEeqnarrayseprowcut[separation length][font size commands] +% default is \IEEEeqnarrayseprowcut[0.25\normalbaselineskip][\relax] +% blank arguments inherit the default values +% uses \skip5 as a scratch register - calls \@IEEEeqnarraystrutsize which uses more scratch registers +\def\IEEEeqnarrayseprowcut{\multispan{\@IEEEeqnnumcols}\relax% span all the cols +% advance column counter only if the IEEEeqnarray environment wants it +\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by \@IEEEeqnnumcols\relax\fi% +\@ifnextchar[{\@IEEEeqnarrayseprowcut}{\@IEEEeqnarrayseprowcut[0.25\normalbaselineskip]}} +\def\@IEEEeqnarrayseprowcut[#1]{\relax\@ifnextchar[{\@@IEEEeqnarrayseprowcut[#1]}{\@@IEEEeqnarrayseprowcut[#1][\relax]}} +\def\@@IEEEeqnarrayseprowcut[#1][#2]{\def\@IEEEeqnarrayseprowARGONE{#1}% +\ifx\@IEEEeqnarrayseprowARGONE\@empty% +% get the skip value, based on the font commands +% use skip5 because \IEEEeqnarraystrutsize uses \skip0, \skip2, \skip3 +% assign within a bogus box to confine the font changes +{\setbox0=\hbox{#2\relax\global\skip5=0.25\normalbaselineskip}}% +\else% +{\setbox0=\hbox{#2\relax\global\skip5=#1}}% +\fi% +\IEEEeqnarraystrutsize{\skip5}{0pt}[\relax]\relax} + + + +% draws a single rule across all the columns optional +% argument determines the rule width, \arrayrulewidth is the default +% updates column counter as needed and turns off struts +% usage: \IEEEeqnarrayrulerow[rule line thickness] +\def\IEEEeqnarrayrulerow{\multispan{\@IEEEeqnnumcols}\relax% span all the cols +% advance column counter only if the IEEEeqnarray environment wants it +\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by \@IEEEeqnnumcols\relax\fi% +\@ifnextchar[{\@IEEEeqnarrayrulerow}{\@IEEEeqnarrayrulerow[\arrayrulewidth]}} +\def\@IEEEeqnarrayrulerow[#1]{\leaders\hrule height#1\hfil\relax% put in our rule +% turn off any struts +\IEEEeqnarraystrutsize{0pt}{0pt}[\relax]\relax} + + +% draws a double rule by using a single rule row, a separator row, and then +% another single rule row +% first optional argument determines the rule thicknesses, \arrayrulewidth is the default +% second optional argument determines the rule spacing, \doublerulesep is the default +% usage: \IEEEeqnarraydblrulerow[rule line thickness][rule spacing] +\def\IEEEeqnarraydblrulerow{\multispan{\@IEEEeqnnumcols}\relax% span all the cols +% advance column counter only if the IEEEeqnarray environment wants it +\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by \@IEEEeqnnumcols\relax\fi% +\@ifnextchar[{\@IEEEeqnarraydblrulerow}{\@IEEEeqnarraydblrulerow[\arrayrulewidth]}} +\def\@IEEEeqnarraydblrulerow[#1]{\relax\@ifnextchar[{\@@IEEEeqnarraydblrulerow[#1]}% +{\@@IEEEeqnarraydblrulerow[#1][\doublerulesep]}} +\def\@@IEEEeqnarraydblrulerow[#1][#2]{\def\@IEEEeqnarraydblrulerowARG{#1}% +% we allow the user to say \IEEEeqnarraydblrulerow[][] +\ifx\@IEEEeqnarraydblrulerowARG\@empty% +\@IEEEeqnarrayrulerow[\arrayrulewidth]% +\else% +\@IEEEeqnarrayrulerow[#1]\relax% +\fi% +\def\@IEEEeqnarraydblrulerowARG{#2}% +\ifx\@IEEEeqnarraydblrulerowARG\@empty% +\\\IEEEeqnarrayseprow[\doublerulesep][\relax]% +\else% +\\\IEEEeqnarrayseprow[#2][\relax]% +\fi% +\\\multispan{\@IEEEeqnnumcols}% +% advance column counter only if the IEEEeqnarray environment wants it +\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by \@IEEEeqnnumcols\relax\fi% +\def\@IEEEeqnarraydblrulerowARG{#1}% +\ifx\@IEEEeqnarraydblrulerowARG\@empty% +\@IEEEeqnarrayrulerow[\arrayrulewidth]% +\else% +\@IEEEeqnarrayrulerow[#1]% +\fi% +} + +% draws a double rule by using a single rule row, a separator (cutting) row, and then +% another single rule row +% first optional argument determines the rule thicknesses, \arrayrulewidth is the default +% second optional argument determines the rule spacing, \doublerulesep is the default +% usage: \IEEEeqnarraydblrulerow[rule line thickness][rule spacing] +\def\IEEEeqnarraydblrulerowcut{\multispan{\@IEEEeqnnumcols}\relax% span all the cols +% advance column counter only if the IEEEeqnarray environment wants it +\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by \@IEEEeqnnumcols\relax\fi% +\@ifnextchar[{\@IEEEeqnarraydblrulerowcut}{\@IEEEeqnarraydblrulerowcut[\arrayrulewidth]}} +\def\@IEEEeqnarraydblrulerowcut[#1]{\relax\@ifnextchar[{\@@IEEEeqnarraydblrulerowcut[#1]}% +{\@@IEEEeqnarraydblrulerowcut[#1][\doublerulesep]}} +\def\@@IEEEeqnarraydblrulerowcut[#1][#2]{\def\@IEEEeqnarraydblrulerowARG{#1}% +% we allow the user to say \IEEEeqnarraydblrulerow[][] +\ifx\@IEEEeqnarraydblrulerowARG\@empty% +\@IEEEeqnarrayrulerow[\arrayrulewidth]% +\else% +\@IEEEeqnarrayrulerow[#1]% +\fi% +\def\@IEEEeqnarraydblrulerowARG{#2}% +\ifx\@IEEEeqnarraydblrulerowARG\@empty% +\\\IEEEeqnarrayseprowcut[\doublerulesep][\relax]% +\else% +\\\IEEEeqnarrayseprowcut[#2][\relax]% +\fi% +\\\multispan{\@IEEEeqnnumcols}% +% advance column counter only if the IEEEeqnarray environment wants it +\if@advanceIEEEeqncolcnt\global\advance\@IEEEeqncolcnt by \@IEEEeqnnumcols\relax\fi% +\def\@IEEEeqnarraydblrulerowARG{#1}% +\ifx\@IEEEeqnarraydblrulerowARG\@empty% +\@IEEEeqnarrayrulerow[\arrayrulewidth]% +\else% +\@IEEEeqnarrayrulerow[#1]% +\fi% +} + + + +% inserts a full row's worth of &'s +% relies on \@IEEEeqnnumcols to provide the correct number of columns +% uses \@IEEEtrantmptoksA, \count0 as scratch registers +\def\@IEEEeqnarrayhoptolastcolumn{\@IEEEtrantmptoksA={}\count0=1\relax% +\loop% add cols if the user did not use them all +\ifnum\count0<\@IEEEeqnnumcols\relax% +\@IEEEappendtoksA{&}% +\advance\count0 by 1\relax% update the col count +\repeat% +\the\@IEEEtrantmptoksA%execute the &'s +} + + + +\newif\if@IEEEeqnarrayISinner % flag to indicate if we are within the lines +\@IEEEeqnarrayISinnerfalse % of an IEEEeqnarray - after the IEEEeqnarraydecl + +\edef\@IEEEeqnarrayTHEstrutheight{0pt} % height and depth of IEEEeqnarray struts +\edef\@IEEEeqnarrayTHEstrutdepth{0pt} + +\edef\@IEEEeqnarrayTHEmasterstrutheight{0pt} % default height and depth of +\edef\@IEEEeqnarrayTHEmasterstrutdepth{0pt} % struts within an IEEEeqnarray + +\edef\@IEEEeqnarrayTHEmasterstrutHSAVE{0pt} % saved master strut height +\edef\@IEEEeqnarrayTHEmasterstrutDSAVE{0pt} % and depth + +\newif\if@IEEEeqnarrayusemasterstrut % flag to indicate that the master strut value +\@IEEEeqnarrayusemasterstruttrue % is to be used + + + +% saves the strut height and depth of the master strut +\def\@IEEEeqnarraymasterstrutsave{\relax% +\expandafter\skip0=\@IEEEeqnarrayTHEmasterstrutheight\relax% +\expandafter\skip2=\@IEEEeqnarrayTHEmasterstrutdepth\relax% +% remove stretchability +\dimen0\skip0\relax% +\dimen2\skip2\relax% +% save values +\edef\@IEEEeqnarrayTHEmasterstrutHSAVE{\the\dimen0}% +\edef\@IEEEeqnarrayTHEmasterstrutDSAVE{\the\dimen2}} + +% restores the strut height and depth of the master strut +\def\@IEEEeqnarraymasterstrutrestore{\relax% +\expandafter\skip0=\@IEEEeqnarrayTHEmasterstrutHSAVE\relax% +\expandafter\skip2=\@IEEEeqnarrayTHEmasterstrutDSAVE\relax% +% remove stretchability +\dimen0\skip0\relax% +\dimen2\skip2\relax% +% restore values +\edef\@IEEEeqnarrayTHEmasterstrutheight{\the\dimen0}% +\edef\@IEEEeqnarrayTHEmasterstrutdepth{\the\dimen2}} + + +% globally restores the strut height and depth to the +% master values and sets the master strut flag to true +\def\@IEEEeqnarraystrutreset{\relax% +\expandafter\skip0=\@IEEEeqnarrayTHEmasterstrutheight\relax% +\expandafter\skip2=\@IEEEeqnarrayTHEmasterstrutdepth\relax% +% remove stretchability +\dimen0\skip0\relax% +\dimen2\skip2\relax% +% restore values +\xdef\@IEEEeqnarrayTHEstrutheight{\the\dimen0}% +\xdef\@IEEEeqnarrayTHEstrutdepth{\the\dimen2}% +\global\@IEEEeqnarrayusemasterstruttrue} + + +% if the master strut is not to be used, make the current +% values of \@IEEEeqnarrayTHEstrutheight, \@IEEEeqnarrayTHEstrutdepth +% and the use master strut flag, global +% this allows user strut commands issued in the last column to be carried +% into the isolation/strut column +\def\@IEEEeqnarrayglobalizestrutstatus{\relax% +\if@IEEEeqnarrayusemasterstrut\else% +\xdef\@IEEEeqnarrayTHEstrutheight{\@IEEEeqnarrayTHEstrutheight}% +\xdef\@IEEEeqnarrayTHEstrutdepth{\@IEEEeqnarrayTHEstrutdepth}% +\global\@IEEEeqnarrayusemasterstrutfalse% +\fi} + + + +% usage: \IEEEeqnarraystrutsize{height}{depth}[font size commands] +% If called outside the lines of an IEEEeqnarray, sets the height +% and depth of both the master and local struts. If called inside +% an IEEEeqnarray line, sets the height and depth of the local strut +% only and sets the flag to indicate the use of the local strut +% values. If the height or depth is left blank, 0.7\normalbaselineskip +% and 0.3\normalbaselineskip will be used, respectively. +% The optional argument can be used to evaluate the lengths under +% a different font size and styles. If none is specified, the current +% font is used. +% uses scratch registers \skip0, \skip2, \skip3, \dimen0, \dimen2 +\def\IEEEeqnarraystrutsize#1#2{\relax\@ifnextchar[{\@IEEEeqnarraystrutsize{#1}{#2}}{\@IEEEeqnarraystrutsize{#1}{#2}[\relax]}} +\def\@IEEEeqnarraystrutsize#1#2[#3]{\def\@IEEEeqnarraystrutsizeARG{#1}% +\ifx\@IEEEeqnarraystrutsizeARG\@empty% +{\setbox0=\hbox{#3\relax\global\skip3=0.7\normalbaselineskip}}% +\skip0=\skip3\relax% +\else% arg one present +{\setbox0=\hbox{#3\relax\global\skip3=#1\relax}}% +\skip0=\skip3\relax% +\fi% if null arg +\def\@IEEEeqnarraystrutsizeARG{#2}% +\ifx\@IEEEeqnarraystrutsizeARG\@empty% +{\setbox0=\hbox{#3\relax\global\skip3=0.3\normalbaselineskip}}% +\skip2=\skip3\relax% +\else% arg two present +{\setbox0=\hbox{#3\relax\global\skip3=#2\relax}}% +\skip2=\skip3\relax% +\fi% if null arg +% remove stretchability, just to be safe +\dimen0\skip0\relax% +\dimen2\skip2\relax% +% dimen0 = height, dimen2 = depth +\if@IEEEeqnarrayISinner% inner does not touch master strut size +\edef\@IEEEeqnarrayTHEstrutheight{\the\dimen0}% +\edef\@IEEEeqnarrayTHEstrutdepth{\the\dimen2}% +\@IEEEeqnarrayusemasterstrutfalse% do not use master +\else% outer, have to set master strut too +\edef\@IEEEeqnarrayTHEmasterstrutheight{\the\dimen0}% +\edef\@IEEEeqnarrayTHEmasterstrutdepth{\the\dimen2}% +\edef\@IEEEeqnarrayTHEstrutheight{\the\dimen0}% +\edef\@IEEEeqnarrayTHEstrutdepth{\the\dimen2}% +\@IEEEeqnarrayusemasterstruttrue% use master strut +\fi} + + +% usage: \IEEEeqnarraystrutsizeadd{added height}{added depth}[font size commands] +% If called outside the lines of an IEEEeqnarray, adds the given height +% and depth to both the master and local struts. +% If called inside an IEEEeqnarray line, adds the given height and depth +% to the local strut only and sets the flag to indicate the use +% of the local strut values. +% In both cases, if a height or depth is left blank, 0pt is used instead. +% The optional argument can be used to evaluate the lengths under +% a different font size and styles. If none is specified, the current +% font is used. +% uses scratch registers \skip0, \skip2, \skip3, \dimen0, \dimen2 +\def\IEEEeqnarraystrutsizeadd#1#2{\relax\@ifnextchar[{\@IEEEeqnarraystrutsizeadd{#1}{#2}}{\@IEEEeqnarraystrutsizeadd{#1}{#2}[\relax]}} +\def\@IEEEeqnarraystrutsizeadd#1#2[#3]{\def\@IEEEeqnarraystrutsizearg{#1}% +\ifx\@IEEEeqnarraystrutsizearg\@empty% +\skip0=0pt\relax% +\else% arg one present +{\setbox0=\hbox{#3\relax\global\skip3=#1}}% +\skip0=\skip3\relax% +\fi% if null arg +\def\@IEEEeqnarraystrutsizearg{#2}% +\ifx\@IEEEeqnarraystrutsizearg\@empty% +\skip2=0pt\relax% +\else% arg two present +{\setbox0=\hbox{#3\relax\global\skip3=#2}}% +\skip2=\skip3\relax% +\fi% if null arg +% remove stretchability, just to be safe +\dimen0\skip0\relax% +\dimen2\skip2\relax% +% dimen0 = height, dimen2 = depth +\if@IEEEeqnarrayISinner% inner does not touch master strut size +% get local strut size +\expandafter\skip0=\@IEEEeqnarrayTHEstrutheight\relax% +\expandafter\skip2=\@IEEEeqnarrayTHEstrutdepth\relax% +% add it to the user supplied values +\advance\dimen0 by \skip0\relax% +\advance\dimen2 by \skip2\relax% +% update the local strut size +\edef\@IEEEeqnarrayTHEstrutheight{\the\dimen0}% +\edef\@IEEEeqnarrayTHEstrutdepth{\the\dimen2}% +\@IEEEeqnarrayusemasterstrutfalse% do not use master +\else% outer, have to set master strut too +% get master strut size +\expandafter\skip0=\@IEEEeqnarrayTHEmasterstrutheight\relax% +\expandafter\skip2=\@IEEEeqnarrayTHEmasterstrutdepth\relax% +% add it to the user supplied values +\advance\dimen0 by \skip0\relax% +\advance\dimen2 by \skip2\relax% +% update the local and master strut sizes +\edef\@IEEEeqnarrayTHEmasterstrutheight{\the\dimen0}% +\edef\@IEEEeqnarrayTHEmasterstrutdepth{\the\dimen2}% +\edef\@IEEEeqnarrayTHEstrutheight{\the\dimen0}% +\edef\@IEEEeqnarrayTHEstrutdepth{\the\dimen2}% +\@IEEEeqnarrayusemasterstruttrue% use master strut +\fi} + + +% allow user a way to see the struts +\newif\ifIEEEvisiblestruts +\IEEEvisiblestrutsfalse + +% inserts an invisible strut using the master or local strut values +% uses scratch registers \skip0, \skip2, \dimen0, \dimen2 +\def\@IEEEeqnarrayinsertstrut{\relax% +\if@IEEEeqnarrayusemasterstrut +% get master strut size +\expandafter\skip0=\@IEEEeqnarrayTHEmasterstrutheight\relax% +\expandafter\skip2=\@IEEEeqnarrayTHEmasterstrutdepth\relax% +\else% +% get local strut size +\expandafter\skip0=\@IEEEeqnarrayTHEstrutheight\relax% +\expandafter\skip2=\@IEEEeqnarrayTHEstrutdepth\relax% +\fi% +% remove stretchability, probably not needed +\dimen0\skip0\relax% +\dimen2\skip2\relax% +% dimen0 = height, dimen2 = depth +% allow user to see struts if desired +\ifIEEEvisiblestruts% +\vrule width0.2pt height\dimen0 depth\dimen2\relax% +\else% +\vrule width0pt height\dimen0 depth\dimen2\relax\fi} + + +% creates an invisible strut, useable even outside \IEEEeqnarray +% if \IEEEvisiblestrutstrue, the strut will be visible and 0.2pt wide. +% usage: \IEEEstrut[height][depth][font size commands] +% default is \IEEEstrut[0.7\normalbaselineskip][0.3\normalbaselineskip][\relax] +% blank arguments inherit the default values +% uses \dimen0, \dimen2, \skip0, \skip2 +\def\IEEEstrut{\relax\@ifnextchar[{\@IEEEstrut}{\@IEEEstrut[0.7\normalbaselineskip]}} +\def\@IEEEstrut[#1]{\relax\@ifnextchar[{\@@IEEEstrut[#1]}{\@@IEEEstrut[#1][0.3\normalbaselineskip]}} +\def\@@IEEEstrut[#1][#2]{\relax\@ifnextchar[{\@@@IEEEstrut[#1][#2]}{\@@@IEEEstrut[#1][#2][\relax]}} +\def\@@@IEEEstrut[#1][#2][#3]{\mbox{#3\relax% +\def\@IEEEstrutARG{#1}% +\ifx\@IEEEstrutARG\@empty% +\skip0=0.7\normalbaselineskip\relax% +\else% +\skip0=#1\relax% +\fi% +\def\@IEEEstrutARG{#2}% +\ifx\@IEEEstrutARG\@empty% +\skip2=0.3\normalbaselineskip\relax% +\else% +\skip2=#2\relax% +\fi% +% remove stretchability, probably not needed +\dimen0\skip0\relax% +\dimen2\skip2\relax% +\ifIEEEvisiblestruts% +\vrule width0.2pt height\dimen0 depth\dimen2\relax% +\else% +\vrule width0.0pt height\dimen0 depth\dimen2\relax\fi}} + + +% enables strut mode by setting a default strut size and then zeroing the +% \baselineskip, \lineskip, \lineskiplimit and \jot +\def\IEEEeqnarraystrutmode{\IEEEeqnarraystrutsize{0.7\normalbaselineskip}{0.3\normalbaselineskip}[\relax]% +\baselineskip=0pt\lineskip=0pt\lineskiplimit=0pt\jot=0pt} + + +% equation and subequation forms to use to setup hyperref's \@currentHref +\def\@IEEEtheHrefequation{equation.\theHequation} +\def\@IEEEtheHrefsubequation{equation.\theHequation\alph{IEEEsubequation}} + + +\def\IEEEeqnarray{\@IEEEeqnumpersisttrue\@IEEEsubeqnumpersistfalse\@IEEEeqnarray} +\def\endIEEEeqnarray{\end@IEEEeqnarray} + +\@namedef{IEEEeqnarray*}{\@IEEEeqnumpersistfalse\@IEEEsubeqnumpersistfalse\@IEEEeqnarray} +\@namedef{endIEEEeqnarray*}{\end@IEEEeqnarray} + + +% \IEEEeqnarray is an enhanced \eqnarray. +% The star form defaults to not putting equation numbers at the end of each row. +% usage: \IEEEeqnarray[decl]{cols} +\def\@IEEEeqnarray{\relax\@ifnextchar[{\@@IEEEeqnarray}{\@@IEEEeqnarray[\relax]}} +% We have to be careful here to normalize catcodes just before acquiring the +% cols as that specification may contain punctuation which could be subject +% to document catcode changes. +\def\@@IEEEeqnarray[#1]{\begingroup\IEEEnormalcatcodes\@@@IEEEeqnarray[#1]} +\def\@@@IEEEeqnarray[#1]#2{\endgroup + % default to showing the equation number or not based on whether or not + % the star form was involked + \if@IEEEeqnumpersist\global\@eqnswtrue + \else% not the star form + \global\@eqnswfalse + \fi% if star form + % provide a basic hyperref \theHequation if this has not already been setup (hyperref not loaded, or no section counter) + \@ifundefined{theHequation}{\def\theHequation{\arabic{equation}}}{}\relax + % provide dummy hyperref commands in case hyperref is not loaded + \providecommand{\Hy@raisedlink}[1]{}\relax + \providecommand{\hyper@anchorstart}[1]{}\relax + \providecommand{\hyper@anchorend}{}\relax + \providecommand{\@currentHref}{}\relax + \@IEEEeqnumpreadvfalse% reset eqnpreadv flag + \@IEEEsubeqnumpreadvfalse% reset subeqnpreadv flag + \@IEEEeqnarrayISinnerfalse% not yet within the lines of the halign + \@IEEEeqnarraystrutsize{0pt}{0pt}[\relax]% turn off struts by default + \@IEEEeqnarrayusemasterstruttrue% use master strut till user asks otherwise + \IEEEvisiblestrutsfalse% diagnostic mode defaults to off + % no extra space unless the user specifically requests it + \lineskip=0pt\relax + \lineskiplimit=0pt\relax + \baselineskip=\normalbaselineskip\relax% + \jot=\IEEEnormaljot\relax% + \mathsurround\z@\relax% no extra spacing around math + \@advanceIEEEeqncolcnttrue% advance the col counter for each col the user uses, + % used in \IEEEeqnarraymulticol and in the preamble build + %V1.8 Here we preadvance to the next equation number. + % If the user later wants a continued subequation, we can roll back. + \global\@IEEEsubeqnnumrollback=\c@IEEEsubequation% + \stepcounter{equation}\@IEEEeqnumpreadvtrue% advance equation counter before first line + \setcounter{IEEEsubequation}{0}% no subequation yet + \let\@IEEEcurrentlabelsave\@currentlabel% save current label as we later change it globally + \let\@IEEEcurrentHrefsave\@currentHref% save current href label as we later change it globally + \def\@currentlabel{\p@equation\theequation}% redefine the ref label + \def\@currentHref{\@IEEEtheHrefequation}% setup hyperref label + \IEEEeqnarraydecl\relax% allow a way for the user to make global overrides + #1\relax% allow user to override defaults + \let\\\@IEEEeqnarraycr% replace newline with one that can put in eqn. numbers + \global\@IEEEeqncolcnt\z@% col. count = 0 for first line + \@IEEEbuildpreamble{#2}\relax% build the preamble and put it into \@IEEEtrantmptoksA + % put in the column for the equation number + \ifnum\@IEEEeqnnumcols>0\relax\@IEEEappendtoksA{&}\fi% col separator for those after the first + \toks0={##}% + % advance the \@IEEEeqncolcnt for the isolation col, this helps with error checking + \@IEEEappendtoksA{\global\advance\@IEEEeqncolcnt by 1\relax}% + % add the isolation column + \@IEEEappendtoksA{\tabskip\z@skip\bgroup\the\toks0\egroup}% + % advance the \@IEEEeqncolcnt for the equation number col, this helps with error checking + \@IEEEappendtoksA{&\global\advance\@IEEEeqncolcnt by 1\relax}% + % add the equation number col to the preamble + \@IEEEappendtoksA{\tabskip\z@skip\hb@xt@\z@\bgroup\hss\the\toks0\egroup}% + % note \@IEEEeqnnumcols does not count the equation col or isolation col + % set the starting tabskip glue as determined by the preamble build + \tabskip=\@IEEEBPstartglue\relax + % begin the display alignment + \@IEEEeqnarrayISinnertrue% commands are now within the lines + $$\everycr{}\halign to\displaywidth\bgroup + % "exspand" the preamble + \span\the\@IEEEtrantmptoksA\cr} + +% enter isolation/strut column (or the next column if the user did not use +% every column), record the strut status, complete the columns, do the strut if needed, +% restore counters (to backout any equation setup for a next line that was never used) +% to their correct values and exit +\def\end@IEEEeqnarray{\@IEEEeqnarrayglobalizestrutstatus&\@@IEEEeqnarraycr\egroup +\if@IEEEsubeqnumpreadv\global\advance\c@IEEEsubequation\m@ne\fi +\if@IEEEeqnumpreadv\global\advance\c@equation\m@ne\global\c@IEEEsubequation=\@IEEEsubeqnnumrollback\fi +\global\let\@currentlabel\@IEEEcurrentlabelsave% restore current label +\global\let\@currentHref\@IEEEcurrentHrefsave% restore current href label +$$\@ignoretrue} + + +% IEEEeqnarray uses a modifed \\ instead of the plain \cr to +% end rows. This allows for things like \\*[vskip amount] +% These "cr" macros are modified versions of those for LaTeX2e's eqnarray +% the {\ifnum0=`} braces must be kept away from the last column to avoid +% altering spacing of its math, so we use & to advance to the next column +% as there is an isolation/strut column after the user's columns +\def\@IEEEeqnarraycr{\@IEEEeqnarrayglobalizestrutstatus&% save strut status and advance to next column + {\ifnum0=`}\fi + \@ifstar{% + \global\@eqpen\@M\@IEEEeqnarrayYCR + }{% + \global\@eqpen\interdisplaylinepenalty \@IEEEeqnarrayYCR + }% +} + +\def\@IEEEeqnarrayYCR{\@testopt\@IEEEeqnarrayXCR\z@skip} + +\def\@IEEEeqnarrayXCR[#1]{% + \ifnum0=`{\fi}% + \@@IEEEeqnarraycr + \noalign{\penalty\@eqpen\vskip\jot\vskip #1\relax}}% + +\def\@@IEEEeqnarraycr{\@IEEEtrantmptoksA={}% clear token register + \advance\@IEEEeqncolcnt by -1\relax% adjust col count because of the isolation column + \ifnum\@IEEEeqncolcnt>\@IEEEeqnnumcols\relax + \@IEEEclspkgerror{Too many columns within the IEEEeqnarray\MessageBreak + environment}% + {Use fewer \string &'s or put more columns in the IEEEeqnarray column\MessageBreak + specifications.}\relax% + \else + \loop% add cols if the user did not use them all + \ifnum\@IEEEeqncolcnt<\@IEEEeqnnumcols\relax + \@IEEEappendtoksA{&}% + \advance\@IEEEeqncolcnt by 1\relax% update the col count + \repeat + % this number of &'s will take us the the isolation column + \fi + % execute the &'s + \the\@IEEEtrantmptoksA% + % handle the strut/isolation column + \@IEEEeqnarrayinsertstrut% do the strut if needed + \@IEEEeqnarraystrutreset% reset the strut system for next line or IEEEeqnarray + &% and enter the equation number column + \if@eqnsw% only if we display something + \Hy@raisedlink{\hyper@anchorstart{\@currentHref}}% start a hyperref anchor + \global\@IEEEeqnumpreadvfalse\relax% displaying an equation number means + \global\@IEEEsubeqnumpreadvfalse\relax% the equation counters point to valid equations + % V1.8 Here we setup the counters, currentlabel and status for what would be the *next* + % equation line as would be the case under the current settings. However, there are two problems. + % One problem is that there might not ever be a next line. The second problem is that the user + % may later alter the meaning of a line with commands such as \IEEEyessubnumber. So, to handle + % these cases we have to record the current values of the (sub)equation counters and revert back + % to them if the next line is changed or never comes. The \if@IEEEeqnumpreadv, \if@IEEEsubeqnumpreadv + % and \@IEEEsubeqnnumrollback stuff tracks this. + % The logic to handle all this is surprisingly complex, but a nice feature of the approach here is + % that the equation counters and labels remain valid for what the line would be unless a + % \IEEEyessubnumber et al. later changes it. So, any hyperref links are always correct. + \ifnum\c@IEEEsubequation>0\relax% handle subequation + \theIEEEsubequationdis\relax + \if@IEEEsubeqnumpersist% setup for default type of next line + \stepcounter{IEEEsubequation}\global\@IEEEsubeqnumpreadvtrue\relax + \gdef\@currentlabel{\p@IEEEsubequation\theIEEEsubequation}\relax + \gdef\@currentHref{\@IEEEtheHrefsubequation}% setup hyperref label + \else + % if no subeqnum persist, go ahead and setup for a new equation number + \global\@IEEEsubeqnnumrollback=\c@IEEEsubequation + \stepcounter{equation}\global\@IEEEeqnumpreadvtrue\relax + \setcounter{IEEEsubequation}{0}\gdef\@currentlabel{\p@equation\theequation}\relax + \gdef\@currentHref{\@IEEEtheHrefequation}% setup hyperref label + \fi + \else% display a standard equation number + \theequationdis\relax + \setcounter{IEEEsubequation}{0}\relax% not really needed + \if@IEEEsubeqnumpersist% setup for default type of next line + % subequations that follow plain equations carry the same equation number e.g, 5, 5a rather than 5, 6a + \stepcounter{IEEEsubequation}\global\@IEEEsubeqnumpreadvtrue\relax + \gdef\@currentlabel{\p@IEEEsubequation\theIEEEsubequation}\relax + \gdef\@currentHref{\@IEEEtheHrefsubequation}% setup hyperref label + \else + % if no subeqnum persist, go ahead and setup for a new equation number + \global\@IEEEsubeqnnumrollback=\c@IEEEsubequation + \stepcounter{equation}\global\@IEEEeqnumpreadvtrue\relax + \setcounter{IEEEsubequation}{0}\gdef\@currentlabel{\p@equation\theequation}\relax + \gdef\@currentHref{\@IEEEtheHrefequation}% setup hyperref label + \fi + \fi% + \Hy@raisedlink{\hyper@anchorend}% end hyperref anchor + \fi% fi only if we display something + % reset the flags to indicate the default preferences of the display of equation numbers + \if@IEEEeqnumpersist\global\@eqnswtrue\else\global\@eqnswfalse\fi + \if@IEEEsubeqnumpersist\global\@eqnswtrue\fi% ditto for the subequation flag + % reset the number of columns the user actually used + \global\@IEEEeqncolcnt\z@\relax + % the real end of the line + \cr} + + + + + +% \IEEEeqnarraybox is like \IEEEeqnarray except the box form puts everything +% inside a vtop, vbox, or vcenter box depending on the letter in the second +% optional argument (t,b,c). Vbox is the default. Unlike \IEEEeqnarray, +% equation numbers are not displayed and \IEEEeqnarraybox can be nested. +% \IEEEeqnarrayboxm is for math mode (like \array) and does not put the vbox +% within an hbox. +% \IEEEeqnarrayboxt is for text mode (like \tabular) and puts the vbox within +% a \hbox{$ $} construct. +% \IEEEeqnarraybox will auto detect whether to use \IEEEeqnarrayboxm or +% \IEEEeqnarrayboxt depending on the math mode. +% The third optional argument specifies the width this box is to be set to - +% natural width is the default. +% The * forms do not add \jot line spacing +% usage: \IEEEeqnarraybox[decl][pos][width]{cols} +\def\IEEEeqnarrayboxm{\@IEEEeqnarrayboxnojotfalse\@IEEEeqnarrayboxHBOXSWfalse\@IEEEeqnarraybox} +\def\endIEEEeqnarrayboxm{\end@IEEEeqnarraybox} +\@namedef{IEEEeqnarrayboxm*}{\@IEEEeqnarrayboxnojottrue\@IEEEeqnarrayboxHBOXSWfalse\@IEEEeqnarraybox} +\@namedef{endIEEEeqnarrayboxm*}{\end@IEEEeqnarraybox} + +\def\IEEEeqnarrayboxt{\@IEEEeqnarrayboxnojotfalse\@IEEEeqnarrayboxHBOXSWtrue\@IEEEeqnarraybox} +\def\endIEEEeqnarrayboxt{\end@IEEEeqnarraybox} +\@namedef{IEEEeqnarrayboxt*}{\@IEEEeqnarrayboxnojottrue\@IEEEeqnarrayboxHBOXSWtrue\@IEEEeqnarraybox} +\@namedef{endIEEEeqnarrayboxt*}{\end@IEEEeqnarraybox} + +\def\IEEEeqnarraybox{\@IEEEeqnarrayboxnojotfalse\ifmmode\@IEEEeqnarrayboxHBOXSWfalse\else\@IEEEeqnarrayboxHBOXSWtrue\fi% +\@IEEEeqnarraybox} +\def\endIEEEeqnarraybox{\end@IEEEeqnarraybox} + +\@namedef{IEEEeqnarraybox*}{\@IEEEeqnarrayboxnojottrue\ifmmode\@IEEEeqnarrayboxHBOXSWfalse\else\@IEEEeqnarrayboxHBOXSWtrue\fi% +\@IEEEeqnarraybox} +\@namedef{endIEEEeqnarraybox*}{\end@IEEEeqnarraybox} + +% flag to indicate if the \IEEEeqnarraybox needs to put things into an hbox{$ $} +% for \vcenter in non-math mode +\newif\if@IEEEeqnarrayboxHBOXSW% +\@IEEEeqnarrayboxHBOXSWfalse + +\def\@IEEEeqnarraybox{\relax\@ifnextchar[{\@@IEEEeqnarraybox}{\@@IEEEeqnarraybox[\relax]}} +% We have to be careful here to normalize catcodes just before acquiring the +% cols as that specification may contain punctuation which could be subject +% to document catcode changes. +\def\@@IEEEeqnarraybox[#1]{\relax\begingroup\IEEEnormalcatcodes\@ifnextchar[{\@@@IEEEeqnarraybox[#1]}{\@@@IEEEeqnarraybox[#1][b]}} +\def\@@@IEEEeqnarraybox[#1][#2]{\relax\@ifnextchar[{\@@@@IEEEeqnarraybox[#1][#2]}{\@@@@IEEEeqnarraybox[#1][#2][\relax]}} + +% #1 = decl; #2 = t,b,c; #3 = width, #4 = col specs +\def\@@@@IEEEeqnarraybox[#1][#2][#3]#4{\endgroup\@IEEEeqnarrayISinnerfalse % not yet within the lines of the halign + \@IEEEeqnarraymasterstrutsave% save current master strut values + \@IEEEeqnarraystrutsize{0pt}{0pt}[\relax]% turn off struts by default + \@IEEEeqnarrayusemasterstruttrue% use master strut till user asks otherwise + \IEEEvisiblestrutsfalse% diagnostic mode defaults to off + % no extra space unless the user specifically requests it + \lineskip=0pt\relax% + \lineskiplimit=0pt\relax% + \baselineskip=\normalbaselineskip\relax% + \jot=\IEEEnormaljot\relax% + \mathsurround\z@\relax% no extra spacing around math + % the default end glues are zero for an \IEEEeqnarraybox + \edef\@IEEEeqnarraycolSEPdefaultstart{\@IEEEeqnarraycolSEPzero}% default start glue + \edef\@IEEEeqnarraycolSEPdefaultend{\@IEEEeqnarraycolSEPzero}% default end glue + \edef\@IEEEeqnarraycolSEPdefaultmid{\@IEEEeqnarraycolSEPzero}% default inter-column glue + \@advanceIEEEeqncolcntfalse% do not advance the col counter for each col the user uses, + % used in \IEEEeqnarraymulticol and in the preamble build + \IEEEeqnarrayboxdecl\relax% allow a way for the user to make global overrides + #1\relax% allow user to override defaults + \let\\\@IEEEeqnarrayboxcr% replace newline with one that allows optional spacing + \@IEEEbuildpreamble{#4}\relax% build the preamble and put it into \@IEEEtrantmptoksA + % add an isolation column to the preamble to stop \\'s {} from getting into the last col + \ifnum\@IEEEeqnnumcols>0\relax\@IEEEappendtoksA{&}\fi% col separator for those after the first + \toks0={##}% + % add the isolation column to the preamble + \@IEEEappendtoksA{\tabskip\z@skip\bgroup\the\toks0\egroup}% + % set the starting tabskip glue as determined by the preamble build + \tabskip=\@IEEEBPstartglue\relax + % begin the alignment + \everycr{}% + % use only the very first token to determine the positioning + \@IEEEextracttoken{#2}\relax + \ifx\@IEEEextractedtokensdiscarded\@empty\else + \typeout{** WARNING: IEEEeqnarraybox position specifiers after the first in `\@IEEEextracttokenarg' ignored (line \the\inputlineno).}\relax + \fi + % \@IEEEextractedtoken has the first token, the rest are ignored + % if we need to put things into and hbox and go into math mode, do so now + \if@IEEEeqnarrayboxHBOXSW \leavevmode \hbox \bgroup $\fi% + % use the appropriate vbox type + \if\@IEEEextractedtoken t\relax\vtop\else\if\@IEEEextractedtoken c\relax% + \vcenter\else\vbox\fi\fi\bgroup% + \@IEEEeqnarrayISinnertrue% commands are now within the lines + \ifx#3\relax\halign\else\halign to #3\relax\fi% + \bgroup + % "exspand" the preamble + \span\the\@IEEEtrantmptoksA\cr} + +% carry strut status and enter the isolation/strut column, +% exit from math mode if needed, and exit +\def\end@IEEEeqnarraybox{\@IEEEeqnarrayglobalizestrutstatus% carry strut status +&% enter isolation/strut column +\@IEEEeqnarrayinsertstrut% do strut if needed +\@IEEEeqnarraymasterstrutrestore% restore the previous master strut values +% reset the strut system for next IEEEeqnarray +% (sets local strut values back to previous master strut values) +\@IEEEeqnarraystrutreset% +% ensure last line, exit from halign, close vbox +\crcr\egroup\egroup% +% exit from math mode and close hbox if needed +\if@IEEEeqnarrayboxHBOXSW $\egroup\fi} + + + +% IEEEeqnarraybox uses a modifed \\ instead of the plain \cr to +% end rows. This allows for things like \\[vskip amount] +% This "cr" macros are modified versions those for LaTeX2e's eqnarray +% For IEEEeqnarraybox, \\* is the same as \\ +% the {\ifnum0=`} braces must be kept away from the last column to avoid +% altering spacing of its math, so we use & to advance to the isolation/strut column +% carry strut status into isolation/strut column +\def\@IEEEeqnarrayboxcr{\@IEEEeqnarrayglobalizestrutstatus% carry strut status +&% enter isolation/strut column +\@IEEEeqnarrayinsertstrut% do strut if needed +% reset the strut system for next line or IEEEeqnarray +\@IEEEeqnarraystrutreset% +{\ifnum0=`}\fi% +\@ifstar{\@IEEEeqnarrayboxYCR}{\@IEEEeqnarrayboxYCR}} + +% test and setup the optional argument to \\[] +\def\@IEEEeqnarrayboxYCR{\@testopt\@IEEEeqnarrayboxXCR\z@skip} + +% IEEEeqnarraybox does not automatically increase line spacing by \jot +\def\@IEEEeqnarrayboxXCR[#1]{\ifnum0=`{\fi}% +\cr\noalign{\if@IEEEeqnarrayboxnojot\else\vskip\jot\fi\vskip#1\relax}} + + + +% usage: \@IEEEbuildpreamble{column specifiers} +% starts the halign preamble build +% the assembled preamble is put in \@IEEEtrantmptoksA +\def\@IEEEbuildpreamble#1{\@IEEEtrantmptoksA={}% clear token register +\let\@IEEEBPcurtype=u%current column type is not yet known +\let\@IEEEBPprevtype=s%the previous column type was the start +\let\@IEEEBPnexttype=u%next column type is not yet known +% ensure these are valid +\def\@IEEEBPcurglue={0pt plus 0pt minus 0pt}% +\def\@IEEEBPcurcolname{@IEEEdefault}% name of current column definition +% currently acquired numerically referenced glue +% use a name that is easier to remember +\let\@IEEEBPcurnum=\@IEEEtrantmpcountA% +\@IEEEBPcurnum=0% +% tracks number of columns in the preamble +\@IEEEeqnnumcols=0% +% record the default end glues +\edef\@IEEEBPstartglue{\@IEEEeqnarraycolSEPdefaultstart}% +\edef\@IEEEBPendglue{\@IEEEeqnarraycolSEPdefaultend}% +\edef\@IEEEedefMACRO{#1}\relax% fully expand the preamble to support macro containers +% now parse the user's column specifications +% \ignorespaces is used as a delimiter, need at least one trailing \relax because +% \@@IEEEbuildpreamble looks into the future +\expandafter\@@IEEEbuildpreamble\@IEEEedefMACRO\ignorespaces\relax\relax} + + +% usage: \@@IEEEbuildpreamble{current column}{next column} +% parses and builds the halign preamble +\def\@@IEEEbuildpreamble#1#2{\let\@@nextIEEEbuildpreamble=\@@IEEEbuildpreamble% +% use only the very first token to check the end +\@IEEEextracttokengroups{#1}\relax +\ifx\@IEEEextractedfirsttoken\ignorespaces\let\@@nextIEEEbuildpreamble=\@@IEEEfinishpreamble\else% +% identify current and next token type +\@IEEEgetcoltype{#1}{\@IEEEBPcurtype}{1}% current, error on invalid +\@IEEEgetcoltype{#2}{\@IEEEBPnexttype}{0}% next, no error on invalid next +% if curtype is a glue, get the glue def +\if\@IEEEBPcurtype g\@IEEEgetcurglue{#1}{\@IEEEBPcurglue}\fi% +% if curtype is a column, get the column def and set the current column name +\if\@IEEEBPcurtype c\@IEEEgetcurcol{#1}\fi% +% if curtype is a numeral, acquire the user defined glue +\if\@IEEEBPcurtype n\@IEEEprocessNcol{#1}\fi% +% process the acquired glue +\if\@IEEEBPcurtype g\@IEEEprocessGcol\fi% +% process the acquired col +\if\@IEEEBPcurtype c\@IEEEprocessCcol\fi% +% ready prevtype for next col spec. +\let\@IEEEBPprevtype=\@IEEEBPcurtype% +% be sure and put back the future token(s) as a group +\fi\@@nextIEEEbuildpreamble{#2}} + + +% usage: \@@IEEEfinishpreamble{discarded} +% executed just after preamble build is completed +% warn about zero cols, and if prevtype type = u, put in end tabskip glue +% argument is not used +\def\@@IEEEfinishpreamble#1{\ifnum\@IEEEeqnnumcols<1\relax +\@IEEEclspkgerror{No column specifiers declared for IEEEeqnarray}% +{At least one column type must be declared for each IEEEeqnarray.}% +\fi%num cols less than 1 +%if last type undefined, set default end tabskip glue +\if\@IEEEBPprevtype u\@IEEEappendtoksA{\tabskip=\@IEEEBPendglue}\fi} + + +% usage: \@IEEEgetcoltype{col specifier}{\output}{error more} +% Identify and return the column specifier's type code in the given +% \output macro: +% n = number +% g = glue (any other char in catagory 12) +% c = letter +% e = \ignorespaces (end of sequence) +% u = undefined +% error mode: 0 = no error message, 1 = error on invalid char +\def\@IEEEgetcoltype#1#2#3{% +% use only the very first token to determine the type +\@IEEEextracttoken{#1}\relax +% \@IEEEextractedtoken has the first token, the rest are discarded +\let#2=u\relax% assume invalid until know otherwise +\ifx\@IEEEextractedtoken\ignorespaces\let#2=e\else +\ifcat\@IEEEextractedtoken\relax\else% screen out control sequences +\if0\@IEEEextractedtoken\let#2=n\else +\if1\@IEEEextractedtoken\let#2=n\else +\if2\@IEEEextractedtoken\let#2=n\else +\if3\@IEEEextractedtoken\let#2=n\else +\if4\@IEEEextractedtoken\let#2=n\else +\if5\@IEEEextractedtoken\let#2=n\else +\if6\@IEEEextractedtoken\let#2=n\else +\if7\@IEEEextractedtoken\let#2=n\else +\if8\@IEEEextractedtoken\let#2=n\else +\if9\@IEEEextractedtoken\let#2=n\else +\ifcat,\@IEEEextractedtoken\let#2=g\relax +\else\ifcat a\@IEEEextractedtoken\let#2=c\relax\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi +\if#2u\relax +\if0\noexpand#3\relax\else\@IEEEclspkgerror{Invalid character in column specifications}% +{Only letters, numerals and certain other symbols are allowed \MessageBreak +as IEEEeqnarray column specifiers.}\fi\fi} + + +% usage: \@IEEEgetcurcol{col specifier} +% verify the letter referenced column exists +% and return its name in \@IEEEBPcurcolname +% if column specifier is invalid, use the default column @IEEEdefault +\def\@IEEEgetcurcol#1{\expandafter\ifx\csname @IEEEeqnarraycolDEF#1\endcsname\@IEEEeqnarraycolisdefined% +\def\@IEEEBPcurcolname{#1}\else% invalid column name +\@IEEEclspkgerror{Invalid column type "#1" in column specifications.\MessageBreak +Using a default centering column instead}% +{You must define IEEEeqnarray column types before use.}% +\def\@IEEEBPcurcolname{@IEEEdefault}\fi} + + +% usage: \@IEEEgetcurglue{glue specifier}{\output} +% identify the predefined (punctuation) glue value +% and return it in the given output macro +\def\@IEEEgetcurglue#1#2{% +% ! = \! (neg small) -0.16667em (-3/18 em) +% , = \, (small) 0.16667em ( 3/18 em) +% : = \: (med) 0.22222em ( 4/18 em) +% ; = \; (large) 0.27778em ( 5/18 em) +% ' = \quad 1em +% " = \qquad 2em +% . = 0.5\arraycolsep +% / = \arraycolsep +% ? = 2\arraycolsep +% * = 1fil +% + = \@IEEEeqnarraycolSEPcenter +% - = \@IEEEeqnarraycolSEPzero +% Note that all em values are referenced to the math font (textfont2) fontdimen6 +% value for 1em. +% +% use only the very first token to determine the type +\@IEEEextracttoken{#1}\relax +\ifx\@IEEEextractedtokensdiscarded\@empty\else + \typeout{** WARNING: IEEEeqnarray predefined inter-column glue type specifiers after the first in `\@IEEEextracttokenarg' ignored (line \the\inputlineno).}\relax +\fi +% get the math font 1em value +% LaTeX2e's NFSS2 does not preload the fonts, but \IEEEeqnarray needs +% to gain access to the math (\textfont2) font's spacing parameters. +% So we create a bogus box here that uses the math font to ensure +% that \textfont2 is loaded and ready. If this is not done, +% the \textfont2 stuff here may not work. +% Thanks to Bernd Raichle for his 1997 post on this topic. +{\setbox0=\hbox{$\displaystyle\relax$}}% +% fontdimen6 has the width of 1em (a quad). +\@IEEEtrantmpdimenA=\fontdimen6\textfont2\relax% +% identify the glue value based on the first token +% we discard anything after the first +\if!\@IEEEextractedtoken\@IEEEtrantmpdimenA=-0.16667\@IEEEtrantmpdimenA\edef#2{\the\@IEEEtrantmpdimenA}\else +\if,\@IEEEextractedtoken\@IEEEtrantmpdimenA=0.16667\@IEEEtrantmpdimenA\edef#2{\the\@IEEEtrantmpdimenA}\else +\if:\@IEEEextractedtoken\@IEEEtrantmpdimenA=0.22222\@IEEEtrantmpdimenA\edef#2{\the\@IEEEtrantmpdimenA}\else +\if;\@IEEEextractedtoken\@IEEEtrantmpdimenA=0.27778\@IEEEtrantmpdimenA\edef#2{\the\@IEEEtrantmpdimenA}\else +\if'\@IEEEextractedtoken\@IEEEtrantmpdimenA=1\@IEEEtrantmpdimenA\edef#2{\the\@IEEEtrantmpdimenA}\else +\if"\@IEEEextractedtoken\@IEEEtrantmpdimenA=2\@IEEEtrantmpdimenA\edef#2{\the\@IEEEtrantmpdimenA}\else +\if.\@IEEEextractedtoken\@IEEEtrantmpdimenA=0.5\arraycolsep\edef#2{\the\@IEEEtrantmpdimenA}\else +\if/\@IEEEextractedtoken\edef#2{\the\arraycolsep}\else +\if?\@IEEEextractedtoken\@IEEEtrantmpdimenA=2\arraycolsep\edef#2{\the\@IEEEtrantmpdimenA}\else +\if *\@IEEEextractedtoken\edef#2{0pt plus 1fil minus 0pt}\else +\if+\@IEEEextractedtoken\edef#2{\@IEEEeqnarraycolSEPcenter}\else +\if-\@IEEEextractedtoken\edef#2{\@IEEEeqnarraycolSEPzero}\else +\edef#2{\@IEEEeqnarraycolSEPzero}% +\@IEEEclspkgerror{Invalid predefined inter-column glue type "#1" in\MessageBreak +column specifications. Using a default value of\MessageBreak +0pt instead}% +{Only !,:;'"./?*+ and - are valid predefined glue types in the\MessageBreak +IEEEeqnarray column specifications.}\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi\fi} + + +% usage: \@IEEEprocessNcol{digit} +% process a numerical digit from the column specification +% and look up the corresponding user defined glue value +% can transform current type from n to g or a as the user defined glue is acquired +\def\@IEEEprocessNcol#1{\if\@IEEEBPprevtype g% +\@IEEEclspkgerror{Back-to-back inter-column glue specifiers in column\MessageBreak +specifications. Ignoring consecutive glue specifiers\MessageBreak +after the first}% +{You cannot have two or more glue types next to each other\MessageBreak +in the IEEEeqnarray column specifications.}% +\let\@IEEEBPcurtype=a% abort this glue, future digits will be discarded +\@IEEEBPcurnum=0\relax% +\else% if we previously aborted a glue +\if\@IEEEBPprevtype a\@IEEEBPcurnum=0\let\@IEEEBPcurtype=a%maintain digit abortion +\else%acquire this number +% save the previous type before the numerical digits started +\if\@IEEEBPprevtype n\else\let\@IEEEBPprevsavedtype=\@IEEEBPprevtype\fi% +\multiply\@IEEEBPcurnum by 10\relax% +\advance\@IEEEBPcurnum by #1\relax% add in number, \relax is needed to stop TeX's number scan +\if\@IEEEBPnexttype n\else%close acquisition +\expandafter\ifx\csname @IEEEeqnarraycolSEPDEF\expandafter\romannumeral\number\@IEEEBPcurnum\endcsname\@IEEEeqnarraycolisdefined% +\edef\@IEEEBPcurglue{\csname @IEEEeqnarraycolSEP\expandafter\romannumeral\number\@IEEEBPcurnum\endcsname}% +\else%user glue not defined +\@IEEEclspkgerror{Invalid user defined inter-column glue type "\number\@IEEEBPcurnum" in\MessageBreak +column specifications. Using a default value of\MessageBreak +0pt instead}% +{You must define all IEEEeqnarray numerical inter-column glue types via\MessageBreak +\string\IEEEeqnarraydefcolsep \space before they are used in column specifications.}% +\edef\@IEEEBPcurglue{\@IEEEeqnarraycolSEPzero}% +\fi% glue defined or not +\let\@IEEEBPcurtype=g% change the type to reflect the acquired glue +\let\@IEEEBPprevtype=\@IEEEBPprevsavedtype% restore the prev type before this number glue +\@IEEEBPcurnum=0\relax%ready for next acquisition +\fi%close acquisition, get glue +\fi%discard or acquire number +\fi%prevtype glue or not +} + + +% process an acquired glue +% add any acquired column/glue pair to the preamble +\def\@IEEEprocessGcol{\if\@IEEEBPprevtype a\let\@IEEEBPcurtype=a%maintain previous glue abortions +\else +% if this is the start glue, save it, but do nothing else +% as this is not used in the preamble, but before +\if\@IEEEBPprevtype s\edef\@IEEEBPstartglue{\@IEEEBPcurglue}% +\else%not the start glue +\if\@IEEEBPprevtype g%ignore if back to back glues +\@IEEEclspkgerror{Back-to-back inter-column glue specifiers in column\MessageBreak +specifications. Ignoring consecutive glue specifiers\MessageBreak +after the first}% +{You cannot have two or more glue types next to each other\MessageBreak +in the IEEEeqnarray column specifications.}% +\let\@IEEEBPcurtype=a% abort this glue +\else% not a back to back glue +\if\@IEEEBPprevtype c\relax% if the previoustype was a col, add column/glue pair to preamble +\ifnum\@IEEEeqnnumcols>0\relax\@IEEEappendtoksA{&}\fi +\toks0={##}% +% make preamble advance col counter if this environment needs this +\if@advanceIEEEeqncolcnt\@IEEEappendtoksA{\global\advance\@IEEEeqncolcnt by 1\relax}\fi +% insert the column defintion into the preamble, being careful not to expand +% the column definition +\@IEEEappendtoksA{\tabskip=\@IEEEBPcurglue}% +\@IEEEappendNOEXPANDtoksA{\begingroup\csname @IEEEeqnarraycolPRE}% +\@IEEEappendtoksA{\@IEEEBPcurcolname}% +\@IEEEappendNOEXPANDtoksA{\endcsname}% +\@IEEEappendtoksA{\the\toks0}% +\@IEEEappendNOEXPANDtoksA{\relax\relax\relax\relax\relax% +\relax\relax\relax\relax\relax\csname @IEEEeqnarraycolPOST}% +\@IEEEappendtoksA{\@IEEEBPcurcolname}% +\@IEEEappendNOEXPANDtoksA{\endcsname\relax\relax\relax\relax\relax% +\relax\relax\relax\relax\relax\endgroup}% +\advance\@IEEEeqnnumcols by 1\relax%one more column in the preamble +\else% error: non-start glue with no pending column +\@IEEEclspkgerror{Inter-column glue specifier without a prior column\MessageBreak +type in the column specifications. Ignoring this glue\MessageBreak +specifier}% +{Except for the first and last positions, glue can be placed only\MessageBreak +between column types.}% +\let\@IEEEBPcurtype=a% abort this glue +\fi% previous was a column +\fi% back-to-back glues +\fi% is start column glue +\fi% prev type not a +} + + +% process an acquired letter referenced column and, if necessary, add it to the preamble +\def\@IEEEprocessCcol{\if\@IEEEBPnexttype g\else +\if\@IEEEBPnexttype n\else +% we have a column followed by something other than a glue (or numeral glue) +% so we must add this column to the preamble now +\ifnum\@IEEEeqnnumcols>0\relax\@IEEEappendtoksA{&}\fi%col separator for those after the first +\if\@IEEEBPnexttype e\@IEEEappendtoksA{\tabskip=\@IEEEBPendglue\relax}\else%put in end glue +\@IEEEappendtoksA{\tabskip=\@IEEEeqnarraycolSEPdefaultmid\relax}\fi% or default mid glue +\toks0={##}% +% make preamble advance col counter if this environment needs this +\if@advanceIEEEeqncolcnt\@IEEEappendtoksA{\global\advance\@IEEEeqncolcnt by 1\relax}\fi +% insert the column definition into the preamble, being careful not to expand +% the column definition +\@IEEEappendNOEXPANDtoksA{\begingroup\csname @IEEEeqnarraycolPRE}% +\@IEEEappendtoksA{\@IEEEBPcurcolname}% +\@IEEEappendNOEXPANDtoksA{\endcsname}% +\@IEEEappendtoksA{\the\toks0}% +\@IEEEappendNOEXPANDtoksA{\relax\relax\relax\relax\relax% +\relax\relax\relax\relax\relax\csname @IEEEeqnarraycolPOST}% +\@IEEEappendtoksA{\@IEEEBPcurcolname}% +\@IEEEappendNOEXPANDtoksA{\endcsname\relax\relax\relax\relax\relax% +\relax\relax\relax\relax\relax\endgroup}% +\advance\@IEEEeqnnumcols by 1\relax%one more column in the preamble +\fi%next type not numeral +\fi%next type not glue +} + + +%% +%% END OF IEEEeqnarray DEFINITIONS +%% + + + + + +% set up the running headers and footers +% +% header and footer font and size specifications +\def\@IEEEheaderstyle{\normalfont\scriptsize} +\def\@IEEEfooterstyle{\normalfont\scriptsize} +% +% compsoc uses sans-serif headers and footers +\ifCLASSOPTIONcompsoc + \def\@IEEEheaderstyle{\normalfont\sffamily\scriptsize} + \def\@IEEEfooterstyle{\normalfont\sffamily\scriptsize} +\fi + + +% standard page style, ps@headings +\def\ps@headings{% default to standard twoside headers, no footers +% will change later if the mode requires otherwise +\def\@oddhead{\hbox{}\@IEEEheaderstyle\rightmark\hfil\thepage}\relax +\def\@evenhead{\@IEEEheaderstyle\thepage\hfil\leftmark\hbox{}}\relax +\let\@oddfoot\@empty +\let\@evenfoot\@empty +\ifCLASSOPTIONtechnote + % technote twoside + \def\@oddhead{\hbox{}\@IEEEheaderstyle\leftmark\hfil\thepage}\relax + \def\@evenhead{\@IEEEheaderstyle\thepage\hfil\leftmark\hbox{}}\relax +\fi +\ifCLASSOPTIONdraftcls + % draft footers + \def\@oddfoot{\@IEEEfooterstyle\@date\hfil DRAFT}\relax + \def\@evenfoot{\@IEEEfooterstyle DRAFT\hfil\@date}\relax +\fi +% oneside +\if@twoside\else + % standard one side headers + \def\@oddhead{\hbox{}\@IEEEheaderstyle\leftmark\hfil\thepage}\relax + \let\@evenhead\@empty + \ifCLASSOPTIONdraftcls + % oneside draft footers + \def\@oddfoot{\@IEEEfooterstyle\@date\hfil DRAFT}\relax + \let\@evenfoot\@empty + \fi +\fi +% turn off headers for conferences +\ifCLASSOPTIONconference + \let\@oddhead\@empty + \let\@evenhead\@empty +\fi +% turn off footers for draftclsnofoot +\ifCLASSOPTIONdraftclsnofoot + \let\@oddfoot\@empty + \let\@evenfoot\@empty +\fi} + + +% title page style, ps@IEEEtitlepagestyle +\def\ps@IEEEtitlepagestyle{% default title page headers, no footers +\def\@oddhead{\hbox{}\@IEEEheaderstyle\leftmark\hfil\thepage}\relax +\def\@evenhead{\@IEEEheaderstyle\thepage\hfil\leftmark\hbox{}}\relax +\let\@oddfoot\@empty +\let\@evenfoot\@empty +% will change later if the mode requires otherwise +\ifCLASSOPTIONdraftcls + % draft footers + \ifCLASSOPTIONdraftclsnofoot\else + % but only if not draftclsnofoot + \def\@oddfoot{\@IEEEfooterstyle\@date\hfil DRAFT}\relax + \def\@evenfoot{\@IEEEfooterstyle DRAFT\hfil\@date}\relax + \fi +\else + % all nondraft mode footers + \if@IEEEusingpubid + % for title pages that are using a pubid + % do not repeat pubid on the title page if using a peer review cover page + \ifCLASSOPTIONpeerreview\else + % for noncompsoc papers, the pubid uses footnotesize and + % is at the same vertical position as where the last baseline would normally be + \def\@oddfoot{\hbox{}\hss\@IEEEfooterstyle\footnotesize\raisebox{\footskip}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \def\@evenfoot{\hbox{}\hss\@IEEEfooterstyle\footnotesize\raisebox{\footskip}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \ifCLASSOPTIONcompsoc + % for compsoc papers, the pubid is at the same vertical position as the normal footer + \def\@oddfoot{\hbox{}\hss\@IEEEfooterstyle\raisebox{0pt}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \def\@evenfoot{\hbox{}\hss\@IEEEfooterstyle\raisebox{0pt}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \fi + \fi + \fi +\fi +% turn off headers for conferences +\ifCLASSOPTIONconference + \let\@oddhead\@empty + \let\@evenhead\@empty +\fi} + + +% peer review cover page style, ps@IEEEpeerreviewcoverpagestyle +\def\ps@IEEEpeerreviewcoverpagestyle{% default peer review cover no headers, no footers +\let\@oddhead\@empty +\let\@evenhead\@empty +\let\@oddfoot\@empty +\let\@evenfoot\@empty +% will change later if the mode requires otherwise +\ifCLASSOPTIONdraftcls + % draft footers + \ifCLASSOPTIONdraftclsnofoot\else + % but only if not draftclsnofoot + \def\@oddfoot{\@IEEEfooterstyle\@date\hfil DRAFT}\relax + \def\@evenfoot{\@IEEEfooterstyle DRAFT\hfil\@date}\relax + \fi +\else + % all nondraft mode footers + \if@IEEEusingpubid + % for peer review cover pages that are using a pubid + % for noncompsoc papers, the pubid uses footnotesize and + % is at the same vertical position as where the last baseline would normally be + \def\@oddfoot{\hbox{}\hss\@IEEEfooterstyle\footnotesize\raisebox{\footskip}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \def\@evenfoot{\hbox{}\hss\@IEEEfooterstyle\footnotesize\raisebox{\footskip}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \ifCLASSOPTIONcompsoc + % for compsoc papers, the pubid is at the same vertical position as the normal footer + \def\@oddfoot{\hbox{}\hss\@IEEEfooterstyle\raisebox{0pt}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \def\@evenfoot{\hbox{}\hss\@IEEEfooterstyle\raisebox{0pt}[0pt][0pt]{\@IEEEpubid}\hss\hbox{}}\relax + \fi + \fi +\fi} + + + +%% Defines the command for putting the header. +%% Note that all the text is forced into uppercase, if you have some text +%% that needs to be in lower case, for instance et. al., then either manually +%% set \leftmark and \rightmark or use \MakeLowercase{et. al.} within the +%% arguments to \markboth. +%% V1.7b add \protect to work with Babel +\def\markboth#1#2{\def\leftmark{\MakeUppercase{\protect#1}}% +\def\rightmark{\MakeUppercase{\protect#2}}} + +\def\today{\ifcase\month\or + January\or February\or March\or April\or May\or June\or + July\or August\or September\or October\or November\or December\fi + \space\number\day, \number\year} + + + + +%% CITATION AND BIBLIOGRAPHY COMMANDS +%% +%% V1.6 no longer supports the older, nonstandard \shortcite and \citename setup stuff +% +% +% Modify Latex2e \@citex to separate citations with "], [" +\def\@citex[#1]#2{% + \let\@citea\@empty + \@cite{\@for\@citeb:=#2\do + {\@citea\def\@citea{], [}% + \edef\@citeb{\expandafter\@firstofone\@citeb\@empty}% + \if@filesw\immediate\write\@auxout{\string\citation{\@citeb}}\fi + \@ifundefined{b@\@citeb}{\mbox{\reset@font\bfseries ?}% + \G@refundefinedtrue + \@latex@warning + {Citation `\@citeb' on page \thepage \space undefined}}% + {\hbox{\csname b@\@citeb\endcsname}}}}{#1}} + +% V1.6 we create hooks for the optional use of Donald Arseneau's +% cite.sty package. cite.sty is "smart" and will notice that the +% following format controls are already defined and will not +% redefine them. The result will be the proper sorting of the +% citation numbers and auto detection of 3 or more entry "ranges" - +% all in IEEE style: [1], [2], [5]--[7], [12] +% This also allows for an optional note, i.e., \cite[mynote]{..}. +% If the \cite with note has more than one reference, the note will +% be applied to the last of the listed references. It is generally +% desired that if a note is given, only one reference is listed in +% that \cite. +% Thanks to Mr. Arseneau for providing the required format arguments +% to produce the IEEE style. +\def\citepunct{], [} +\def\citedash{]--[} + +% V1.7 default to using same font for urls made by url.sty +\AtBeginDocument{\csname url@samestyle\endcsname} + +% V1.6 class files should always provide these +\def\newblock{\hskip .11em\@plus.33em\@minus.07em} +\let\@openbib@code\@empty +% V1.8b article.cls is now providing these too +% we do not use \@mkboth, nor alter the page style +\newenvironment{theindex} + {\if@twocolumn + \@restonecolfalse + \else + \@restonecoltrue + \fi + \twocolumn[\section*{\indexname}]% + \parindent\z@ + \parskip\z@ \@plus .3\p@\relax + \columnseprule \z@ + \columnsep 35\p@ + \let\item\@idxitem} + {\if@restonecol\onecolumn\else\clearpage\fi} +\newcommand\@idxitem{\par\hangindent 40\p@} +\newcommand\subitem{\@idxitem \hspace*{20\p@}} +\newcommand\subsubitem{\@idxitem \hspace*{30\p@}} +\newcommand\indexspace{\par \vskip 10\p@ \@plus5\p@ \@minus3\p@\relax} + + + +% Provide support for the control entries of IEEEtran.bst V1.00 and later. +% V1.7 optional argument allows for a different aux file to be specified in +% order to handle multiple bibliographies. For example, with multibib.sty: +% \newcites{sec}{Secondary Literature} +% \bstctlcite[@auxoutsec]{BSTcontrolhak} +\def\bstctlcite{\@ifnextchar[{\@bstctlcite}{\@bstctlcite[@auxout]}} +\def\@bstctlcite[#1]#2{\@bsphack + \@for\@citeb:=#2\do{% + \edef\@citeb{\expandafter\@firstofone\@citeb}% + \if@filesw\immediate\write\csname #1\endcsname{\string\citation{\@citeb}}\fi}% + \@esphack} + +% \IEEEnoauxwrite{} allows for citations that do not add to or affect +% the order of the existing citation list. Can be useful for \cite +% within \thanks{}. +\DeclareRobustCommand{\IEEEnoauxwrite}[1]{\relax +\if@filesw +\@fileswfalse +#1\relax\relax\relax\relax\relax +\@fileswtrue +\else +#1\relax\relax\relax\relax\relax +\fi} + +% V1.6 provide a way for a user to execute a command just before +% a given reference number - used to insert a \newpage to balance +% the columns on the last page +\edef\@IEEEtriggerrefnum{0} % the default of zero means that + % the command is not executed +\def\@IEEEtriggercmd{\newpage} + +% allow the user to alter the triggered command +\long\def\IEEEtriggercmd#1{\long\def\@IEEEtriggercmd{#1}} + +% allow user a way to specify the reference number just before the +% command is executed +\def\IEEEtriggeratref#1{\@IEEEtrantmpcountA=#1% +\edef\@IEEEtriggerrefnum{\the\@IEEEtrantmpcountA}}% + +% trigger command at the given reference +\def\@IEEEbibitemprefix{\@IEEEtrantmpcountA=\@IEEEtriggerrefnum\relax% +\advance\@IEEEtrantmpcountA by -1\relax% +\ifnum\c@enumiv=\@IEEEtrantmpcountA\relax\@IEEEtriggercmd\relax\fi} + + +\def\@biblabel#1{[#1]} + +% compsoc journals and conferences left align the reference numbers +\@IEEEcompsoconly{\def\@biblabel#1{[#1]\hfill}} + +% controls bib item spacing +\def\IEEEbibitemsep{0pt plus .5pt} + +\@IEEEcompsocconfonly{\def\IEEEbibitemsep{0.5\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip}} + + +\def\thebibliography#1{\section*{\refname}% + \addcontentsline{toc}{section}{\refname}% + % V1.6 add some rubber space here and provide a command trigger + \footnotesize\vskip 0.3\baselineskip plus 0.1\baselineskip minus 0.1\baselineskip% + \list{\@biblabel{\@arabic\c@enumiv}}% + {\settowidth\labelwidth{\@biblabel{#1}}% + \leftmargin\labelwidth + \advance\leftmargin\labelsep\relax + \itemsep \IEEEbibitemsep\relax + \usecounter{enumiv}% + \let\p@enumiv\@empty + \renewcommand\theenumiv{\@arabic\c@enumiv}}% + \let\@IEEElatexbibitem\bibitem% + \def\bibitem{\@IEEEbibitemprefix\@IEEElatexbibitem}% +\def\newblock{\hskip .11em plus .33em minus .07em}% +% originally: +% \sloppy\clubpenalty4000\widowpenalty4000% +% by adding the \interlinepenalty here, we make it more +% difficult, but not impossible, for LaTeX to break within a reference. +% The IEEE almost never breaks a reference (but they do it more often with +% technotes). You may get an underfull vbox warning around the bibliography, +% but the final result will be much more like what the IEEE will publish. +% MDS 11/2000 +\ifCLASSOPTIONtechnote\sloppy\clubpenalty4000\widowpenalty4000\interlinepenalty100% +\else\sloppy\clubpenalty4000\widowpenalty4000\interlinepenalty500\fi% + \sfcode`\.=1000\relax} +\let\endthebibliography=\endlist + + + + +% TITLE PAGE COMMANDS +% +% +% \IEEEmembership is used to produce the sublargesize italic font used to indicate author +% IEEE membership. compsoc uses a large size sans slant font +\def\IEEEmembership#1{{\@IEEEnotcompsoconly{\sublargesize}\normalfont\@IEEEcompsoconly{\sffamily}\textit{#1}}} + + +% \IEEEauthorrefmark{} produces a footnote type symbol to indicate author affiliation. +% When given an argument of 1 to 9, \IEEEauthorrefmark{} follows the standard LaTeX footnote +% symbol sequence convention. However, for arguments 10 and above, \IEEEauthorrefmark{} +% reverts to using lower case roman numerals, so it cannot overflow. Do note that you +% cannot use \footnotemark[] in place of \IEEEauthorrefmark{} within \author as the footnote +% symbols will have been turned off to prevent \thanks from creating footnote marks. +% \IEEEauthorrefmark{} produces a symbol that appears to LaTeX as having zero vertical +% height - this allows for a more compact line packing, but the user must ensure that +% the interline spacing is large enough to prevent \IEEEauthorrefmark{} from colliding +% with the text above. +% V1.7 make this a robust command +% V1.8 transmag uses an arabic author affiliation symbol +\ifCLASSOPTIONtransmag +\DeclareRobustCommand*{\IEEEauthorrefmark}[1]{\raisebox{0pt}[0pt][0pt]{\textsuperscript{\footnotesize #1}}} +\else +\DeclareRobustCommand*{\IEEEauthorrefmark}[1]{\raisebox{0pt}[0pt][0pt]{\textsuperscript{\footnotesize\ensuremath{\ifcase#1\or *\or \dagger\or \ddagger\or% + \mathsection\or \mathparagraph\or \|\or **\or \dagger\dagger% + \or \ddagger\ddagger \else\textsuperscript{\expandafter\romannumeral#1}\fi}}}} +\fi + + +% FONT CONTROLS AND SPACINGS FOR CONFERENCE MODE AUTHOR NAME AND AFFILIATION BLOCKS +% +% The default font styles for the author name and affiliation blocks (confmode) +\def\@IEEEauthorblockNstyle{\normalfont\@IEEEcompsocnotconfonly{\sffamily}\sublargesize} +\def\@IEEEauthorblockAstyle{\normalfont\@IEEEcompsocnotconfonly{\sffamily}\@IEEEcompsocconfonly{\itshape}\normalsize} +% The default if the user does not use an author block +\def\@IEEEauthordefaulttextstyle{\normalfont\@IEEEcompsocnotconfonly{\sffamily}\sublargesize} + +% adjustment spacing from title (or special paper notice) to author name blocks (confmode) +% can be negative +\def\@IEEEauthorblockconfadjspace{-0.25em} +% compsoc conferences need more space here +\@IEEEcompsocconfonly{\def\@IEEEauthorblockconfadjspace{0.75\@IEEEnormalsizeunitybaselineskip}} + +% spacing between name and affiliation blocks (confmode) +% This can be negative. +% The IEEE doesn't want any added spacing here, but I will leave these +% controls in place in case they ever change their mind. +% Personally, I like 0.75ex. +%\def\@IEEEauthorblockNtopspace{0.75ex} +%\def\@IEEEauthorblockAtopspace{0.75ex} +\def\@IEEEauthorblockNtopspace{0.0ex} +\def\@IEEEauthorblockAtopspace{0.0ex} +\ifCLASSOPTIONtransmag +% transmag uses one line of space above first affiliation block +\def\@IEEEauthorblockAtopspace{1\@IEEEnormalsizeunitybaselineskip} +\fi + +% baseline spacing within name and affiliation blocks (confmode) +% must be positive, spacings below certain values will make +% the position of line of text sensitive to the contents of the +% line above it i.e., whether or not the prior line has descenders, +% subscripts, etc. For this reason it is a good idea to keep +% these above 2.6ex +\def\@IEEEauthorblockNinterlinespace{2.6ex} +\def\@IEEEauthorblockAinterlinespace{2.75ex} + +% This tracks the required strut size. +% See the \@IEEEauthorhalign command for the actual default value used. +\def\@IEEEauthorblockXinterlinespace{2.7ex} + +% variables to retain font size and style across groups +% values given here have no effect as they will be overwritten later +\gdef\@IEEESAVESTATEfontsize{10} +\gdef\@IEEESAVESTATEfontbaselineskip{12} +\gdef\@IEEESAVESTATEfontencoding{OT1} +\gdef\@IEEESAVESTATEfontfamily{ptm} +\gdef\@IEEESAVESTATEfontseries{m} +\gdef\@IEEESAVESTATEfontshape{n} + +% saves the current font attributes +\def\@IEEEcurfontSAVE{\global\let\@IEEESAVESTATEfontsize\f@size% +\global\let\@IEEESAVESTATEfontbaselineskip\f@baselineskip% +\global\let\@IEEESAVESTATEfontencoding\f@encoding% +\global\let\@IEEESAVESTATEfontfamily\f@family% +\global\let\@IEEESAVESTATEfontseries\f@series% +\global\let\@IEEESAVESTATEfontshape\f@shape} + +% restores the saved font attributes +\def\@IEEEcurfontRESTORE{\fontsize{\@IEEESAVESTATEfontsize}{\@IEEESAVESTATEfontbaselineskip}% +\fontencoding{\@IEEESAVESTATEfontencoding}% +\fontfamily{\@IEEESAVESTATEfontfamily}% +\fontseries{\@IEEESAVESTATEfontseries}% +\fontshape{\@IEEESAVESTATEfontshape}% +\selectfont} + + +% variable to indicate if the current block is the first block in the column +\newif\if@IEEEprevauthorblockincol \@IEEEprevauthorblockincolfalse + + +% the command places a strut with height and depth = \@IEEEauthorblockXinterlinespace +% we use this technique to have complete manual control over the spacing of the lines +% within the halign environment. +% We set the below baseline portion at 30%, the above +% baseline portion at 70% of the total length. +% Responds to changes in the document's \baselinestretch +\def\@IEEEauthorstrutrule{\@IEEEtrantmpdimenA\@IEEEauthorblockXinterlinespace% +\@IEEEtrantmpdimenA=\baselinestretch\@IEEEtrantmpdimenA% +\rule[-0.3\@IEEEtrantmpdimenA]{0pt}{\@IEEEtrantmpdimenA}} + + +% blocks to hold the authors' names and affilations. +% Makes formatting easy for conferences +% +% use real definitions in conference mode +% name block +\def\IEEEauthorblockN#1{\relax\@IEEEauthorblockNstyle% set the default text style +\gdef\@IEEEauthorblockXinterlinespace{0pt}% disable strut for spacer row +% the \expandafter hides the \cr in conditional tex, see the array.sty docs +% for details, probably not needed here as the \cr is in a macro +% do a spacer row if needed +\if@IEEEprevauthorblockincol\expandafter\@IEEEauthorblockNtopspaceline\fi +\global\@IEEEprevauthorblockincoltrue% we now have a block in this column +%restore the correct strut value +\gdef\@IEEEauthorblockXinterlinespace{\@IEEEauthorblockNinterlinespace}% +% input the author names +#1% +% end the row if the user did not already +\crcr} +% spacer row for names +\def\@IEEEauthorblockNtopspaceline{\cr\noalign{\vskip\@IEEEauthorblockNtopspace}} +% +% affiliation block +\def\IEEEauthorblockA#1{\relax\@IEEEauthorblockAstyle% set the default text style +\gdef\@IEEEauthorblockXinterlinespace{0pt}%disable strut for spacer row +% the \expandafter hides the \cr in conditional tex, see the array.sty docs +% for details, probably not needed here as the \cr is in a macro +% do a spacer row if needed +\if@IEEEprevauthorblockincol\expandafter\@IEEEauthorblockAtopspaceline\fi +\global\@IEEEprevauthorblockincoltrue% we now have a block in this column +%restore the correct strut value +\gdef\@IEEEauthorblockXinterlinespace{\@IEEEauthorblockAinterlinespace}% +% input the author affiliations +#1% +% end the row if the user did not already +\crcr +% V1.8 transmag does not use any additional affiliation spacing after the first author +\ifCLASSOPTIONtransmag\gdef\@IEEEauthorblockAtopspace{0pt}\fi} + +% spacer row for affiliations +\def\@IEEEauthorblockAtopspaceline{\cr\noalign{\vskip\@IEEEauthorblockAtopspace}} + + +% allow papers to compile even if author blocks are used in modes other +% than conference or peerreviewca. For such cases, we provide dummy blocks. +\ifCLASSOPTIONconference +\else + \ifCLASSOPTIONpeerreviewca\else + % not conference, peerreviewca or transmag mode + \ifCLASSOPTIONtransmag\else + \def\IEEEauthorblockN#1{#1}% + \def\IEEEauthorblockA#1{#1}% + \fi + \fi +\fi + + + +% we provide our own halign so as not to have to depend on tabular +\def\@IEEEauthorhalign{\@IEEEauthordefaulttextstyle% default text style + \lineskip=0pt\relax% disable line spacing + \lineskiplimit=0pt\relax% + \baselineskip=0pt\relax% + \@IEEEcurfontSAVE% save the current font + \mathsurround\z@\relax% no extra spacing around math + \let\\\@IEEEauthorhaligncr% replace newline with halign friendly one + \tabskip=0pt\relax% no column spacing + \everycr{}% ensure no problems here + \@IEEEprevauthorblockincolfalse% no author blocks yet + \def\@IEEEauthorblockXinterlinespace{2.7ex}% default interline space + \vtop\bgroup%vtop box + \halign\bgroup&\relax\hfil\@IEEEcurfontRESTORE\relax ##\relax + \hfil\@IEEEcurfontSAVE\@IEEEauthorstrutrule\cr} + +% ensure last line, exit from halign, close vbox +\def\end@IEEEauthorhalign{\crcr\egroup\egroup} + +% handle bogus star form +\def\@IEEEauthorhaligncr{{\ifnum0=`}\fi\@ifstar{\@@IEEEauthorhaligncr}{\@@IEEEauthorhaligncr}} + +% test and setup the optional argument to \\[] +\def\@@IEEEauthorhaligncr{\@testopt\@@@IEEEauthorhaligncr\z@skip} + +% end the line and do the optional spacer +\def\@@@IEEEauthorhaligncr[#1]{\ifnum0=`{\fi}\cr\noalign{\vskip#1\relax}} + + + +% flag to prevent multiple \and warning messages +\newif\if@IEEEWARNand +\@IEEEWARNandtrue + +% if in conference or peerreviewca modes, we support the use of \and as \author is a +% tabular environment, otherwise we warn the user that \and is invalid +% outside of conference or peerreviewca modes. +\def\and{\relax} % provide a bogus \and that we will then override + +\renewcommand{\and}[1][\relax]{\if@IEEEWARNand\typeout{** WARNING: \noexpand\and is valid only + when in conference or peerreviewca}\typeout{modes (line \the\inputlineno).}\fi\global\@IEEEWARNandfalse} + +\ifCLASSOPTIONconference% +\renewcommand{\and}[1][\hfill]{\end{@IEEEauthorhalign}#1\begin{@IEEEauthorhalign}}% +\fi +\ifCLASSOPTIONpeerreviewca +\renewcommand{\and}[1][\hfill]{\end{@IEEEauthorhalign}#1\begin{@IEEEauthorhalign}}% +\fi +% V1.8 transmag uses conference author format +\ifCLASSOPTIONtransmag +\renewcommand{\and}[1][\hfill]{\end{@IEEEauthorhalign}#1\begin{@IEEEauthorhalign}}% +\fi + +% page clearing command +% based on LaTeX2e's \cleardoublepage, but allows different page styles +% for the inserted blank pages +\def\@IEEEcleardoublepage#1{\clearpage\if@twoside\ifodd\c@page\else +\hbox{}\thispagestyle{#1}\newpage\if@twocolumn\hbox{}\thispagestyle{#1}\newpage\fi\fi\fi} + +% V1.8b hooks to allow adjustment of space above title +\def\IEEEtitletopspace{0.5\baselineskip} +% an added extra amount to allow for adjustment/offset +\def\IEEEtitletopspaceextra{0pt} + +% user command to invoke the title page +\def\maketitle{\par% + \begingroup% + \normalfont% + \def\thefootnote{}% the \thanks{} mark type is empty + \def\footnotemark{}% and kill space from \thanks within author + \let\@makefnmark\relax% V1.7, must *really* kill footnotemark to remove all \textsuperscript spacing as well. + \footnotesize% equal spacing between thanks lines + \footnotesep 0.7\baselineskip%see global setting of \footnotesep for more info + % V1.7 disable \thanks note indention for compsoc + \@IEEEcompsoconly{\long\def\@makefntext##1{\parindent 1em\noindent\hbox{\@makefnmark}##1}}% + \normalsize% + \ifCLASSOPTIONpeerreview + \newpage\global\@topnum\z@ \@maketitle\@IEEEstatictitlevskip\@IEEEaftertitletext% + \thispagestyle{IEEEpeerreviewcoverpagestyle}\@thanks% + \else + \if@twocolumn% + \ifCLASSOPTIONtechnote% + \newpage\global\@topnum\z@ \@maketitle\@IEEEstatictitlevskip\@IEEEaftertitletext% + \else + \twocolumn[{\IEEEquantizevspace{\@maketitle}[\IEEEquantizedisabletitlecmds]{0pt}[-\topskip]{\baselineskip}{\@IEEENORMtitlevspace}{\@IEEEMINtitlevspace}\@IEEEaftertitletext}]% + \fi + \else + \newpage\global\@topnum\z@ \@maketitle\@IEEEstatictitlevskip\@IEEEaftertitletext% + \fi + \thispagestyle{IEEEtitlepagestyle}\@thanks% + \fi + % pullup page for pubid if used. + \if@IEEEusingpubid + \enlargethispage{-\@IEEEpubidpullup}% + \fi + \endgroup + \setcounter{footnote}{0}\let\maketitle\relax\let\@maketitle\relax + \gdef\@thanks{}% + % v1.6b do not clear these as we will need the title again for peer review papers + % \gdef\@author{}\gdef\@title{}% + \let\thanks\relax} + + +% V1.8 parbox to format \@IEEEtitleabstractindextext +\long\def\@IEEEtitleabstractindextextbox#1{\parbox{1\textwidth}{#1}} +% V1.8 compsoc is partial width +\ifCLASSOPTIONcompsoc +% comparison with proofs suggests it's in the range of 92.1-92.3% +\long\def\@IEEEtitleabstractindextextbox#1{\parbox{0.922\textwidth}{\@IEEEcompsocnotconfonly{\rightskip\@flushglue\leftskip\z@skip}#1}} +\fi + +% formats the Title, authors names, affiliations and special paper notice +% THIS IS A CONTROLLED SPACING COMMAND! Do not allow blank lines or unintentional +% spaces to enter the definition - use % at the end of each line +\def\@maketitle{\newpage +\bgroup\par\vskip\IEEEtitletopspace\vskip\IEEEtitletopspaceextra\centering% +\ifCLASSOPTIONtechnote% technotes, V1.8a abstract and index terms are not treated differently for compsoc technotes + {\bfseries\large\@IEEEcompsoconly{\Large\sffamily}\@title\par}\vskip 1.3em{\lineskip .5em\@IEEEcompsoconly{\large\sffamily}\@author + \@IEEEspecialpapernotice\par}\relax +\else% not a technote + \vskip0.2em{\Huge\ifCLASSOPTIONtransmag\bfseries\LARGE\fi\@IEEEcompsoconly{\sffamily}\@IEEEcompsocconfonly{\normalfont\normalsize\vskip 2\@IEEEnormalsizeunitybaselineskip + \bfseries\Large}\@IEEEcompsocnotconfonly{\vskip 0.75\@IEEEnormalsizeunitybaselineskip}\@title\par}\relax + \@IEEEcompsocnotconfonly{\vskip 0.5\@IEEEnormalsizeunitybaselineskip}\vskip1.0em\par% + % V1.6 handle \author differently if in conference mode + \ifCLASSOPTIONconference% + {\@IEEEspecialpapernotice\mbox{}\vskip\@IEEEauthorblockconfadjspace% + \mbox{}\hfill\begin{@IEEEauthorhalign}\@author\end{@IEEEauthorhalign}\hfill\mbox{}\par}\relax + \else% peerreviewca, peerreview or journal + \ifCLASSOPTIONpeerreviewca + % peerreviewca handles author names just like conference mode + {\@IEEEcompsoconly{\sffamily}\@IEEEspecialpapernotice\mbox{}\vskip\@IEEEauthorblockconfadjspace% + \mbox{}\hfill\begin{@IEEEauthorhalign}\@author\end{@IEEEauthorhalign}\hfill\mbox{}\par + {\@IEEEcompsoconly{\vskip 1.5em\relax + \@IEEEtitleabstractindextextbox{\@IEEEtitleabstractindextext}\par\noindent\hfill + \IEEEcompsocdiamondline\hfill\hbox{}\par}}}\relax + \else% journal, peerreview or transmag + \ifCLASSOPTIONtransmag + % transmag also handles author names just like conference mode + % it also uses \@IEEEtitleabstractindextex, but with one line less + % space above, and one more below + {\@IEEEspecialpapernotice\mbox{}\vskip\@IEEEauthorblockconfadjspace% + \mbox{}\hfill\begin{@IEEEauthorhalign}\@author\end{@IEEEauthorhalign}\hfill\mbox{}\par + {\vspace{0.5\baselineskip}\relax\@IEEEtitleabstractindextextbox{\@IEEEtitleabstractindextext}\vspace{-1\baselineskip}\par}}\relax + \else% journal or peerreview + {\lineskip.5em\@IEEEcompsoconly{\sffamily}\sublargesize\@author\@IEEEspecialpapernotice\par + {\@IEEEcompsoconly{\vskip 1.5em\relax + \@IEEEtitleabstractindextextbox{\@IEEEtitleabstractindextext}\par\noindent\hfill + \IEEEcompsocdiamondline\hfill\hbox{}\par}}}\relax + \fi + \fi + \fi +\fi\par\addvspace{0.5\baselineskip}\egroup} + + +% V1.7 Computer Society "diamond line" which follows index terms for nonconference papers +% V1.8a full width diamond line for single column use +\def\@IEEEcompsocdiamondlinei{\vrule depth 0pt height 0.5pt width 4cm\nobreak\hspace{7.5pt}\nobreak +\raisebox{-3.5pt}{\fontfamily{pzd}\fontencoding{U}\fontseries{m}\fontshape{n}\fontsize{11}{12}\selectfont\char70}\nobreak +\hspace{7.5pt}\nobreak\vrule depth 0pt height 0.5pt width 4cm\relax} +% V1.8a narrower width diamond line for double column use +\def\@IEEEcompsocdiamondlineii{\vrule depth 0pt height 0.5pt width 2.5cm\nobreak\hspace{7.5pt}\nobreak +\raisebox{-3.5pt}{\fontfamily{pzd}\fontencoding{U}\fontseries{m}\fontshape{n}\fontsize{11}{12}\selectfont\char70}\nobreak +\hspace{7.5pt}\nobreak\vrule depth 0pt height 0.5pt width 2.5cm\relax} +% V1.8a bare core without rules to base a last resort on for very narrow linewidths +\def\@IEEEcompsocdiamondlineiii{\mbox{}\nobreak\hspace{7.5pt}\nobreak +\raisebox{-3.5pt}{\fontfamily{pzd}\fontencoding{U}\fontseries{m}\fontshape{n}\fontsize{11}{12}\selectfont\char70}\nobreak +\hspace{7.5pt}\nobreak\mbox{}\relax} + +% V1.8a allow \IEEEcompsocdiamondline to adjust for different linewidths. +% Use \@IEEEcompsocdiamondlinei if its width is less than 0.66\linewidth (0.487 nominal for single column) +% if not, fall back to \@IEEEcompsocdiamondlineii if its width is less than 0.75\linewidth (0.659 nominal for double column) +% if all else fails, try to make a custom diamondline based on the abnormally narrow linewidth +\def\IEEEcompsocdiamondline{\settowidth{\@IEEEtrantmpdimenA}{\@IEEEcompsocdiamondlinei}\relax +\ifdim\@IEEEtrantmpdimenA<0.66\linewidth\relax\@IEEEcompsocdiamondlinei\relax +\else +\settowidth{\@IEEEtrantmpdimenA}{\@IEEEcompsocdiamondlineii}\relax +\ifdim\@IEEEtrantmpdimenA<0.75\linewidth\relax\@IEEEcompsocdiamondlineii\relax +\else +\settowidth{\@IEEEtrantmpdimenA}{\@IEEEcompsocdiamondlineiii}\relax +\@IEEEtrantmpdimenB=\linewidth\relax +\addtolength{\@IEEEtrantmpdimenB}{-1\@IEEEtrantmpdimenA}\relax +\vrule depth 0pt height 0.5pt width 0.33\@IEEEtrantmpdimenB\@IEEEcompsocdiamondlineiii\vrule depth 0pt height 0.5pt width 0.33\@IEEEtrantmpdimenB\relax +\fi\fi} + + +% V1.7 standard LateX2e \thanks, but with \itshape under compsoc. Also make it a \long\def +% We also need to trigger the one-shot footnote rule +\def\@IEEEtriggeroneshotfootnoterule{\global\@IEEEenableoneshotfootnoteruletrue} + + +\long\def\thanks#1{\footnotemark + \protected@xdef\@thanks{\@thanks + \protect\footnotetext[\the\c@footnote]{\@IEEEcompsoconly{\itshape + \protect\@IEEEtriggeroneshotfootnoterule\relax}\ignorespaces#1}}} +\let\@thanks\@empty + + +% V1.7 allow \author to contain \par's. This is needed to allow \thanks to contain \par. +\long\def\author#1{\gdef\@author{#1}} + + +% in addition to setting up IEEEitemize, we need to remove a baselineskip space above and +% below it because \list's \pars introduce blank lines because of the footnote struts. +\def\@IEEEsetupcompsocitemizelist{\def\labelitemi{$\bullet$}% +\setlength{\IEEElabelindent}{0pt}\setlength{\labelsep}{1.2em}\setlength{\parskip}{0pt}% +\setlength{\partopsep}{0pt}\setlength{\topsep}{0.5\baselineskip}\vspace{-1\baselineskip}\relax} + + +% flag for fake non-compsoc \IEEEcompsocthanksitem - prevents line break on very first item +\newif\if@IEEEbreakcompsocthanksitem \@IEEEbreakcompsocthanksitemfalse + +\ifCLASSOPTIONcompsoc +% V1.7 compsoc bullet item \thanks +% also, we need to redefine this to destroy the argument in \IEEEquantizevspace +\long\def\IEEEcompsocitemizethanks#1{\relax\@IEEEbreakcompsocthanksitemfalse\footnotemark + \protected@xdef\@thanks{\@thanks + \protect\footnotetext[\the\c@footnote]{\itshape\protect\@IEEEtriggeroneshotfootnoterule + {\let\IEEEiedlistdecl\relax\protect\begin{IEEEitemize}[\protect\@IEEEsetupcompsocitemizelist]\ignorespaces#1\relax + \protect\end{IEEEitemize}}\protect\vspace{-1\baselineskip}}}} +\DeclareRobustCommand*{\IEEEcompsocthanksitem}{\item} +\else +% non-compsoc, allow for dual compilation via rerouting to normal \thanks +\long\def\IEEEcompsocitemizethanks#1{\thanks{#1}} +% redirect to "pseudo-par" \hfil\break\indent after swallowing [] from \IEEEcompsocthanksitem[] +\DeclareRobustCommand{\IEEEcompsocthanksitem}{\@ifnextchar [{\@IEEEthanksswallowoptionalarg}% +{\@IEEEthanksswallowoptionalarg[\relax]}} +% be sure and break only after first item, be sure and ignore spaces after optional argument +\def\@IEEEthanksswallowoptionalarg[#1]{\relax\if@IEEEbreakcompsocthanksitem\hfil\break +\indent\fi\@IEEEbreakcompsocthanksitemtrue\ignorespaces} +\fi + + +% V1.6b define the \IEEEpeerreviewmaketitle as needed +\ifCLASSOPTIONpeerreview +\def\IEEEpeerreviewmaketitle{\@IEEEcleardoublepage{empty}% +\ifCLASSOPTIONtwocolumn +\twocolumn[{\IEEEquantizevspace{\@IEEEpeerreviewmaketitle}[\IEEEquantizedisabletitlecmds]{0pt}[-\topskip]{\baselineskip}{\@IEEENORMtitlevspace}{\@IEEEMINtitlevspace}}] +\else +\newpage\@IEEEpeerreviewmaketitle\@IEEEstatictitlevskip +\fi +\thispagestyle{IEEEtitlepagestyle}} +\else +% \IEEEpeerreviewmaketitle does nothing if peer review option has not been selected +\def\IEEEpeerreviewmaketitle{\relax} +\fi + +% peerreview formats the repeated title like the title in journal papers. +\def\@IEEEpeerreviewmaketitle{\bgroup\par\addvspace{0.5\baselineskip}\centering\@IEEEcompsoconly{\sffamily}% +\normalfont\normalsize\vskip0.2em{\Huge\@title\par}\vskip1.0em\par +\par\addvspace{0.5\baselineskip}\egroup} + + + +% V1.6 +% this is a static rubber spacer between the title/authors and the main text +% used for single column text, or when the title appears in the first column +% of two column text (technotes). +\def\@IEEEstatictitlevskip{{\normalfont\normalsize +% adjust spacing to next text +% v1.6b handle peer review papers +\ifCLASSOPTIONpeerreview +% for peer review papers, the same value is used for both title pages +% regardless of the other paper modes + \vskip 1\baselineskip plus 0.375\baselineskip minus 0.1875\baselineskip +\else + \ifCLASSOPTIONconference% conference + \vskip 1\baselineskip plus 0.375\baselineskip minus 0.1875\baselineskip% + \else% + \ifCLASSOPTIONtechnote% technote + \vskip 1\baselineskip plus 0.375\baselineskip minus 0.1875\baselineskip% + \else% journal uses more space + \vskip 2.5\baselineskip plus 0.75\baselineskip minus 0.375\baselineskip% + \fi + \fi +\fi}} + + +% set the nominal and minimum values for the quantized title spacer +% the quantization algorithm will not allow the spacer size to +% become less than \@IEEEMINtitlevspace - instead it will be lengthened +% default to journal values +\def\@IEEENORMtitlevspace{2.5\baselineskip} +\def\@IEEEMINtitlevspace{2\baselineskip} +% conferences and technotes need tighter spacing +\ifCLASSOPTIONconference% conference + \def\@IEEENORMtitlevspace{1\baselineskip} + \def\@IEEEMINtitlevspace{0.75\baselineskip} +\fi +\ifCLASSOPTIONtechnote% technote + \def\@IEEENORMtitlevspace{1\baselineskip} + \def\@IEEEMINtitlevspace{0.75\baselineskip} +\fi + + +% V1.8a +\def\IEEEquantizevspace{\begingroup\@ifstar{\@IEEEquantizevspacestarformtrue\@IEEEquantizevspace}{\@IEEEquantizevspacestarformfalse\@IEEEquantizevspace}} +% \IEEEquantizevspace[output dimen register]{object}[object decl] +% {top baselineskip} +% [offset][prevdepth][lineskip limit][lineskip] +% {unit height}{nominal vspace}{minimum vspace} +% +% Calculates and creates the vspace needed to make the combined height with +% the given object an integer multiple of the given unit height. This command +% is more general than the older \@IEEEdynamictitlevspace it replaces. +% +% The star form has no effect at present, but is reserved for future use. +% +% If the optional argument [output dimen register] is given, the calculated +% vspace height is stored in the given output dimen (or skip) register +% and no other action is taken, otherwise the object followed by a vspace* +% of the appropriate height is evaluated/output. +% +% The optional object decl (declarations) is code that is evaluated just +% before the object's height is evaluated. Its intented purpose is to allow +% for the alteration or disabling of code within the object during internal +% height evaluation (e.g., \long\def\thanks#1{\relax} ). +% This special code is not invoked if/when the object is rendered at the end. +% +% The nominal vspace is the target value of the added vspace and the minimum +% vspace is the lower allowed limit. The vspacer will be the value that achieves +% integral overall height, in terms of the given unit height, that is closest +% to the nominal vspace and that is not less than the specified minimum vspace. +% +% The line spacing algorithm of TeX is somewhat involved and requires special +% care with regard to the first line of a vertical list (which is indicated +% when \prevdepth is -1000pt or less). top baselineskip specifies the +% baselineskip or topskip used prior to the object. If the height of the +% first line of the object is greater than the given top baselineskip, then +% the top baselineskip is subtracted from the height of the first line and +% that difference is considered along with the rest of the object height +% (because the object will be shifted down by an amount = +% top line height - top baselineskip). Otherwise, the height of the first line +% of the object is ignored as far as the calculations are concerned. +% This algorithm is adequate for objects that appear at the top of a page +% (e.g., titles) where \topskip spacing is used. +% +% However, as explained on page 78 of the TeXbook, interline spacing is more +% complex when \baselineskip is being used (indicated by \prevdepth > +% -1000pt). The four optional parameters offset, prevdepth, lineskip limit and +% lineskip are assumed to be equal to be 0pt, \prevdepth, \lineskiplimit and +% \lineskip, respectively, if they are omitted. +% +% The prevdepth is the depth of the line before the object, the lineskip limit +% specifies how close the top of the object can come to the bottom of the +% previous line before \baselineskip is ignored and \lineskip is inserted +% between the object and the line above it. Lineskip does not come into +% play unless the first line of the object is high enough to "get too close" +% (as specified by lineskiplimit) to the line before it. The the prevdepth, +% lineskip limit, and lineskip optional parameters are not needed for the +% first object/line on a page (i.e., prevdepth <= -1000pt) where the simplier +% \topskip spacing rules are in effect. +% +% Offset is a manual adjustment that is added to the height calculations of +% object irrespective of the value of \prevdepth. It is useful when the top +% baselineskip will result in a noninteger unit height object placement even +% if the object itself has integral height. e.g., a footnotesize baselineskip +% is used before the object, thus an offset of, say -3pt, can be given as a +% correction. + +% Common combinations of these parameters include: +% +% top baselineskip: (and default values for offset, prevdepth, etc.) +% \topskip % for objects that appear at the top of a page +% \maxdimen % always ignore the height of the top line +% 0pt % always consider any positive height of the top line +% +% for objects to appear inline in normal text: +% top baselineskip = \baselineskip +% +% set prevdepth = -1000pt and top baselineskip = 0pt to consider the +% overall height of the object without any other external skip +% consideration + +\newif\if@IEEEquantizevspacestarform % flag to indicate star form +\newif\if@IEEEquantizevspaceuseoutdimenreg % flag to indicate output dimen register is to be used +% Use our own private registers because the object could contain a +% structure that uses the existing tmp scratch pad registers +\newdimen\@IEEEquantizeheightA +\newdimen\@IEEEquantizeheightB +\newdimen\@IEEEquantizeheightC +\newdimen\@IEEEquantizeprevdepth % need to save this early as can change +\newcount\@IEEEquantizemultiple +\newbox\@IEEEquantizeboxA + + +\def\@IEEEquantizevspace{\@ifnextchar [{\@IEEEquantizevspaceuseoutdimenregtrue\@@IEEEquantizevspace}{\@IEEEquantizevspaceuseoutdimenregfalse\@@IEEEquantizevspace[]}} + + +\long\def\@@IEEEquantizevspace[#1]#2{\relax +% acquire and store +% #1 optional output dimen register +% #2 object +\edef\@IEEEquantizeoutdimenreg{#1}\relax +% allow for object specifications that contain parameters +\@IEEEtrantmptoksA={#2}\relax +\long\edef\@IEEEquantizeobject{\the\@IEEEtrantmptoksA}\relax +\@ifnextchar [{\@@@IEEEquantizevspace}{\@@@IEEEquantizevspace[\relax]}} + +\long\def\@@@IEEEquantizevspace[#1]#2{\relax +% acquire and store +% [#1] optional object decl, is \relax if not given by user +% #2 top baselineskip +% allow for object decl specifications that have parameters +\@IEEEtrantmptoksA={#1}\relax +\long\edef\@IEEEquantizeobjectdecl{\the\@IEEEtrantmptoksA}\relax +\edef\@IEEEquantizetopbaselineskip{#2}\ivIEEEquantizevspace} + +% acquire optional argument set and store +% [offset][prevdepth][lineskip limit][lineskip] +\def\ivIEEEquantizevspace{\@ifnextchar [{\@vIEEEquantizevspace}{\@vIEEEquantizevspace[0pt]}} +\def\@vIEEEquantizevspace[#1]{\edef\@IEEEquantizeoffset{#1}\@ifnextchar [{\@viIEEEquantizevspace}{\@viIEEEquantizevspace[\prevdepth]}} +\def\@viIEEEquantizevspace[#1]{\@IEEEquantizeprevdepth=#1\relax\@ifnextchar [{\@viiIEEEquantizevspace}{\@viiIEEEquantizevspace[\lineskiplimit]}} +\def\@viiIEEEquantizevspace[#1]{\edef\@IEEEquantizelineskiplimit{#1}\@ifnextchar [{\@viiiIEEEquantizevspace}{\@viiiIEEEquantizevspace[\lineskip]}} +\def\@viiiIEEEquantizevspace[#1]{\edef\@IEEEquantizelineskip{#1}\@ixIEEEquantizevspace} + +% main routine +\def\@ixIEEEquantizevspace#1#2#3{\relax +\edef\@IEEEquantizeunitheight{#1}\relax +\edef\@IEEEquantizenomvspace{#2}\relax +\edef\@IEEEquantizeminvspace{#3}\relax +% \@IEEEquantizeoutdimenreg +% \@IEEEquantizeobject +% \@IEEEquantizeobjectdecl +% \@IEEEquantizetopbaselineskip +% \@IEEEquantizeoffset +% \@IEEEquantizeprevdepth +% \@IEEEquantizelineskiplimit +% \@IEEEquantizelineskip +% \@IEEEquantizeunitheight +% \@IEEEquantizenomvspace +% \@IEEEquantizeminvspace +% get overall height of object +\setbox\@IEEEquantizeboxA\vbox{\begingroup\@IEEEquantizeobjectdecl\@IEEEquantizeobject\relax\endgroup}\relax +\@IEEEquantizeheightA\ht\@IEEEquantizeboxA\relax +% get height of first line of object +\setbox\@IEEEquantizeboxA\vtop{\begingroup\@IEEEquantizeobjectdecl\@IEEEquantizeobject\relax\endgroup}\relax +\@IEEEquantizeheightB\ht\@IEEEquantizeboxA\relax +\ifdim\@IEEEquantizeprevdepth>-1000pt\relax % prevdepth > -1000pf means full baselineskip\lineskip rules in effect +% lineskip spacing rule takes effect if height of top line > baselineskip - prevdepth - lineskiplimit, +% otherwise the baselineskip rule is in effect and the height of the first line does not matter at all. +\@IEEEquantizeheightC=\@IEEEquantizetopbaselineskip\relax +\advance\@IEEEquantizeheightC-\@IEEEquantizeprevdepth\relax +\advance\@IEEEquantizeheightC-\@IEEEquantizelineskiplimit\relax % this works even though \@IEEEquantizelineskiplimit is a macro because TeX allows --10pt notation +\ifdim\@IEEEquantizeheightB>\@IEEEquantizeheightC\relax +% lineskip spacing rule is in effect i.e., the object is going to be shifted down relative to the +% baselineskip set position by its top line height (already a part of the total height) + prevdepth + lineskip - baselineskip +\advance\@IEEEquantizeheightA\@IEEEquantizeprevdepth\relax +\advance\@IEEEquantizeheightA\@IEEEquantizelineskip\relax +\advance\@IEEEquantizeheightA-\@IEEEquantizetopbaselineskip\relax +\else +% height of first line <= \@IEEEquantizetopbaselineskip - \@IEEEquantizeprevdepth - \@IEEEquantizelineskiplimit +% standard baselineskip rules are in effect, so don't consider height of first line +\advance\@IEEEquantizeheightA-\@IEEEquantizeheightB\relax +\fi +% +\else % prevdepth <= -1000pt, simplier \topskip type rules in effect +\ifdim\@IEEEquantizeheightB>\@IEEEquantizetopbaselineskip +% height of top line (already included in the total height) in excess of +% baselineskip is the amount it will be downshifted +\advance\@IEEEquantizeheightA-\@IEEEquantizetopbaselineskip\relax +\else +% height of first line is irrelevant, remove it +\advance\@IEEEquantizeheightA-\@IEEEquantizeheightB\relax +\fi +\fi % prevdepth <= -1000pt +% +% adjust height for any manual offset +\advance\@IEEEquantizeheightA\@IEEEquantizeoffset\relax +% add in nominal spacer +\advance\@IEEEquantizeheightA\@IEEEquantizenomvspace\relax +% check for nonzero unitheight +\@IEEEquantizeheightB=\@IEEEquantizeunitheight\relax +\ifnum\@IEEEquantizeheightB=0\relax +\@IEEEclspkgerror{IEEEquantizevspace unit height cannot be zero. Assuming 10pt.}% +{Division by zero is not allowed.} +\@IEEEquantizeheightB=10pt\relax +\fi +% get integer number of lines +\@IEEEquantizemultiple=\@IEEEquantizeheightA\relax +\divide\@IEEEquantizemultiple\@IEEEquantizeheightB\relax +% set A to contain the excess height over the \@IEEEquantizemultiple of lines +% A = height - multiple*unitheight +\@IEEEquantizeheightC\@IEEEquantizeheightB\relax +\multiply\@IEEEquantizeheightC\@IEEEquantizemultiple\relax +\advance\@IEEEquantizeheightA-\@IEEEquantizeheightC\relax +% set B to contain the height short of \@IEEEquantizemultiple+1 of lines +% B = unitheight - A +\advance\@IEEEquantizeheightB-\@IEEEquantizeheightA\relax +% choose A or B based on which is closer +\@IEEEquantizeheightC\@IEEEquantizenomvspace\relax +\ifdim\@IEEEquantizeheightA<\@IEEEquantizeheightB\relax +% C = nomvspace - A, go with lower +\advance\@IEEEquantizeheightC-\@IEEEquantizeheightA\relax +\else +% C = nomvspace + B, go with upper +\advance\@IEEEquantizeheightC\@IEEEquantizeheightB\relax +\fi +% if violate lower bound, use next integer bound +\ifdim\@IEEEquantizeheightC<\@IEEEquantizeminvspace\relax +% A + B = unitheight +\advance\@IEEEquantizeheightC\@IEEEquantizeheightA\relax +\advance\@IEEEquantizeheightC\@IEEEquantizeheightB\relax +\fi +% export object and spacer outside of group +\global\let\@IEEEquantizeobjectout\@IEEEquantizeobject\relax +\global\@IEEEquantizeheightC\@IEEEquantizeheightC\relax +\endgroup +\if@IEEEquantizevspaceuseoutdimenreg +\@IEEEquantizeoutdimenreg=\@IEEEquantizeheightC\relax +\else +\@IEEEquantizeobjectout\relax +\vskip\@IEEEquantizeheightC\relax +\fi} + + +% user command to disable all global assignments, possible use within object decl +\def\IEEEquantizedisableglobal{\let\global\relax +\let\gdef\def +\let\xdef\edef} +% user command to allow for the disabling of \thanks and other commands, possible use within object decl +\def\IEEEquantizedisabletitlecmds{\long\def\thanks##1{\relax}\relax +\long\def\IEEEcompsocitemizethanks##1{\relax}\def\newpage{\relax}} + + + + + +% V1.6 +% we allow the user access to the last part of the title area +% useful in emergencies such as when a different spacing is needed +% This text is NOT compensated for in the dynamic sizer. +\let\@IEEEaftertitletext=\relax +\long\def\IEEEaftertitletext#1{\def\@IEEEaftertitletext{#1}} + + +% V1.7 provide a way for users to enter abstract and keywords +% into the onecolumn title are. This text is compensated for +% in the dynamic sizer. +\let\@IEEEtitleabstractindextext=\relax +\long\def\IEEEtitleabstractindextext#1{\def\@IEEEtitleabstractindextext{#1}} + +% V1.7 provide a way for users to get the \@IEEEtitleabstractindextext if +% not in compsoc or transmag journal mode - this way abstract and keywords +% can still be placed in their conventional position if not in those modes. +\def\IEEEdisplaynontitleabstractindextext{% +% display for all conference formats +\ifCLASSOPTIONconference\@IEEEtitleabstractindextext\relax +\else% non-conferences + % V1.8a display for all technotes + \ifCLASSOPTIONtechnote\@IEEEtitleabstractindextext\relax + % V1.8a add diamond line after abstract and index terms for compsoc technotes + \@IEEEcompsoconly{\noindent\hfill\IEEEcompsocdiamondline\hfill\hbox{}\par}\relax + \else % non-conferences and non-technotes + \ifCLASSOPTIONcompsoc% display if not compsoc and not transmag + \else + \ifCLASSOPTIONtransmag + \else% not compsoc journal nor transmag journal + \@IEEEtitleabstractindextext\relax + \fi + \fi + \fi +\fi} + + +% command to allow alteration of baselinestretch, but only if the current +% baselineskip is unity. Used to tweak the compsoc abstract and keywords line spacing. +\def\@IEEEtweakunitybaselinestretch#1{{\def\baselinestretch{1}\selectfont +\global\@tempskipa\baselineskip}\ifnum\@tempskipa=\baselineskip% +\def\baselinestretch{#1}\selectfont\fi\relax} + + +% abstract and keywords are in \small, except +% for 9pt docs in which they are in \footnotesize +% Because 9pt docs use an 8pt footnotesize, \small +% becomes a rather awkward 8.5pt +\def\@IEEEabskeysecsize{\small} +\ifx\CLASSOPTIONpt\@IEEEptsizenine + \def\@IEEEabskeysecsize{\footnotesize} +\fi + +% compsoc journals use \footnotesize, compsoc conferences use normalsize +\@IEEEcompsoconly{\def\@IEEEabskeysecsize{\footnotesize}} +\@IEEEcompsocconfonly{\def\@IEEEabskeysecsize{\small}} + + +% V1.6 have abstract and keywords strip leading spaces, pars and newlines +% so that spacing is more tightly controlled. +\def\abstract{\normalfont + \if@twocolumn + \@IEEEabskeysecsize\bfseries\textit{\abstractname}---\relax + \else + \bgroup\par\addvspace{0.5\baselineskip}\centering\vspace{-1.78ex}\@IEEEabskeysecsize\textbf{\abstractname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize + \fi\@IEEEgobbleleadPARNLSP} +% V1.6 The IEEE wants only 1 pica from end of abstract to introduction heading when in +% conference mode (the heading already has this much above it) +\def\endabstract{\relax\ifCLASSOPTIONconference\vspace{0ex}\else\vspace{1.34ex}\fi\par\if@twocolumn\else\endquotation\fi + \normalfont\normalsize} + +\def\IEEEkeywords{\normalfont + \if@twocolumn + \@IEEEabskeysecsize\bfseries\textit{\IEEEkeywordsname}---\relax + \else + \bgroup\par\addvspace{0.5\baselineskip}\centering\@IEEEabskeysecsize\textbf{\IEEEkeywordsname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize + \fi\@IEEEgobbleleadPARNLSP} +\def\endIEEEkeywords{\relax\ifCLASSOPTIONtechnote\vspace{1.34ex}\else\vspace{0.67ex}\fi + \par\if@twocolumn\else\endquotation\fi% + \normalfont\normalsize} + +% V1.7 compsoc keywords index terms +\ifCLASSOPTIONcompsoc + \ifCLASSOPTIONconference% compsoc conference +\def\abstract{\normalfont\@IEEEtweakunitybaselinestretch{1.15}\bfseries + \if@twocolumn + \@IEEEabskeysecsize\noindent\textit{\abstractname}---\relax + \else + \bgroup\par\addvspace{0.5\baselineskip}\centering\vspace{-1.78ex}\@IEEEabskeysecsize\textbf{\abstractname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize% + \fi\@IEEEgobbleleadPARNLSP} +\def\IEEEkeywords{\normalfont\@IEEEtweakunitybaselinestretch{1.15}\bfseries + \if@twocolumn + \@IEEEabskeysecsize\vskip 0.5\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip\noindent + \textit{\IEEEkeywordsname}---\relax + \else + \bgroup\par\addvspace{0.5\baselineskip}\centering\@IEEEabskeysecsize\textbf{\IEEEkeywordsname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize% + \fi\@IEEEgobbleleadPARNLSP} + \else% compsoc not conference +\def\abstract{\normalfont\@IEEEtweakunitybaselinestretch{1.15}\sffamily + \if@twocolumn + \@IEEEabskeysecsize\noindent\textbf{\abstractname}---\relax + \else + \bgroup\par\addvspace{0.5\baselineskip}\centering\vspace{-1.78ex}\@IEEEabskeysecsize\textbf{\abstractname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize% + \fi\@IEEEgobbleleadPARNLSP} +\def\IEEEkeywords{\normalfont\@IEEEtweakunitybaselinestretch{1.15}\sffamily + \if@twocolumn + \@IEEEabskeysecsize\vskip 0.5\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip\noindent + \textbf{\IEEEkeywordsname}---\relax + \else + \bgroup\par\addvspace{0.5\baselineskip}\centering\@IEEEabskeysecsize\textbf{\IEEEkeywordsname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize% + \fi\@IEEEgobbleleadPARNLSP} + \fi +\fi + +% V1.8 transmag keywords index terms +% no abstract name, use indentation +\ifCLASSOPTIONtransmag +\def\abstract{\normalfont\parindent 1em\relax + \if@twocolumn + \@IEEEabskeysecsize\bfseries\indent + \else + \bgroup\par\addvspace{0.5\baselineskip}\centering\vspace{-1.78ex}\@IEEEabskeysecsize + \textbf{\abstractname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize + \fi\@IEEEgobbleleadPARNLSP} + +\def\IEEEkeywords{\normalfont\parindent 1em\relax + \if@twocolumn + \@IEEEabskeysecsize\vspace{1\baselineskip}\bfseries\indent\textit{\IEEEkeywordsname}---\relax + \else + \bgroup\par\vspace{1\baselineskip}\centering\@IEEEabskeysecsize + \textbf{\IEEEkeywordsname}\par\addvspace{0.5\baselineskip}\egroup\quotation\@IEEEabskeysecsize + \fi\@IEEEgobbleleadPARNLSP} +\fi + + + +% gobbles all leading \, \\ and \par, upon finding first token that +% is not a \ , \\ or a \par, it ceases and returns that token +% +% used to strip leading \, \\ and \par from the input +% so that such things in the beginning of an environment will not +% affect the formatting of the text +\long\def\@IEEEgobbleleadPARNLSP#1{\let\@IEEEswallowthistoken=0% +\let\@IEEEgobbleleadPARNLSPtoken#1% +\let\@IEEEgobbleleadPARtoken=\par% +\let\@IEEEgobbleleadNLtoken=\\% +\let\@IEEEgobbleleadSPtoken=\ % +\def\@IEEEgobbleleadSPMACRO{\ }% +\ifx\@IEEEgobbleleadPARNLSPtoken\@IEEEgobbleleadPARtoken% +\let\@IEEEswallowthistoken=1% +\fi% +\ifx\@IEEEgobbleleadPARNLSPtoken\@IEEEgobbleleadNLtoken% +\let\@IEEEswallowthistoken=1% +\fi% +\ifx\@IEEEgobbleleadPARNLSPtoken\@IEEEgobbleleadSPtoken% +\let\@IEEEswallowthistoken=1% +\fi% +% a control space will come in as a macro +% when it is the last one on a line +\ifx\@IEEEgobbleleadPARNLSPtoken\@IEEEgobbleleadSPMACRO% +\let\@IEEEswallowthistoken=1% +\fi% +% if we have to swallow this token, do so and taste the next one +% else spit it out and stop gobbling +\ifx\@IEEEswallowthistoken 1\let\@IEEEnextgobbleleadPARNLSP=\@IEEEgobbleleadPARNLSP\else% +\let\@IEEEnextgobbleleadPARNLSP=#1\fi% +\@IEEEnextgobbleleadPARNLSP}% + + + + +% TITLING OF SECTIONS +\def\@IEEEsectpunct{:\ \,} % Punctuation after run-in section heading (headings which are + % part of the paragraphs), need little bit more than a single space + % spacing from section number to title +% compsoc conferences use regular period/space punctuation +\ifCLASSOPTIONcompsoc +\ifCLASSOPTIONconference +\def\@IEEEsectpunct{.\ } +\fi\fi + + +\def\@seccntformat#1{\csname the#1dis\endcsname\hskip 0.5em\relax} + +\ifCLASSOPTIONcompsoc +% compsoc journals need extra spacing +\ifCLASSOPTIONconference\else +\def\@seccntformat#1{\csname the#1dis\endcsname\hskip 1em\relax} +\fi\fi + +%v1.7 put {} after #6 to allow for some types of user font control +%and use \@@par rather than \par +\def\@sect#1#2#3#4#5#6[#7]#8{% + \ifnum #2>\c@secnumdepth + \let\@svsec\@empty + \else + \refstepcounter{#1}% + % load section label and spacer into \@svsec + \protected@edef\@svsec{\@seccntformat{#1}\relax}% + \fi% + \@tempskipa #5\relax + \ifdim \@tempskipa>\z@% tempskipa determines whether is treated as a high + \begingroup #6{\relax% or low level heading + \noindent % subsections are NOT indented + % print top level headings. \@svsec is label, #8 is heading title + % The IEEE does not block indent the section title text, it flows like normal + {\hskip #3\relax\@svsec}{\interlinepenalty \@M #8\@@par}}% + \endgroup + \addcontentsline{toc}{#1}{\ifnum #2>\c@secnumdepth\relax\else + \protect\numberline{\csname the#1\endcsname}\fi#7}% + \else % printout low level headings + % svsechd seems to swallow the trailing space, protect it with \mbox{} + % got rid of sectionmark stuff + \def\@svsechd{#6{\hskip #3\relax\@svsec #8\@IEEEsectpunct\mbox{}}% + \addcontentsline{toc}{#1}{\ifnum #2>\c@secnumdepth\relax\else + \protect\numberline{\csname the#1\endcsname}\fi#7}}% + \fi%skip down + \@xsect{#5}} + + +% section* handler +%v1.7 put {} after #4 to allow for some types of user font control +%and use \@@par rather than \par +\def\@ssect#1#2#3#4#5{\@tempskipa #3\relax + \ifdim \@tempskipa>\z@ + %\begingroup #4\@hangfrom{\hskip #1}{\interlinepenalty \@M #5\par}\endgroup + % The IEEE does not block indent the section title text, it flows like normal + \begingroup \noindent #4{\relax{\hskip #1}{\interlinepenalty \@M #5\@@par}}\endgroup + % svsechd swallows the trailing space, protect it with \mbox{} + \else \def\@svsechd{#4{\hskip #1\relax #5\@IEEEsectpunct\mbox{}}}\fi + \@xsect{#3}} + + +%% SECTION heading spacing and font +%% +% arguments are: #1 - sectiontype name +% (for \@sect) #2 - section level +% #3 - section heading indent +% #4 - top separation (absolute value used, neg indicates not to indent main text) +% If negative, make stretch parts negative too! +% #5 - (absolute value used) positive: bottom separation after heading, +% negative: amount to indent main text after heading +% Both #4 and #5 negative means to indent main text and use negative top separation +% #6 - font control +% You've got to have \normalfont\normalsize in the font specs below to prevent +% trouble when you do something like: +% \section{Note}{\ttfamily TT-TEXT} is known to ... +% The IEEE sometimes REALLY stretches the area before a section +% heading by up to about 0.5in. However, it may not be a good +% idea to let LaTeX have quite this much rubber. +\ifCLASSOPTIONconference% +% The IEEE wants section heading spacing to decrease for conference mode +\def\section{\@startsection{section}{1}{\z@}{1.5ex plus 1.5ex minus 0.5ex}% +{0.7ex plus 1ex minus 0ex}{\normalfont\normalsize\centering\scshape}}% +\def\subsection{\@startsection{subsection}{2}{\z@}{1.5ex plus 1.5ex minus 0.5ex}% +{0.7ex plus .5ex minus 0ex}{\normalfont\normalsize\itshape}}% +\else % for journals +\def\section{\@startsection{section}{1}{\z@}{3.0ex plus 1.5ex minus 1.5ex}% V1.6 3.0ex from 3.5ex +{0.7ex plus 1ex minus 0ex}{\normalfont\normalsize\centering\scshape}}% +\def\subsection{\@startsection{subsection}{2}{\z@}{3.5ex plus 1.5ex minus 1.5ex}% +{0.7ex plus .5ex minus 0ex}{\normalfont\normalsize\itshape}}% +\fi + +% for both journals and conferences +% decided to put in a little rubber above the section, might help somebody +\def\subsubsection{\@startsection{subsubsection}{3}{\parindent}{0ex plus 0.1ex minus 0.1ex}% +{0ex}{\normalfont\normalsize\itshape}}% +\def\paragraph{\@startsection{paragraph}{4}{2\parindent}{0ex plus 0.1ex minus 0.1ex}% +{0ex}{\normalfont\normalsize\itshape}}% + + +% compsoc +\ifCLASSOPTIONcompsoc +\ifCLASSOPTIONconference +% compsoc conference +\def\section{\@startsection{section}{1}{\z@}{1\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip}% +{1\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip}{\normalfont\large\bfseries}}% +\def\subsection{\@startsection{subsection}{2}{\z@}{1\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip}% +{1\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip}{\normalfont\sublargesize\bfseries}}% +\def\subsubsection{\@startsection{subsubsection}{3}{\z@}{1\baselineskip plus 0.25\baselineskip minus 0.25\baselineskip}% +{0ex}{\normalfont\normalsize\bfseries}}% +\def\paragraph{\@startsection{paragraph}{4}{2\parindent}{0ex plus 0.1ex minus 0.1ex}% +{0ex}{\normalfont\normalsize}}% +\else% compsoc journals +% use negative top separation as compsoc journals do not indent paragraphs after section titles +\def\section{\@startsection{section}{1}{\z@}{-3.5ex plus -2ex minus -1.5ex}% +{0.7ex plus 1ex minus 0ex}{\normalfont\sublargesize\sffamily\bfseries\scshape}}% +% Note that subsection and smaller may not be correct for the Computer Society, +% I have to look up an example. +\def\subsection{\@startsection{subsection}{2}{\z@}{-3.5ex plus -1.5ex minus -1.5ex}% +{0.7ex plus .5ex minus 0ex}{\normalfont\normalsize\sffamily\bfseries}}% +\def\subsubsection{\@startsection{subsubsection}{3}{\z@}{-2.5ex plus -1ex minus -1ex}% +{0.5ex plus 0.5ex minus 0ex}{\normalfont\normalsize\sffamily\itshape}}% +\def\paragraph{\@startsection{paragraph}{4}{2\parindent}{-0ex plus -0.1ex minus -0.1ex}% +{0ex}{\normalfont\normalsize}}% +\fi\fi + +% transmag +\ifCLASSOPTIONtransmag +\def\subsection{\@startsection{subsection}{2}{0.75\parindent}{3.5ex plus 1.5ex minus 1.5ex}% +{0.7ex plus .5ex minus 0ex}{\normalfont\normalsize\itshape}}% +\def\subsubsection{\@startsection{subsubsection}{3}{1.25\parindent}{0.1ex plus 0.1ex minus 0.1ex}% +{0.1ex}{\normalfont\normalsize\itshape}}% +\fi + + +% V1.8a provide for a raised line Introduction section for use with Computer +% Society papers. We have to remove any spacing glue after the section +% heading and then remove the blank line for the new paragraph after it. +% LaTeX's section handler alters \everypar and we need to propogate those +% changes outside of the \parbox lest there be spacing problems at the top +% of the next section. +\def\IEEEraisesectionheading#1{\noindent\raisebox{1.5\baselineskip}[0pt][0pt]{\parbox[b]{\columnwidth}{#1\unskip\global\everypar=\everypar}}\vspace{-1\baselineskip}\vspace{-\parskip}\par} + + + +%% ENVIRONMENTS +% "box" symbols at end of proofs +\def\IEEEQEDclosed{\mbox{\rule[0pt]{1.3ex}{1.3ex}}} % for a filled box +% V1.6 some journals use an open box instead that will just fit around a closed one +\def\IEEEQEDopen{{\setlength{\fboxsep}{0pt}\setlength{\fboxrule}{0.2pt}\fbox{\rule[0pt]{0pt}{1.3ex}\rule[0pt]{1.3ex}{0pt}}}} +\ifCLASSOPTIONcompsoc +\def\IEEEQED{\IEEEQEDopen} % default to open for compsoc +\else +\def\IEEEQED{\IEEEQEDclosed} % otherwise default to closed +\fi + +%V1.8 flag to indicate if QED symbol is to be shown +\newif\if@IEEEQEDshow \@IEEEQEDshowtrue +\def\IEEEproofindentspace{2\parindent}% V1.8 allow user to change indentation amount if desired +% v1.7 name change to avoid namespace collision with amsthm. Also add support +% for an optional argument. +\def\IEEEproof{\@ifnextchar[{\@IEEEproof}{\@IEEEproof[\IEEEproofname]}} +\def\@IEEEproof[#1]{\@IEEEQEDshowtrue\par\noindent\hspace{\IEEEproofindentspace}{\itshape #1: }} +\def\endIEEEproof{\if@IEEEQEDshow\hspace*{\fill}\nobreakspace\IEEEQED\fi\par} +% qedhere for equation environments, similar to AMS \qedhere +\def\IEEEQEDhereeqn{\global\@IEEEQEDshowfalse\eqno\let\eqno\relax\let\leqno\relax + \let\veqno\relax\hbox{\IEEEQED}} +% IEEE style qedhere for IEEEeqnarray and other environments +\def\IEEEQEDhere{\global\@IEEEQEDshowfalse\IEEEQED} +% command to disable QED at end of IEEEproof +\def\IEEEQEDoff{\global\@IEEEQEDshowfalse} + + +%\itemindent is set to \z@ by list, so define new temporary variable +\newdimen\@IEEEtmpitemindent + +\ifCLASSOPTIONcompsoc +% V1.8a compsoc uses bold theorem titles, a period instead of a colon, vertical spacing, and hanging indentation +% V1.8 allow long theorem names to break across lines. +% Thanks to Miquel Payaro for reporting this. +\def\@begintheorem#1#2{\@IEEEtmpitemindent\itemindent\relax + \topsep 0.2\@IEEEnormalsizeunitybaselineskip plus 0.26\@IEEEnormalsizeunitybaselineskip minus 0.05\@IEEEnormalsizeunitybaselineskip + \rmfamily\trivlist\hangindent\parindent% + \item[]\textit{\bfseries\noindent #1\ #2.} \itemindent\@IEEEtmpitemindent\relax} +\def\@opargbegintheorem#1#2#3{\@IEEEtmpitemindent\itemindent\relax +\topsep 0.2\@IEEEnormalsizeunitybaselineskip plus 0.26\@IEEEnormalsizeunitybaselineskip minus 0.05\@IEEEnormalsizeunitybaselineskip +\rmfamily\trivlist\hangindent\parindent% +% V1.6 The IEEE is back to using () around theorem names which are also in italics +% Thanks to Christian Peel for reporting this. + \item[]\textit{\bfseries\noindent #1\ #2\ (#3).} \itemindent\@IEEEtmpitemindent\relax} +% V1.7 remove bogus \unskip that caused equations in theorems to collide with +% lines below. +\def\@endtheorem{\endtrivlist\vskip 0.25\@IEEEnormalsizeunitybaselineskip plus 0.26\@IEEEnormalsizeunitybaselineskip minus 0.05\@IEEEnormalsizeunitybaselineskip} +\else +% +% noncompsoc +% +% V1.8 allow long theorem names to break across lines. +% Thanks to Miquel Payaro for reporting this. +\def\@begintheorem#1#2{\@IEEEtmpitemindent\itemindent\relax\topsep 0pt\rmfamily\trivlist% + \item[]\textit{\indent #1\ #2:} \itemindent\@IEEEtmpitemindent\relax} +\def\@opargbegintheorem#1#2#3{\@IEEEtmpitemindent\itemindent\relax\topsep 0pt\rmfamily \trivlist% +% V1.6 The IEEE is back to using () around theorem names which are also in italics +% Thanks to Christian Peel for reporting this. + \item[]\textit{\indent #1\ #2\ (#3):} \itemindent\@IEEEtmpitemindent\relax} +% V1.7 remove bogus \unskip that caused equations in theorems to collide with +% lines below. +\def\@endtheorem{\endtrivlist} +\fi + + + +% V1.6 +% display command for the section the theorem is in - so that \thesection +% is not used as this will be in Roman numerals when we want arabic. +% LaTeX2e uses \def\@thmcounter#1{\noexpand\arabic{#1}} for the theorem number +% (second part) display and \def\@thmcountersep{.} as a separator. +% V1.7 intercept calls to the section counter and reroute to \@IEEEthmcounterinsection +% to allow \appendix(ices} to override as needed. +% +% special handler for sections, allows appendix(ices) to override +\gdef\@IEEEthmcounterinsection#1{\arabic{#1}} +% string macro +\edef\@IEEEstringsection{section} + +% redefine the #1#2[#3] form of newtheorem to use a hook to \@IEEEthmcounterinsection +% if section in_counter is used +\def\@xnthm#1#2[#3]{% + \expandafter\@ifdefinable\csname #1\endcsname + {\@definecounter{#1}\@newctr{#1}[#3]% + \edef\@IEEEstringtmp{#3} + \ifx\@IEEEstringtmp\@IEEEstringsection + \expandafter\xdef\csname the#1\endcsname{% + \noexpand\@IEEEthmcounterinsection{#3}\@thmcountersep + \@thmcounter{#1}}% + \else + \expandafter\xdef\csname the#1\endcsname{% + \expandafter\noexpand\csname the#3\endcsname \@thmcountersep + \@thmcounter{#1}}% + \fi + \global\@namedef{#1}{\@thm{#1}{#2}}% + \global\@namedef{end#1}{\@endtheorem}}} + + + +%% SET UP THE DEFAULT PAGESTYLE +\pagestyle{headings} +\pagenumbering{arabic} + +% normally the page counter starts at 1 +\setcounter{page}{1} +% however, for peerreview the cover sheet is page 0 or page -1 +% (for duplex printing) +\ifCLASSOPTIONpeerreview + \if@twoside + \setcounter{page}{-1} + \else + \setcounter{page}{0} + \fi +\fi + +% standard book class behavior - let bottom line float up and down as +% needed when single sided +\ifCLASSOPTIONtwoside\else\raggedbottom\fi +% if two column - turn on twocolumn, allow word spacings to stretch more and +% enforce a rigid position for the last lines +\ifCLASSOPTIONtwocolumn +% the peer review option delays invoking twocolumn + \ifCLASSOPTIONpeerreview\else + \twocolumn + \fi +\sloppy +\flushbottom +\fi + + + + +% \APPENDIX and \APPENDICES definitions + +% This is the \@ifmtarg command from the LaTeX ifmtarg package +% by Peter Wilson (CUA) and Donald Arseneau +% \@ifmtarg is used to determine if an argument to a command +% is present or not. +% For instance: +% \@ifmtarg{#1}{\typeout{empty}}{\typeout{has something}} +% \@ifmtarg is used with our redefined \section command if +% \appendices is invoked. +% The command \section will behave slightly differently depending +% on whether the user specifies a title: +% \section{My appendix title} +% or not: +% \section{} +% This way, we can eliminate the blank lines where the title +% would be, and the unneeded : after Appendix in the table of +% contents +\begingroup +\catcode`\Q=3 +\long\gdef\@ifmtarg#1{\@xifmtarg#1QQ\@secondoftwo\@firstoftwo\@nil} +\long\gdef\@xifmtarg#1#2Q#3#4#5\@nil{#4} +\endgroup +% end of \@ifmtarg defs + + +% V1.7 +% command that allows the one time saving of the original definition +% of section to \@IEEEappendixsavesection for \appendix or \appendices +% we don't save \section here as it may be redefined later by other +% packages (hyperref.sty, etc.) +\def\@IEEEsaveoriginalsectiononce{\let\@IEEEappendixsavesection\section +\let\@IEEEsaveoriginalsectiononce\relax} + +% neat trick to grab and process the argument from \section{argument} +% we process differently if the user invoked \section{} with no +% argument (title) +% note we reroute the call to the old \section* +\def\@IEEEprocessthesectionargument#1{% +\@ifmtarg{#1}{% +\@IEEEappendixsavesection*{\appendixname\nobreakspace\thesectiondis}% +\addcontentsline{toc}{section}{\appendixname\nobreakspace\thesection}}{% +\@IEEEappendixsavesection*{\appendixname\nobreakspace\thesectiondis\\* #1}% +\addcontentsline{toc}{section}{\appendixname\nobreakspace\thesection: #1}}} + +% we use this if the user calls \section{} after +% \appendix-- which has no meaning. So, we ignore the +% command and its argument. Then, warn the user. +\def\@IEEEdestroythesectionargument#1{\typeout{** WARNING: Ignoring useless +\protect\section\space in Appendix (line \the\inputlineno).}} + + +% remember \thesection forms will be displayed in \ref calls +% and in the Table of Contents. +% The \sectiondis form is used in the actual heading itself + +% appendix command for one single appendix +% normally has no heading. However, if you want a +% heading, you can do so via the optional argument: +% \appendix[Optional Heading] +\def\appendix{\relax} +\renewcommand{\appendix}[1][]{\@IEEEsaveoriginalsectiononce\par + % v1.6 keep hyperref's identifiers unique + \gdef\theHsection{Appendix.A}% + % v1.6 adjust hyperref's string name for the section + \xdef\Hy@chapapp{appendix}% + \setcounter{section}{0}% + \setcounter{subsection}{0}% + \setcounter{subsubsection}{0}% + \setcounter{paragraph}{0}% + \gdef\thesection{A}% + \gdef\thesectiondis{}% + \gdef\thesubsection{\Alph{subsection}}% + \gdef\@IEEEthmcounterinsection##1{A} + \refstepcounter{section}% update the \ref counter + \@ifmtarg{#1}{\@IEEEappendixsavesection*{\appendixname}% + \addcontentsline{toc}{section}{\appendixname}}{% + \@IEEEappendixsavesection*{\appendixname\nobreakspace\\* #1}% + \addcontentsline{toc}{section}{\appendixname: #1}}% + % redefine \section command for appendix + % leave \section* as is + \def\section{\@ifstar{\@IEEEappendixsavesection*}{% + \@IEEEdestroythesectionargument}}% throw out the argument + % of the normal form +} + + + +% appendices command for multiple appendices +% user then calls \section with an argument (possibly empty) to +% declare the individual appendices +\def\appendices{\@IEEEsaveoriginalsectiononce\par + % v1.6 keep hyperref's identifiers unique + \gdef\theHsection{Appendix.\Alph{section}}% + % v1.6 adjust hyperref's string name for the section + \xdef\Hy@chapapp{appendix}% + \setcounter{section}{-1}% we want \refstepcounter to use section 0 + \setcounter{subsection}{0}% + \setcounter{subsubsection}{0}% + \setcounter{paragraph}{0}% + \ifCLASSOPTIONromanappendices% + \gdef\thesection{\Roman{section}}% + \gdef\thesectiondis{\Roman{section}}% + \@IEEEcompsocconfonly{\gdef\thesectiondis{\Roman{section}.}}% + \gdef\@IEEEthmcounterinsection##1{A\arabic{##1}} + \else% + \gdef\thesection{\Alph{section}}% + \gdef\thesectiondis{\Alph{section}}% + \@IEEEcompsocconfonly{\gdef\thesectiondis{\Alph{section}.}}% + \gdef\@IEEEthmcounterinsection##1{\Alph{##1}} + \fi% + \refstepcounter{section}% update the \ref counter + \setcounter{section}{0}% NEXT \section will be the FIRST appendix + % redefine \section command for appendices + % leave \section* as is + \def\section{\@ifstar{\@IEEEappendixsavesection*}{% process the *-form + \refstepcounter{section}% or is a new section so, + \@IEEEprocessthesectionargument}}% process the argument + % of the normal form +} + + + +% V1.7 compoc uses nonbold drop cap and small caps word style +\ifCLASSOPTIONcompsoc + \def\IEEEPARstartFONTSTYLE{\mdseries} + \def\IEEEPARstartWORDFONTSTYLE{\scshape} + \def\IEEEPARstartWORDCAPSTYLE{\relax} +\fi +% +% +% \IEEEPARstart +% Definition for the big two line drop cap letter at the beginning of the +% first paragraph of journal papers. The first argument is the first letter +% of the first word, the second argument is the remaining letters of the +% first word which will be rendered in upper case. +% In V1.6 this has been completely rewritten to: +% +% 1. no longer have problems when the user begins an environment +% within the paragraph that uses \IEEEPARstart. +% 2. auto-detect and use the current font family +% 3. revise handling of the space at the end of the first word so that +% interword glue will now work as normal. +% 4. produce correctly aligned edges for the (two) indented lines. +% +% We generalize things via control macros - playing with these is fun too. +% +% V1.7 added more control macros to make it easy for IEEEtrantools.sty users +% to change the font style. +% +% the number of lines that are indented to clear it +% may need to increase if using decenders +\providecommand{\IEEEPARstartDROPLINES}{2} +% minimum number of lines left on a page to allow a \@IEEEPARstart +% Does not take into consideration rubber shrink, so it tends to +% be overly cautious +\providecommand{\IEEEPARstartMINPAGELINES}{2} +% V1.7 the height of the drop cap is adjusted to match the height of this text +% in the current font (when \IEEEPARstart is called). +\providecommand{\IEEEPARstartHEIGHTTEXT}{T} +% the depth the letter is lowered below the baseline +% the height (and size) of the letter is determined by the sum +% of this value and the height of the \IEEEPARstartHEIGHTTEXT in the current +% font. It is a good idea to set this value in terms of the baselineskip +% so that it can respond to changes therein. +\providecommand{\IEEEPARstartDROPDEPTH}{1.1\baselineskip} +% V1.7 the font the drop cap will be rendered in, +% can take zero or one argument. +\providecommand{\IEEEPARstartFONTSTYLE}{\bfseries} +% V1.7 any additional, non-font related commands needed to modify +% the drop cap letter, can take zero or one argument. +\providecommand{\IEEEPARstartCAPSTYLE}{\MakeUppercase} +% V1.7 the font that will be used to render the rest of the word, +% can take zero or one argument. +\providecommand{\IEEEPARstartWORDFONTSTYLE}{\relax} +% V1.7 any additional, non-font related commands needed to modify +% the rest of the word, can take zero or one argument. +\providecommand{\IEEEPARstartWORDCAPSTYLE}{\MakeUppercase} +% This is the horizontal separation distance from the drop letter to the main text. +% Lengths that depend on the font (e.g., ex, em, etc.) will be referenced +% to the font that is active when \IEEEPARstart is called. +\providecommand{\IEEEPARstartSEP}{0.15em} +% V1.7 horizontal offset applied to the left of the drop cap. +\providecommand{\IEEEPARstartHOFFSET}{0em} +% V1.7 Italic correction command applied at the end of the drop cap. +\providecommand{\IEEEPARstartITLCORRECT}{\/} + +% width of the letter output, set globally. Can be used in \IEEEPARstartSEP +% or \IEEEPARstartHOFFSET, but not the height lengths. +\newdimen\IEEEPARstartletwidth +\IEEEPARstartletwidth 0pt\relax + +% definition of \IEEEPARstart +% THIS IS A CONTROLLED SPACING AREA, DO NOT ALLOW SPACES WITHIN THESE LINES +% +% The token \@IEEEPARstartfont will be globally defined after the first use +% of \IEEEPARstart and will be a font command which creates the big letter +% The first argument is the first letter of the first word and the second +% argument is the rest of the first word(s). +\def\IEEEPARstart#1#2{\par{% +% if this page does not have enough space, break it and lets start +% on a new one +\@IEEEtranneedspace{\IEEEPARstartMINPAGELINES\baselineskip}{\relax}% +% V1.7 move this up here in case user uses \textbf for \IEEEPARstartFONTSTYLE +% which uses command \leavevmode which causes an unwanted \indent to be issued +\noindent +% calculate the desired height of the big letter +% it extends from the top of \IEEEPARstartHEIGHTTEXT in the current font +% down to \IEEEPARstartDROPDEPTH below the current baseline +\settoheight{\@IEEEtrantmpdimenA}{\IEEEPARstartHEIGHTTEXT}% +\addtolength{\@IEEEtrantmpdimenA}{\IEEEPARstartDROPDEPTH}% +% extract the name of the current font in bold +% and place it in \@IEEEPARstartFONTNAME +\def\@IEEEPARstartGETFIRSTWORD##1 ##2\relax{##1}% +{\IEEEPARstartFONTSTYLE{\selectfont\edef\@IEEEPARstartFONTNAMESPACE{\fontname\font\space}% +\xdef\@IEEEPARstartFONTNAME{\expandafter\@IEEEPARstartGETFIRSTWORD\@IEEEPARstartFONTNAMESPACE\relax}}}% +% define a font based on this name with a point size equal to the desired +% height of the drop letter +\font\@IEEEPARstartsubfont\@IEEEPARstartFONTNAME\space at \@IEEEtrantmpdimenA\relax% +% save this value as a counter (integer) value (sp points) +\@IEEEtrantmpcountA=\@IEEEtrantmpdimenA% +% now get the height of the actual letter produced by this font size +\settoheight{\@IEEEtrantmpdimenB}{\@IEEEPARstartsubfont\IEEEPARstartCAPSTYLE{#1}}% +% If something bogus happens like the first argument is empty or the +% current font is strange, do not allow a zero height. +\ifdim\@IEEEtrantmpdimenB=0pt\relax% +\typeout{** WARNING: IEEEPARstart drop letter has zero height! (line \the\inputlineno)}% +\typeout{ Forcing the drop letter font size to 10pt.}% +\@IEEEtrantmpdimenB=10pt% +\fi% +% and store it as a counter +\@IEEEtrantmpcountB=\@IEEEtrantmpdimenB% +% Since a font size doesn't exactly correspond to the height of the capital +% letters in that font, the actual height of the letter, \@IEEEtrantmpcountB, +% will be less than that desired, \@IEEEtrantmpcountA +% we need to raise the font size, \@IEEEtrantmpdimenA +% by \@IEEEtrantmpcountA / \@IEEEtrantmpcountB +% But, TeX doesn't have floating point division, so we have to use integer +% division. Hence the use of the counters. +% We need to reduce the denominator so that the loss of the remainder will +% have minimal affect on the accuracy of the result +\divide\@IEEEtrantmpcountB by 200% +\divide\@IEEEtrantmpcountA by \@IEEEtrantmpcountB% +% Then reequalize things when we use TeX's ability to multiply by +% floating point values +\@IEEEtrantmpdimenB=0.005\@IEEEtrantmpdimenA% +\multiply\@IEEEtrantmpdimenB by \@IEEEtrantmpcountA% +% \@IEEEPARstartfont is globaly set to the calculated font of the big letter +% We need to carry this out of the local calculation area to to create the +% big letter. +\global\font\@IEEEPARstartfont\@IEEEPARstartFONTNAME\space at \@IEEEtrantmpdimenB% +% Now set \@IEEEtrantmpdimenA to the width of the big letter +% We need to carry this out of the local calculation area to set the +% hanging indent +\settowidth{\global\@IEEEtrantmpdimenA}{\@IEEEPARstartfont +\IEEEPARstartCAPSTYLE{#1\IEEEPARstartITLCORRECT}}}% +% end of the isolated calculation environment +\global\IEEEPARstartletwidth\@IEEEtrantmpdimenA\relax% +% add in the extra clearance we want +\advance\@IEEEtrantmpdimenA by \IEEEPARstartSEP\relax% +% add in the optional offset +\advance\@IEEEtrantmpdimenA by \IEEEPARstartHOFFSET\relax% +% V1.7 don't allow negative offsets to produce negative hanging indents +\@IEEEtrantmpdimenB\@IEEEtrantmpdimenA +\ifnum\@IEEEtrantmpdimenB < 0 \@IEEEtrantmpdimenB 0pt\fi +% \@IEEEtrantmpdimenA has the width of the big letter plus the +% separation space and \@IEEEPARstartfont is the font we need to use +% Now, we make the letter and issue the hanging indent command +% The letter is placed in a box of zero width and height so that other +% text won't be displaced by it. +\hangindent\@IEEEtrantmpdimenB\hangafter=-\IEEEPARstartDROPLINES% +\makebox[0pt][l]{\hspace{-\@IEEEtrantmpdimenA}% +\raisebox{-\IEEEPARstartDROPDEPTH}[0pt][0pt]{\hspace{\IEEEPARstartHOFFSET}% +\@IEEEPARstartfont\IEEEPARstartCAPSTYLE{#1\IEEEPARstartITLCORRECT}% +\hspace{\IEEEPARstartSEP}}}% +{\IEEEPARstartWORDFONTSTYLE{\IEEEPARstartWORDCAPSTYLE{\selectfont#2}}}} + + + + +% determines if the space remaining on a given page is equal to or greater +% than the specified space of argument one +% if not, execute argument two (only if the remaining space is greater than zero) +% and issue a \newpage +% +% example: \@IEEEtranneedspace{2in}{\vfill} +% +% Does not take into consideration rubber shrinkage, so it tends to +% be overly cautious +% Based on an example posted by Donald Arseneau +% Note this macro uses \@IEEEtrantmpdimenB internally for calculations, +% so DO NOT PASS \@IEEEtrantmpdimenB to this routine +% if you need a dimen register, import with \@IEEEtrantmpdimenA instead +\def\@IEEEtranneedspace#1#2{\penalty-100\begingroup%shield temp variable +\@IEEEtrantmpdimenB\pagegoal\advance\@IEEEtrantmpdimenB-\pagetotal% space left +\ifdim #1>\@IEEEtrantmpdimenB\relax% not enough space left +\ifdim\@IEEEtrantmpdimenB>\z@\relax #2\fi% +\newpage% +\fi\endgroup} + + + +% IEEEbiography ENVIRONMENT +% Allows user to enter biography leaving place for picture (adapts to font size) +% As of V1.5, a new optional argument allows you to have a real graphic! +% V1.5 and later also fixes the "colliding biographies" which could happen when a +% biography's text was shorter than the space for the photo. +% MDS 7/2001 +% V1.6 prevent multiple biographies from making multiple TOC entries +\newif\if@IEEEbiographyTOCentrynotmade +\global\@IEEEbiographyTOCentrynotmadetrue + +% biography counter so hyperref can jump directly to the biographies +% and not just the previous section +\newcounter{IEEEbiography} +\setcounter{IEEEbiography}{0} + +% photo area size +\def\@IEEEBIOphotowidth{1.0in} % width of the biography photo area +\def\@IEEEBIOphotodepth{1.25in} % depth (height) of the biography photo area +% area cleared for photo +\def\@IEEEBIOhangwidth{1.14in} % width cleared for the biography photo area +\def\@IEEEBIOhangdepth{1.25in} % depth cleared for the biography photo area + % actual depth will be a multiple of + % \baselineskip, rounded up +\def\@IEEEBIOskipN{4\baselineskip}% nominal value of the vskip above the biography + +\newenvironment{IEEEbiography}[2][]{\normalfont\@IEEEcompsoconly{\sffamily}\footnotesize% +\unitlength 1in\parskip=0pt\par\parindent 1em\interlinepenalty500% +% we need enough space to support the hanging indent +% the nominal value of the spacer +% and one extra line for good measure +\@IEEEtrantmpdimenA=\@IEEEBIOhangdepth% +\advance\@IEEEtrantmpdimenA by \@IEEEBIOskipN% +\advance\@IEEEtrantmpdimenA by 1\baselineskip% +% if this page does not have enough space, break it and lets start +% with a new one +\@IEEEtranneedspace{\@IEEEtrantmpdimenA}{\relax}% +% nominal spacer can strech, not shrink use 1fil so user can out stretch with \vfill +\vskip \@IEEEBIOskipN plus 1fil minus 0\baselineskip% +% the default box for where the photo goes +\def\@IEEEtempbiographybox{{\setlength{\fboxsep}{0pt}\framebox{% +\begin{minipage}[b][\@IEEEBIOphotodepth][c]{\@IEEEBIOphotowidth}\centering PLACE\\ PHOTO\\ HERE \end{minipage}}}}% +% +% detect if the optional argument was supplied, this requires the +% \@ifmtarg command as defined in the appendix section above +% and if so, override the default box with what they want +\@ifmtarg{#1}{\relax}{\def\@IEEEtempbiographybox{\mbox{\begin{minipage}[b][\@IEEEBIOphotodepth][c]{\@IEEEBIOphotowidth}% +\centering% +#1% +\end{minipage}}}}% end if optional argument supplied +% Make an entry into the table of contents only if we have not done so before +\if@IEEEbiographyTOCentrynotmade% +% link labels to the biography counter so hyperref will jump +% to the biography, not the previous section +\setcounter{IEEEbiography}{-1}% +\refstepcounter{IEEEbiography}% +\addcontentsline{toc}{section}{Biographies}% +\global\@IEEEbiographyTOCentrynotmadefalse% +\fi% +% one more biography +\refstepcounter{IEEEbiography}% +% Make an entry for this name into the table of contents +\addcontentsline{toc}{subsection}{#2}% +% V1.6 properly handle if a new paragraph should occur while the +% hanging indent is still active. Do this by redefining \par so +% that it will not start a new paragraph. (But it will appear to the +% user as if it did.) Also, strip any leading pars, newlines, or spaces. +\let\@IEEEBIOORGparCMD=\par% save the original \par command +\edef\par{\hfil\break\indent}% the new \par will not be a "real" \par +\settoheight{\@IEEEtrantmpdimenA}{\@IEEEtempbiographybox}% get height of biography box +\@IEEEtrantmpdimenB=\@IEEEBIOhangdepth% +\@IEEEtrantmpcountA=\@IEEEtrantmpdimenB% countA has the hang depth +\divide\@IEEEtrantmpcountA by \baselineskip% calculates lines needed to produce the hang depth +\advance\@IEEEtrantmpcountA by 1% ensure we overestimate +% set the hanging indent +\hangindent\@IEEEBIOhangwidth% +\hangafter-\@IEEEtrantmpcountA% +% reference the top of the photo area to the top of a capital T +\settoheight{\@IEEEtrantmpdimenB}{\mbox{T}}% +% set the photo box, give it zero width and height so as not to disturb anything +\noindent\makebox[0pt][l]{\hspace{-\@IEEEBIOhangwidth}\raisebox{\@IEEEtrantmpdimenB}[0pt][0pt]{% +\raisebox{-\@IEEEBIOphotodepth}[0pt][0pt]{\@IEEEtempbiographybox}}}% +% now place the author name and begin the bio text +\noindent\textbf{#2\ }\@IEEEgobbleleadPARNLSP}{\relax\let\par=\@IEEEBIOORGparCMD\par% +% 7/2001 V1.5 detect when the biography text is shorter than the photo area +% and pad the unused area - preventing a collision from the next biography entry +% MDS +\ifnum \prevgraf <\@IEEEtrantmpcountA\relax% detect when the biography text is shorter than the photo + \advance\@IEEEtrantmpcountA by -\prevgraf% calculate how many lines we need to pad + \advance\@IEEEtrantmpcountA by -1\relax% we compensate for the fact that we indented an extra line + \@IEEEtrantmpdimenA=\baselineskip% calculate the length of the padding + \multiply\@IEEEtrantmpdimenA by \@IEEEtrantmpcountA% + \noindent\rule{0pt}{\@IEEEtrantmpdimenA}% insert an invisible support strut +\fi% +\par\normalfont} + + + +% V1.6 +% added biography without a photo environment +\newenvironment{IEEEbiographynophoto}[1]{% +% Make an entry into the table of contents only if we have not done so before +\if@IEEEbiographyTOCentrynotmade% +% link labels to the biography counter so hyperref will jump +% to the biography, not the previous section +\setcounter{IEEEbiography}{-1}% +\refstepcounter{IEEEbiography}% +\addcontentsline{toc}{section}{Biographies}% +\global\@IEEEbiographyTOCentrynotmadefalse% +\fi% +% one more biography +\refstepcounter{IEEEbiography}% +% Make an entry for this name into the table of contents +\addcontentsline{toc}{subsection}{#1}% +\normalfont\@IEEEcompsoconly{\sffamily}\footnotesize\interlinepenalty500% +\vskip 4\baselineskip plus 1fil minus 0\baselineskip% +\parskip=0pt\par% +\noindent\textbf{#1\ }\@IEEEgobbleleadPARNLSP}{\relax\par\normalfont} + + +% provide the user with some old font commands +% got this from article.cls +\DeclareOldFontCommand{\rm}{\normalfont\rmfamily}{\mathrm} +\DeclareOldFontCommand{\sf}{\normalfont\sffamily}{\mathsf} +\DeclareOldFontCommand{\tt}{\normalfont\ttfamily}{\mathtt} +\DeclareOldFontCommand{\bf}{\normalfont\bfseries}{\mathbf} +\DeclareOldFontCommand{\it}{\normalfont\itshape}{\mathit} +\DeclareOldFontCommand{\sl}{\normalfont\slshape}{\@nomath\sl} +\DeclareOldFontCommand{\sc}{\normalfont\scshape}{\@nomath\sc} +\DeclareRobustCommand*\cal{\@fontswitch\relax\mathcal} +\DeclareRobustCommand*\mit{\@fontswitch\relax\mathnormal} + + +% SPECIAL PAPER NOTICE COMMANDS +% +% holds the special notice text +\def\@IEEEspecialpapernotice{\relax} + +% for special papers, like invited papers, the user can do: +% \IEEEspecialpapernotice{(Invited Paper)} before \maketitle +\def\IEEEspecialpapernotice#1{\ifCLASSOPTIONconference% +\def\@IEEEspecialpapernotice{{\sublargesize\textit{#1}\vspace*{1em}}}% +\else% +\def\@IEEEspecialpapernotice{{\\*[1.5ex]\sublargesize\textit{#1}}\vspace*{-2ex}}% +\fi} + + + + +% PUBLISHER ID COMMANDS +% to insert a publisher's ID footer +% V1.6 \IEEEpubid has been changed so that the change in page size and style +% occurs in \maketitle. \IEEEpubid must now be issued prior to \maketitle +% use \IEEEpubidadjcol as before - in the second column of the title page +% These changes allow \maketitle to take the reduced page height into +% consideration when dynamically setting the space between the author +% names and the maintext. +% +% the amount the main text is pulled up to make room for the +% publisher's ID footer +% The IEEE uses about 1.3\baselineskip for journals, +% dynamic title spacing will clean up the fraction +\def\@IEEEpubidpullup{1.3\baselineskip} +\ifCLASSOPTIONtechnote +% for technotes it must be an integer of baselineskip as there can be no +% dynamic title spacing for two column mode technotes (the title is in the +% in first column) and we should maintain an integer number of lines in the +% second column +% There are some examples (such as older issues of "Transactions on +% Information Theory") in which the IEEE really pulls the text off the ID for +% technotes - about 0.55in (or 4\baselineskip). We'll use 2\baselineskip +% and call it even. +\def\@IEEEpubidpullup{2\baselineskip} +\fi + +% V1.7 compsoc does not use a pullup +\ifCLASSOPTIONcompsoc +\def\@IEEEpubidpullup{0pt} +\fi + +% holds the ID text +\def\@IEEEpubid{\relax} + +% flag so \maketitle can tell if \IEEEpubid was called +\newif\if@IEEEusingpubid +\global\@IEEEusingpubidfalse +% issue this command in the page to have the ID at the bottom +% V1.6 use before \maketitle +\def\IEEEpubid#1{\def\@IEEEpubid{#1}\global\@IEEEusingpubidtrue} + + +% command which will pull up (shorten) the column it is executed in +% to make room for the publisher ID. Place in the second column of +% the title page when using \IEEEpubid +% Is smart enough not to do anything when in single column text or +% if the user hasn't called \IEEEpubid +% currently needed in for the second column of a page with the +% publisher ID. If not needed in future releases, please provide this +% command and define it as \relax for backward compatibility +% v1.6b do not allow command to operate if the peer review option has been +% selected because \IEEEpubidadjcol will not be on the cover page. +% V1.7 do nothing if compsoc +\def\IEEEpubidadjcol{\ifCLASSOPTIONcompsoc\else\ifCLASSOPTIONpeerreview\else +\if@twocolumn\if@IEEEusingpubid\enlargethispage{-\@IEEEpubidpullup}\fi\fi\fi\fi} + +% Special thanks to Peter Wilson, Daniel Luecking, and the other +% gurus at comp.text.tex, for helping me to understand how best to +% implement the IEEEpubid command in LaTeX. + + + +%% Lockout some commands under various conditions + +% general purpose bit bucket +\newsavebox{\@IEEEtranrubishbin} + +% flags to prevent multiple warning messages +\newif\if@IEEEWARNthanks +\newif\if@IEEEWARNIEEEPARstart +\newif\if@IEEEWARNIEEEbiography +\newif\if@IEEEWARNIEEEbiographynophoto +\newif\if@IEEEWARNIEEEpubid +\newif\if@IEEEWARNIEEEpubidadjcol +\newif\if@IEEEWARNIEEEmembership +\newif\if@IEEEWARNIEEEaftertitletext +\@IEEEWARNthankstrue +\@IEEEWARNIEEEPARstarttrue +\@IEEEWARNIEEEbiographytrue +\@IEEEWARNIEEEbiographynophototrue +\@IEEEWARNIEEEpubidtrue +\@IEEEWARNIEEEpubidadjcoltrue +\@IEEEWARNIEEEmembershiptrue +\@IEEEWARNIEEEaftertitletexttrue + + +%% Lockout some commands when in various modes, but allow them to be restored if needed +%% +% save commands which might be locked out +% so that the user can later restore them if needed +\let\@IEEESAVECMDthanks\thanks +\let\@IEEESAVECMDIEEEPARstart\IEEEPARstart +\let\@IEEESAVECMDIEEEbiography\IEEEbiography +\let\@IEEESAVECMDendIEEEbiography\endIEEEbiography +\let\@IEEESAVECMDIEEEbiographynophoto\IEEEbiographynophoto +\let\@IEEESAVECMDendIEEEbiographynophoto\endIEEEbiographynophoto +\let\@IEEESAVECMDIEEEpubid\IEEEpubid +\let\@IEEESAVECMDIEEEpubidadjcol\IEEEpubidadjcol +\let\@IEEESAVECMDIEEEmembership\IEEEmembership +\let\@IEEESAVECMDIEEEaftertitletext\IEEEaftertitletext + + +% disable \IEEEPARstart when in draft mode +% This may have originally been done because the pre-V1.6 drop letter +% algorithm had problems with a non-unity baselinestretch +% At any rate, it seems too formal to have a drop letter in a draft +% paper. +\ifCLASSOPTIONdraftcls +\def\IEEEPARstart#1#2{#1#2\if@IEEEWARNIEEEPARstart\typeout{** ATTENTION: \noexpand\IEEEPARstart + is disabled in draft mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEPARstartfalse} +\fi +% and for technotes +\ifCLASSOPTIONtechnote +\def\IEEEPARstart#1#2{#1#2\if@IEEEWARNIEEEPARstart\typeout{** WARNING: \noexpand\IEEEPARstart + is locked out for technotes (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEPARstartfalse} +\fi + + +% lockout unneeded commands when in conference mode +\ifCLASSOPTIONconference +% when locked out, \thanks, \IEEEbiography, \IEEEbiographynophoto, \IEEEpubid, +% \IEEEmembership and \IEEEaftertitletext will all swallow their given text. +% \IEEEPARstart will output a normal character instead +% warn the user about these commands only once to prevent the console screen +% from filling up with redundant messages +\def\thanks#1{\if@IEEEWARNthanks\typeout{** WARNING: \noexpand\thanks + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNthanksfalse} +\def\IEEEPARstart#1#2{#1#2\if@IEEEWARNIEEEPARstart\typeout{** WARNING: \noexpand\IEEEPARstart + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEPARstartfalse} + + +% LaTeX treats environments and commands with optional arguments differently. +% the actual ("internal") command is stored as \\commandname +% (accessed via \csname\string\commandname\endcsname ) +% the "external" command \commandname is a macro with code to determine +% whether or not the optional argument is presented and to provide the +% default if it is absent. So, in order to save and restore such a command +% we would have to save and restore \\commandname as well. But, if LaTeX +% ever changes the way it names the internal names, the trick would break. +% Instead let us just define a new environment so that the internal +% name can be left undisturbed. +\newenvironment{@IEEEbogusbiography}[2][]{\if@IEEEWARNIEEEbiography\typeout{** WARNING: \noexpand\IEEEbiography + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEbiographyfalse% +\setbox\@IEEEtranrubishbin\vbox\bgroup}{\egroup\relax} +% and make biography point to our bogus biography +\let\IEEEbiography=\@IEEEbogusbiography +\let\endIEEEbiography=\end@IEEEbogusbiography + +\renewenvironment{IEEEbiographynophoto}[1]{\if@IEEEWARNIEEEbiographynophoto\typeout{** WARNING: \noexpand\IEEEbiographynophoto + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEbiographynophotofalse% +\setbox\@IEEEtranrubishbin\vbox\bgroup}{\egroup\relax} + +\def\IEEEpubid#1{\if@IEEEWARNIEEEpubid\typeout{** WARNING: \noexpand\IEEEpubid + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEpubidfalse} +\def\IEEEpubidadjcol{\if@IEEEWARNIEEEpubidadjcol\typeout{** WARNING: \noexpand\IEEEpubidadjcol + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEpubidadjcolfalse} +\def\IEEEmembership#1{\if@IEEEWARNIEEEmembership\typeout{** WARNING: \noexpand\IEEEmembership + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEmembershipfalse} +\def\IEEEaftertitletext#1{\if@IEEEWARNIEEEaftertitletext\typeout{** WARNING: \noexpand\IEEEaftertitletext + is locked out when in conference mode (line \the\inputlineno).}\fi\global\@IEEEWARNIEEEaftertitletextfalse} +\fi + + +% provide a way to restore the commands that are locked out +\def\IEEEoverridecommandlockouts{% +\typeout{** ATTENTION: Overriding command lockouts (line \the\inputlineno).}% +\let\thanks\@IEEESAVECMDthanks% +\let\IEEEPARstart\@IEEESAVECMDIEEEPARstart% +\let\IEEEbiography\@IEEESAVECMDIEEEbiography% +\let\endIEEEbiography\@IEEESAVECMDendIEEEbiography% +\let\IEEEbiographynophoto\@IEEESAVECMDIEEEbiographynophoto% +\let\endIEEEbiographynophoto\@IEEESAVECMDendIEEEbiographynophoto% +\let\IEEEpubid\@IEEESAVECMDIEEEpubid% +\let\IEEEpubidadjcol\@IEEESAVECMDIEEEpubidadjcol% +\let\IEEEmembership\@IEEESAVECMDIEEEmembership% +\let\IEEEaftertitletext\@IEEESAVECMDIEEEaftertitletext} + + + +% need a backslash character for typeout output +{\catcode`\|=0 \catcode`\\=12 +|xdef|@IEEEbackslash{\}} + + +% hook to allow easy disabling of all legacy warnings +\def\@IEEElegacywarn#1#2{\typeout{** ATTENTION: \@IEEEbackslash #1 is deprecated (line \the\inputlineno). +Use \@IEEEbackslash #2 instead.}} + + +% provide some legacy IEEEtran commands +\def\IEEEcompsoctitleabstractindextext{\@IEEElegacywarn{IEEEcompsoctitleabstractindextext}{IEEEtitleabstractindextext}\IEEEtitleabstractindextext} +\def\IEEEdisplaynotcompsoctitleabstractindextext{\@IEEElegacywarn{IEEEdisplaynotcompsoctitleabstractindextext}{IEEEdisplaynontitleabstractindextext}\IEEEdisplaynontitleabstractindextext} +% provide some legacy IEEEtran environments + + +% V1.8a no more support for these legacy commands +%\def\authorblockA{\@IEEElegacywarn{authorblockA}{IEEEauthorblockA}\IEEEauthorblockA} +%\def\authorblockN{\@IEEElegacywarn{authorblockN}{IEEEauthorblockN}\IEEEauthorblockN} +%\def\authorrefmark{\@IEEElegacywarn{authorrefmark}{IEEEauthorrefmark}\IEEEauthorrefmark} +%\def\PARstart{\@IEEElegacywarn{PARstart}{IEEEPARstart}\IEEEPARstart} +%\def\pubid{\@IEEElegacywarn{pubid}{IEEEpubid}\IEEEpubid} +%\def\pubidadjcol{\@IEEElegacywarn{pubidadjcol}{IEEEpubidadjcol}\IEEEpubidadjcol} +%\def\specialpapernotice{\@IEEElegacywarn{specialpapernotice}{IEEEspecialpapernotice}\IEEEspecialpapernotice} +% and environments +%\def\keywords{\@IEEElegacywarn{keywords}{IEEEkeywords}\IEEEkeywords} +%\def\endkeywords{\endIEEEkeywords} +% V1.8 no more support for legacy IED list commands +%\let\labelindent\IEEElabelindent +%\def\calcleftmargin{\@IEEElegacywarn{calcleftmargin}{IEEEcalcleftmargin}\IEEEcalcleftmargin} +%\def\setlabelwidth{\@IEEElegacywarn{setlabelwidth}{IEEEsetlabelwidth}\IEEEsetlabelwidth} +%\def\usemathlabelsep{\@IEEElegacywarn{usemathlabelsep}{IEEEusemathlabelsep}\IEEEusemathlabelsep} +%\def\iedlabeljustifyc{\@IEEElegacywarn{iedlabeljustifyc}{IEEEiedlabeljustifyc}\IEEEiedlabeljustifyc} +%\def\iedlabeljustifyl{\@IEEElegacywarn{iedlabeljustifyl}{IEEEiedlabeljustifyl}\IEEEiedlabeljustifyl} +%\def\iedlabeljustifyr{\@IEEElegacywarn{iedlabeljustifyr}{IEEEiedlabeljustifyr}\IEEEiedlabeljustifyr} +% V1.8 no more support for QED and proof stuff +%\def\QED{\@IEEElegacywarn{QED}{IEEEQED}\IEEEQED} +%\def\QEDclosed{\@IEEElegacywarn{QEDclosed}{IEEEQEDclosed}\IEEEQEDclosed} +%\def\QEDopen{\@IEEElegacywarn{QEDopen}{IEEEQEDopen}\IEEEQEDopen} +%\AtBeginDocument{\def\proof{\@IEEElegacywarn{proof}{IEEEproof}\IEEEproof}\def\endproof{\endIEEEproof}} +% V1.8 no longer support biography or biographynophoto +%\def\biography{\@IEEElegacywarn{biography}{IEEEbiography}\IEEEbiography} +%\def\biographynophoto{\@IEEElegacywarn{biographynophoto}{IEEEbiographynophoto}\IEEEbiographynophoto} +%\def\endbiography{\endIEEEbiography} +%\def\endbiographynophoto{\endIEEEbiographynophoto} +% V1.7 and later no longer supports \overrideIEEEmargins +%\def\overrideIEEEmargins{% +%\typeout{** WARNING: \string\overrideIEEEmargins \space no longer supported (line \the\inputlineno).}% +%\typeout{** Use the \string\CLASSINPUTinnersidemargin, \string\CLASSINPUToutersidemargin \space controls instead.}} + +\endinput + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% End of IEEEtran.cls %%%%%%%%%%%%%%%%%%%%%%%%%%%% +% That's all folks! + diff --git a/standard/Report/IEEE_report/IEEEtran_HOWTO.pdf b/standard/Report/IEEE_report/IEEEtran_HOWTO.pdf new file mode 100644 index 0000000000000000000000000000000000000000..c8e41daaa36290e7529058ad5c7f4b363d52d801 Binary files /dev/null and b/standard/Report/IEEE_report/IEEEtran_HOWTO.pdf differ diff --git a/standard/Report/IEEE_report/conference_101719.pdf b/standard/Report/IEEE_report/conference_101719.pdf new file mode 100644 index 0000000000000000000000000000000000000000..7bc7647b4954249e07d36335e7ee552595835fbe Binary files /dev/null and b/standard/Report/IEEE_report/conference_101719.pdf differ diff --git a/standard/Report/IEEE_report/fig1.png b/standard/Report/IEEE_report/fig1.png new file mode 100644 index 0000000000000000000000000000000000000000..c45bb5fe5439b40a7c33ff56ebc938c9b9406880 Binary files /dev/null and b/standard/Report/IEEE_report/fig1.png differ diff --git a/standard/Report/IEEE_report/reference.tex b/standard/Report/IEEE_report/reference.tex new file mode 100644 index 0000000000000000000000000000000000000000..967d1315bdb8313f66733ba2512fe2891f926293 --- /dev/null +++ b/standard/Report/IEEE_report/reference.tex @@ -0,0 +1,13 @@ + + +\begin{thebibliography}{01} + \bibitem{a1} S. Kumar, ‘A Review of Different Type of Multipliers and Multiplier-Accumulator Unit.’, vol. 2, no. 4, p. 5, 2013. + + \bibitem{a2} N. Maheshwari, ‘A Design of 4X4 Multiplier using 0.18 um Technology’, International Journal of Latest Trends in Engineering and Technology, vol. 2, no. 1, p. 7, 2013. + \bibitem{a3} M. Krishnamurthy, ‘A. Joseph vijay1, Scholar, Department of’, p. 10. + \bibitem{a4} N. Singh and M. Z. Alam, ‘Design and Implementation of Pipelined 4-Bit Binary Multiplier Using M.G.D.I. Technique’, Management Research, vol. 2, no. 3, p. 7, 2014. + \bibitem{a5} ‘Design of Low Power and High Speed 4X4 Multiplier using Modified Column Bypassing Scheme for DSP Applications’, ijrte, vol. 8, no. 2S3, pp. 643–647, Aug. 2019, doi: 10/gj4nkd. + \bibitem{a6} M. H. Riaz, S. A. Ahmed, Q. Javaid, and T. Kamal, ‘Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder’, in 2018 15th International Bhurban Conference on Applied Sciences and Technology (IBCAST), Islamabad, Jan. 2018, pp. 392–396. doi: 10/gj4nkf. + \bibitem{a7} S. Agwa, E. Yahya, and Y. Ismail, ‘Variability mitigation using correction function technique’, in 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), Abu Dhabi, United Arab Emirates, Dec. 2013, pp. 293–296. doi: 10/gj4nkg. + +\end{thebibliography} \ No newline at end of file diff --git a/standard/Report/IEEE_report/tutorial.tex b/standard/Report/IEEE_report/tutorial.tex new file mode 100644 index 0000000000000000000000000000000000000000..e2022cf2de2a5313c32c81ede4feee3697f7af36 --- /dev/null +++ b/standard/Report/IEEE_report/tutorial.tex @@ -0,0 +1,214 @@ +\section{Ease of Use} + +\subsection{Maintaining the Integrity of the Specifications} + +The IEEEtran class file is used to format your paper and style the text. All margins, +column widths, line spaces, and text fonts are prescribed; please do not +alter them. You may note peculiarities. For example, the head margin +measures proportionately more than is customary. This measurement +and others are deliberate, using specifications that anticipate your paper +as one part of the entire proceedings, and not as an independent document. +Please do not revise any of the current designations. + +\section{Prepare Your Paper Before Styling} +Before you begin to format your paper, first write and save the content as a +separate text file. Complete all content and organizational editing before +formatting. Please note sections \ref{AA}--\ref{SCM} below for more information on +proofreading, spelling and grammar. + +Keep your text and graphic files separate until after the text has been +formatted and styled. Do not number text heads---{\LaTeX} will do that +for you. + +\subsection{Abbreviations and Acronyms}\label{AA} +Define abbreviations and acronyms the first time they are used in the text, +even after they have been defined in the abstract. Abbreviations such as +IEEE, SI, MKS, CGS, ac, dc, and rms do not have to be defined. Do not use +abbreviations in the title or heads unless they are unavoidable. + +\subsection{Units} +\begin{itemize} +\item Use either SI (MKS) or CGS as primary units. (SI units are encouraged.) English units may be used as secondary units (in parentheses). An exception would be the use of English units as identifiers in trade, such as ``3.5-inch disk drive''. +\item Avoid combining SI and CGS units, such as current in amperes and magnetic field in oersteds. This often leads to confusion because equations do not balance dimensionally. If you must use mixed units, clearly state the units for each quantity that you use in an equation. +\item Do not mix complete spellings and abbreviations of units: ``Wb/m\textsuperscript{2}'' or ``webers per square meter'', not ``webers/m\textsuperscript{2}''. Spell out units when they appear in text: ``. . . a few henries'', not ``. . . a few H''. +\item Use a zero before decimal points: ``0.25'', not ``.25''. Use ``cm\textsuperscript{3}'', not ``cc''.) +\end{itemize} + +\subsection{Equations} +Number equations consecutively. To make your +equations more compact, you may use the solidus (~/~), the exp function, or +appropriate exponents. Italicize Roman symbols for quantities and variables, +but not Greek symbols. Use a long dash rather than a hyphen for a minus +sign. Punctuate equations with commas or periods when they are part of a +sentence, as in: +\begin{equation} +a+b=\gamma\label{eq} +\end{equation} + +Be sure that the +symbols in your equation have been defined before or immediately following +the equation. Use ``\eqref{eq}'', not ``Eq.~\eqref{eq}'' or ``equation \eqref{eq}'', except at +the beginning of a sentence: ``Equation \eqref{eq} is . . .'' + +\subsection{\LaTeX-Specific Advice} + +Please use ``soft'' (e.g., \verb|\eqref{Eq}|) cross references instead +of ``hard'' references (e.g., \verb|(1)|). That will make it possible +to combine sections, add equations, or change the order of figures or +citations without having to go through the file line by line. + +Please don't use the \verb|{eqnarray}| equation environment. Use +\verb|{align}| or \verb|{IEEEeqnarray}| instead. The \verb|{eqnarray}| +environment leaves unsightly spaces around relation symbols. + +Please note that the \verb|{subequations}| environment in {\LaTeX} +will increment the main equation counter even when there are no +equation numbers displayed. If you forget that, you might write an +article in which the equation numbers skip from (17) to (20), causing +the copy editors to wonder if you've discovered a new method of +counting. + +{\BibTeX} does not work by magic. It doesn't get the bibliographic +data from thin air but from .bib files. If you use {\BibTeX} to produce a +bibliography you must send the .bib files. + +{\LaTeX} can't read your mind. If you assign the same label to a +subsubsection and a table, you might find that Table I has been cross +referenced as Table IV-B3. + +{\LaTeX} does not have precognitive abilities. If you put a +\verb|\label| command before the command that updates the counter it's +supposed to be using, the label will pick up the last counter to be +cross referenced instead. In particular, a \verb|\label| command +should not go before the caption of a figure or a table. + +Do not use \verb|\nonumber| inside the \verb|{array}| environment. It +will not stop equation numbers inside \verb|{array}| (there won't be +any anyway) and it might stop a wanted equation number in the +surrounding equation. + +\subsection{Some Common Mistakes}\label{SCM} +\begin{itemize} +\item The word ``data'' is plural, not singular. +\item The subscript for the permeability of vacuum $\mu_{0}$, and other common scientific constants, is zero with subscript formatting, not a lowercase letter ``o''. +\item In American English, commas, semicolons, periods, question and exclamation marks are located within quotation marks only when a complete thought or name is cited, such as a title or full quotation. When quotation marks are used, instead of a bold or italic typeface, to highlight a word or phrase, punctuation should appear outside of the quotation marks. A parenthetical phrase or statement at the end of a sentence is punctuated outside of the closing parenthesis (like this). (A parenthetical sentence is punctuated within the parentheses.) +\item A graph within a graph is an ``inset'', not an ``insert''. The word alternatively is preferred to the word ``alternately'' (unless you really mean something that alternates). +\item Do not use the word ``essentially'' to mean ``approximately'' or ``effectively''. +\item In your paper title, if the words ``that uses'' can accurately replace the word ``using'', capitalize the ``u''; if not, keep using lower-cased. +\item Be aware of the different meanings of the homophones ``affect'' and ``effect'', ``complement'' and ``compliment'', ``discreet'' and ``discrete'', ``principal'' and ``principle''. +\item Do not confuse ``imply'' and ``infer''. +\item The prefix ``non'' is not a word; it should be joined to the word it modifies, usually without a hyphen. +\item There is no period after the ``et'' in the Latin abbreviation ``et al.''. +\item The abbreviation ``i.e.'' means ``that is'', and the abbreviation ``e.g.'' means ``for example''. +\end{itemize} +An excellent style manual for science writers is \cite{b7}. + +\subsection{Authors and Affiliations} +\textbf{The class file is designed for, but not limited to, six authors.} A +minimum of one author is required for all conference articles. Author names +should be listed starting from left to right and then moving down to the +next line. This is the author sequence that will be used in future citations +and by indexing services. Names should not be listed in columns nor group by +affiliation. Please keep your affiliations as succinct as possible (for +example, do not differentiate among departments of the same organization). + +\subsection{Identify the Headings} +Headings, or heads, are organizational devices that guide the reader through +your paper. There are two types: component heads and text heads. + +Component heads identify the different components of your paper and are not +topically subordinate to each other. Examples include Acknowledgments and +References and, for these, the correct style to use is ``Heading 5''. Use +``figure caption'' for your Figure captions, and ``table head'' for your +table title. Run-in heads, such as ``Abstract'', will require you to apply a +style (in this case, italic) in addition to the style provided by the drop +down menu to differentiate the head from the text. + +Text heads organize the topics on a relational, hierarchical basis. For +example, the paper title is the primary text head because all subsequent +material relates and elaborates on this one topic. If there are two or more +sub-topics, the next level head (uppercase Roman numerals) should be used +and, conversely, if there are not at least two sub-topics, then no subheads +should be introduced. + +\subsection{Figures and Tables} +\paragraph{Positioning Figures and Tables} Place figures and tables at the top and +bottom of columns. Avoid placing them in the middle of columns. Large +figures and tables may span across both columns. Figure captions should be +below the figures; table heads should appear above the tables. Insert +figures and tables after they are cited in the text. Use the abbreviation +``Fig.~\ref{fig}'', even at the beginning of a sentence. + +\begin{table}[htbp] +\caption{Table Type Styles} +\begin{center} +\begin{tabular}{|c|c|c|c|} +\hline +\textbf{Table}&\multicolumn{3}{|c|}{\textbf{Table Column Head}} \\ +\cline{2-4} +\textbf{Head} & \textbf{\textit{Table column subhead}}& \textbf{\textit{Subhead}}& \textbf{\textit{Subhead}} \\ +\hline +copy& More table copy$^{\mathrm{a}}$& & \\ +\hline +\multicolumn{4}{l}{$^{\mathrm{a}}$Sample of a Table footnote.} +\end{tabular} +\label{tab1} +\end{center} +\end{table} + +\begin{figure}[htbp] +\centerline{\includegraphics{fig1.png}} +\caption{Example of a figure caption.} +\label{fig} +\end{figure} + +Figure Labels: Use 8 point Times New Roman for Figure labels. Use words +rather than symbols or abbreviations when writing Figure axis labels to +avoid confusing the reader. As an example, write the quantity +``Magnetization'', or ``Magnetization, M'', not just ``M''. If including +units in the label, present them within parentheses. Do not label axes only +with units. In the example, write ``Magnetization (A/m)'' or ``Magnetization +\{A[m(1)]\}'', not just ``A/m''. Do not label axes with a ratio of +quantities and units. For example, write ``Temperature (K)'', not +``Temperature/K''. + +\section*{Acknowledgment} + +The preferred spelling of the word ``acknowledgment'' in America is without +an ``e'' after the ``g''. Avoid the stilted expression ``one of us (R. B. +G.) thanks $\ldots$''. Instead, try ``R. B. G. thanks$\ldots$''. Put sponsor +acknowledgments in the unnumbered footnote on the first page. + +\section*{References} + +Please number citations consecutively within brackets \cite{b1}. The +sentence punctuation follows the bracket \cite{b2}. Refer simply to the reference +number, as in \cite{b3}---do not use ``Ref. \cite{b3}'' or ``reference \cite{b3}'' except at +the beginning of a sentence: ``Reference \cite{b3} was the first $\ldots$'' + +Number footnotes separately in superscripts. Place the actual footnote at +the bottom of the column in which it was cited. Do not put footnotes in the +abstract or reference list. Use letters for table footnotes. + +Unless there are six authors or more give all authors' names; do not use +``et al.''. Papers that have not been published, even if they have been +submitted for publication, should be cited as ``unpublished'' \cite{b4}. Papers +that have been accepted for publication should be cited as ``in press'' \cite{b5}. +Capitalize only the first word in a paper title, except for proper nouns and +element symbols. + +For papers published in translation journals, please give the English +citation first, followed by the original foreign-language citation \cite{b6}. + +\begin{thebibliography}{00} +\bibitem{b1} G. Eason, B. Noble, and I. N. Sneddon, ``On certain integrals of Lipschitz-Hankel type involving products of Bessel functions,'' Phil. Trans. Roy. Soc. London, vol. A247, pp. 529--551, April 1955. +\bibitem{b2} J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68--73. +\bibitem{b3} I. S. Jacobs and C. P. Bean, ``Fine particles, thin films and exchange anisotropy,'' in Magnetism, vol. III, G. T. Rado and H. Suhl, Eds. New York: Academic, 1963, pp. 271--350. +\bibitem{b4} K. Elissa, ``Title of paper if known,'' unpublished. +\bibitem{b5} R. Nicole, ``Title of paper with only first word capitalized,'' J. Name Stand. Abbrev., in press. +\bibitem{b6} Y. Yorozu, M. Hirano, K. Oka, and Y. Tagawa, ``Electron spectroscopy studies on magneto-optical media and plastic substrate interface,'' IEEE Transl. J. Magn. Japan, vol. 2, pp. 740--741, August 1987 [Digests 9th Annual Conf. Magnetics Japan, p. 301, 1982]. +\bibitem{b7} M. Young, The Technical Writer's Handbook. Mill Valley, CA: University Science, 1989. +\end{thebibliography} +\vspace{12pt} +\color{red} +IEEE conference templates contain guidance text for composing and formatting conference papers. Please ensure that all template text is removed from your conference paper prior to submission to the conference. Failure to remove the template text from your paper may result in your paper not being published. \ No newline at end of file diff --git a/standard/Report/IEEEtranBST2/IEEEabrv.bib b/standard/Report/IEEEtranBST2/IEEEabrv.bib new file mode 100644 index 0000000000000000000000000000000000000000..f2ea7ba2bdfc4ca990744043d7a66eea4449b17e --- /dev/null +++ b/standard/Report/IEEEtranBST2/IEEEabrv.bib @@ -0,0 +1,447 @@ + +IEEEabrv.bib +V1.12 (2007/01/11) +Copyright (c) 2002-2007 by Michael Shell +See: http://www.michaelshell.org/ +for current contact information. + +BibTeX bibliography string definitions of the ABBREVIATED titles of +IEEE journals and magazines and online publications. + +This file is designed for bibliography styles that require +abbreviated titles and is not for use in bibliographies that +require full-length titles. + +Support sites: +http://www.michaelshell.org/tex/ieeetran/ +http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/ +and/or +http://www.ieee.org/ + +Special thanks to Laura Hyslop and ken Rawson of IEEE for their help +in obtaining the information needed to compile this file. Also, +Volker Kuhlmann and Moritz Borgmann kindly provided some corrections +and additions. + +************************************************************************* +Legal Notice: +This code is offered as-is without any warranty either expressed or +implied; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE! +User assumes all risk. +In no event shall IEEE or any contributor to this code be liable for +any damages or losses, including, but not limited to, incidental, +consequential, or any other damages, resulting from the use or misuse +of any information contained here. + +All comments are the opinions of their respective authors and are not +necessarily endorsed by the IEEE. + +This work is distributed under the LaTeX Project Public License (LPPL) +( http://www.latex-project.org/ ) version 1.3, and may be freely used, +distributed and modified. A copy of the LPPL, version 1.3, is included +in the base LaTeX documentation of all distributions of LaTeX released +2003/12/01 or later. +Retain all contribution notices and credits. +** Modified files should be clearly indicated as such, including ** +** renaming them and changing author support contact information. ** + +File list of work: IEEEabrv.bib, IEEEfull.bib, IEEEexample.bib, + IEEEtran.bst, IEEEtranS.bst, IEEEtranSA.bst, + IEEEtranN.bst, IEEEtranSN.bst, IEEEtran_bst_HOWTO.pdf +************************************************************************* + + +USAGE: + +\bibliographystyle{mybstfile} +\bibliography{IEEEabrv,mybibfile} + +where the IEEE titles in the .bib database entries use the strings +defined here. e.g., + + + journal = IEEE_J_AC, + + +to yield "{IEEE} Trans. Automat. Contr." + + +IEEE uses abbreviated journal titles in their bibliographies - +this file is suitable for work that is to be submitted to the IEEE. + + +For work that requires full-length titles, you should use the full +titles provided in the companion file, IEEEfull.bib. + + +** NOTES ** + + 1. Journals have been grouped according to subject in order to make it + easier to locate and extract the definitions for related journals - + as most works use references that are confined to a single topic. + Magazines are listed in straight alphabetical order. + + 2. String names are closely based on IEEE's own internal acronyms. + + 3. Abbreviations follow IEEE's style. + + 4. Older, out-of-print IEEE titles are included (but not including titles + dating prior to IEEE's formation from the IRE and AIEE in 1963). + + 5. The following NEW/current journal definitions have been disabled because + their abbreviations have not yet been verified: + + STRING{IEEE_J_CBB = "{IEEE/ACM} Trans. Comput. Biology Bioinformatics"} + STRING{IEEE_J_CJECE = "Canadian J. Elect. Comput. Eng."} + STRING{IEEE_J_DSC = "{IEEE} Trans. Dependable Secure Comput."} + STRING{IEEE_O_DSO = "{IEEE} Distrib. Syst. Online"} + + 6. The following OLD journal definitions have been disabled because + their abbreviations have not yet been found/verified: + + STRING{IEEE_J_BCTV = "{IEEE} Trans. Broadcast Television Receivers"} + STRING{IEEE_J_EWS = "{IEEE} Trans. Eng. Writing Speech"} + +If you know what the proper abbreviation is for a string in #5 or #6 above, +email me and I will correct them in the next release. + + + + + +IEEE Journals + + + +aerospace and military +@STRING{IEEE_J_AES = "{IEEE} Trans. Aerosp. Electron. Syst."} +@STRING{IEEE_J_ANE = "{IEEE} Trans. Aerosp. Navig. Electron."} +@STRING{IEEE_J_ANNE = "{IEEE} Trans. Aeronaut. Navig. Electron."} +@STRING{IEEE_J_AS = "{IEEE} Trans. Aerosp."} +@STRING{IEEE_J_AIRE = "{IEEE} Trans. Airborne Electron."} +@STRING{IEEE_J_MIL = "{IEEE} Trans. Mil. Electron."} + + + +autos, transportation and vehicles (non-aerospace) +@STRING{IEEE_J_ITS = "{IEEE} Trans. Intell. Transp. Syst."} +@STRING{IEEE_J_VT = "{IEEE} Trans. Veh. Technol."} +@STRING{IEEE_J_VC = "{IEEE} Trans. Veh. Commun."} + + + +circuits, signals, systems, audio and controls +@STRING{IEEE_J_SPL = "{IEEE} Signal Process. Lett."} +@STRING{IEEE_J_ASSP = "{IEEE} Trans. Acoust., Speech, Signal Process."} +@STRING{IEEE_J_AU = "{IEEE} Trans. Audio"} +@STRING{IEEE_J_AUEA = "{IEEE} Trans. Audio Electroacoust."} +@STRING{IEEE_J_AC = "{IEEE} Trans. Autom. Control"} +@STRING{IEEE_J_CAS = "{IEEE} Trans. Circuits Syst."} +@STRING{IEEE_J_CASVT = "{IEEE} Trans. Circuits Syst. Video Technol."} +@STRING{IEEE_J_CASI = "{IEEE} Trans. Circuits Syst. {I}"} +@STRING{IEEE_J_CASII = "{IEEE} Trans. Circuits Syst. {II}"} +in 2004 CASI and CASII renamed part title to CASI_RP and CASII_EB, respectively. +@STRING{IEEE_J_CASI_RP = "{IEEE} Trans. Circuits Syst. {I}"} +@STRING{IEEE_J_CASII_EB = "{IEEE} Trans. Circuits Syst. {II}"} +@STRING{IEEE_J_CT = "{IEEE} Trans. Circuit Theory"} +@STRING{IEEE_J_CST = "{IEEE} Trans. Control Syst. Technol."} +@STRING{IEEE_J_SP = "{IEEE} Trans. Signal Process."} +@STRING{IEEE_J_SU = "{IEEE} Trans. Sonics Ultrason."} +@STRING{IEEE_J_SAP = "{IEEE} Trans. Speech Audio Process."} +@STRING{IEEE_J_UE = "{IEEE} Trans. Ultrason. Eng."} +@STRING{IEEE_J_UFFC = "{IEEE} Trans. Ultrason., Ferroelectr., Freq. Control"} + + + +communications +@STRING{IEEE_J_COML = "{IEEE} Commun. Lett."} +@STRING{IEEE_J_JSAC = "{IEEE} J. Sel. Areas Commun."} +@STRING{IEEE_J_COM = "{IEEE} Trans. Commun."} +@STRING{IEEE_J_COMT = "{IEEE} Trans. Commun. Technol."} +@STRING{IEEE_J_WCOM = "{IEEE} Trans. Wireless Commun."} + + + +components, packaging and manufacturing +@STRING{IEEE_J_ADVP = "{IEEE} Trans. Adv. Packag."} +@STRING{IEEE_J_CHMT = "{IEEE} Trans. Compon., Hybrids, Manuf. Technol."} +@STRING{IEEE_J_CPMTA = "{IEEE} Trans. Compon., Packag., Manuf. Technol. {A}"} +@STRING{IEEE_J_CPMTB = "{IEEE} Trans. Compon., Packag., Manuf. Technol. {B}"} +@STRING{IEEE_J_CPMTC = "{IEEE} Trans. Compon., Packag., Manuf. Technol. {C}"} +@STRING{IEEE_J_CAPT = "{IEEE} Trans. Compon. Packag. Technol."} +@STRING{IEEE_J_CAPTS = "{IEEE} Trans. Compon. Packag. Technol."} +@STRING{IEEE_J_CPART = "{IEEE} Trans. Compon. Parts"} +@STRING{IEEE_J_EPM = "{IEEE} Trans. Electron. Packag. Manuf."} +@STRING{IEEE_J_MFT = "{IEEE} Trans. Manuf. Technol."} +@STRING{IEEE_J_PHP = "{IEEE} Trans. Parts, Hybrids, Packag."} +@STRING{IEEE_J_PMP = "{IEEE} Trans. Parts, Mater., Packag."} + + + +CAD +@STRING{IEEE_J_TCAD = "{IEEE} J. Technol. Comput. Aided Design"} +@STRING{IEEE_J_CAD = "{IEEE} Trans. Comput.-Aided Design Integr. Circuits Syst."} + + + +coding, data, information, knowledge +@STRING{IEEE_J_IT = "{IEEE} Trans. Inf. Theory"} +@STRING{IEEE_J_KDE = "{IEEE} Trans. Knowl. Data Eng."} + + + +computers, computation, networking and software +@STRING{IEEE_J_C = "{IEEE} Trans. Comput."} +@STRING{IEEE_J_CAL = "{IEEE} Comput. Archit. Lett."} +disabled till definition is verified +STRING{IEEE_J_DSC = "{IEEE} Trans. Dependable Secure Comput."} +@STRING{IEEE_J_ECOMP = "{IEEE} Trans. Electron. Comput."} +@STRING{IEEE_J_EVC = "{IEEE} Trans. Evol. Comput."} +@STRING{IEEE_J_FUZZ = "{IEEE} Trans. Fuzzy Syst."} +@STRING{IEEE_J_IFS = "{IEEE} Trans. Inf. Forensics Security"} +@STRING{IEEE_J_MC = "{IEEE} Trans. Mobile Comput."} +@STRING{IEEE_J_NET = "{IEEE/ACM} Trans. Netw."} +@STRING{IEEE_J_NN = "{IEEE} Trans. Neural Netw."} +@STRING{IEEE_J_PDS = "{IEEE} Trans. Parallel Distrib. Syst."} +@STRING{IEEE_J_SE = "{IEEE} Trans. Softw. Eng."} + + + +computer graphics, imaging, and multimedia +@STRING{IEEE_J_JDT = "{IEEE/OSA} J. Display Technol."} +@STRING{IEEE_J_IP = "{IEEE} Trans. Image Process."} +@STRING{IEEE_J_MM = "{IEEE} Trans. Multimedia"} +@STRING{IEEE_J_VCG = "{IEEE} Trans. Vis. Comput. Graphics"} + + + +cybernetics, ergonomics, robots, man-machine, and automation +@STRING{IEEE_J_ASE = "{IEEE} Trans. Autom. Sci. Eng."} +@STRING{IEEE_J_JRA = "{IEEE} J. Robot. Autom."} +@STRING{IEEE_J_HFE = "{IEEE} Trans. Hum. Factors Electron."} +@STRING{IEEE_J_MMS = "{IEEE} Trans. Man-Mach. Syst."} +@STRING{IEEE_J_PAMI = "{IEEE} Trans. Pattern Anal. Mach. Intell."} +in 1989 JRA became RA +in August 2004, RA split into ASE and RO +@STRING{IEEE_J_RA = "{IEEE} Trans. Robot. Autom."} +@STRING{IEEE_J_RO = "{IEEE} Trans. Robot."} +@STRING{IEEE_J_SMC = "{IEEE} Trans. Syst., Man, Cybern."} +@STRING{IEEE_J_SMCA = "{IEEE} Trans. Syst., Man, Cybern. {A}"} +@STRING{IEEE_J_SMCB = "{IEEE} Trans. Syst., Man, Cybern. {B}"} +@STRING{IEEE_J_SMCC = "{IEEE} Trans. Syst., Man, Cybern. {C}"} +@STRING{IEEE_J_SSC = "{IEEE} Trans. Syst. Sci. Cybern."} + + + +earth, wind, fire and water +@STRING{IEEE_J_GE = "{IEEE} Trans. Geosci. Electron."} +@STRING{IEEE_J_GRS = "{IEEE} Trans. Geosci. Remote Sens."} +@STRING{IEEE_J_GRSL = "{IEEE} Geosci. Remote Sens. Lett."} +@STRING{IEEE_J_OE = "{IEEE} J. Ocean. Eng."} + + + +education, engineering, history, IEEE, professional +disabled till definition is verified +STRING{IEEE_J_CJECE = "Canadian J. Elect. Comput. Eng."} +@STRING{IEEE_J_PROC = "Proc. {IEEE}"} +@STRING{IEEE_J_EDU = "{IEEE} Trans. Educ."} +@STRING{IEEE_J_EM = "{IEEE} Trans. Eng. Manag."} +disabled till definition is verified +STRING{IEEE_J_EWS = "{IEEE} Trans. Eng. Writing Speech"} +@STRING{IEEE_J_PC = "{IEEE} Trans. Prof. Commun."} + + + +electromagnetics, antennas, EMI, magnetics and microwave +@STRING{IEEE_J_AWPL = "{IEEE} Antennas Wireless Propag. Lett."} +@STRING{IEEE_J_MGWL = "{IEEE} Microw. Guided Wave Lett."} +IEEE seems to want "Compon." here, not "Comp." +@STRING{IEEE_J_MWCL = "{IEEE} Microw. Wireless Compon. Lett."} +@STRING{IEEE_J_AP = "{IEEE} Trans. Antennas Propag."} +@STRING{IEEE_J_EMC = "{IEEE} Trans. Electromagn. Compat."} +@STRING{IEEE_J_MAG = "{IEEE} Trans. Magn."} +@STRING{IEEE_J_MTT = "{IEEE} Trans. Microw. Theory Tech."} +@STRING{IEEE_J_RFI = "{IEEE} Trans. Radio Freq. Interference"} +@STRING{IEEE_J_TJMJ = "{IEEE} Transl. J. Magn. Jpn."} + + + +energy and power +@STRING{IEEE_J_EC = "{IEEE} Trans. Energy Convers."} +@STRING{IEEE_J_PEL = "{IEEE} Power Electron. Lett."} +@STRING{IEEE_J_PWRAS = "{IEEE} Trans. Power App. Syst."} +@STRING{IEEE_J_PWRD = "{IEEE} Trans. Power Del."} +@STRING{IEEE_J_PWRE = "{IEEE} Trans. Power Electron."} +@STRING{IEEE_J_PWRS = "{IEEE} Trans. Power Syst."} + + + +industrial, commercial and consumer +@STRING{IEEE_J_APPIND = "{IEEE} Trans. Appl. Ind."} +@STRING{IEEE_J_BC = "{IEEE} Trans. Broadcast."} +disabled till definition is verified +STRING{IEEE_J_BCTV = "{IEEE} Trans. Broadcast Television Receivers"} +@STRING{IEEE_J_CE = "{IEEE} Trans. Consum. Electron."} +@STRING{IEEE_J_IE = "{IEEE} Trans. Ind. Electron."} +@STRING{IEEE_J_IECI = "{IEEE} Trans. Ind. Electron. Contr. Instrum."} +@STRING{IEEE_J_IA = "{IEEE} Trans. Ind. Appl."} +@STRING{IEEE_J_IGA = "{IEEE} Trans. Ind. Gen. Appl."} +@STRING{IEEE_J_IINF = "{IEEE} Trans. Ind. Informat."} +@STRING{IEEE_J_PSE = "{IEEE} J. Product Safety Eng."} + + + +instrumentation and measurement +@STRING{IEEE_J_IM = "{IEEE} Trans. Instrum. Meas."} + + + +insulation and materials +@STRING{IEEE_J_JEM = "{IEEE/TMS} J. Electron. Mater."} +@STRING{IEEE_J_DEI = "{IEEE} Trans. Dielectr. Electr. Insul."} +@STRING{IEEE_J_EI = "{IEEE} Trans. Electr. Insul."} + + + +mechanical +@STRING{IEEE_J_MECH = "{IEEE/ASME} Trans. Mechatronics"} +@STRING{IEEE_J_MEMS = "J. Microelectromech. Syst."} + + + +medical and biological +@STRING{IEEE_J_BME = "{IEEE} Trans. Biomed. Eng."} +Note: The B-ME journal later dropped the hyphen and became the BME. +@STRING{IEEE_J_B-ME = "{IEEE} Trans. Bio-Med. Eng."} +@STRING{IEEE_J_BMELC = "{IEEE} Trans. Bio-Med. Electron."} +disabled till definition is verified +STRING{IEEE_J_CBB = "{IEEE/ACM} Trans. Comput. Biology Bioinformatics"} +@STRING{IEEE_J_ITBM = "{IEEE} Trans. Inf. Technol. Biomed."} +@STRING{IEEE_J_ME = "{IEEE} Trans. Med. Electron."} +@STRING{IEEE_J_MI = "{IEEE} Trans. Med. Imag."} +@STRING{IEEE_J_NB = "{IEEE} Trans. Nanobiosci."} +@STRING{IEEE_J_NSRE = "{IEEE} Trans. Neural Syst. Rehabil. Eng."} +@STRING{IEEE_J_RE = "{IEEE} Trans. Rehabil. Eng."} + + + + optics, lightwave and photonics +@STRING{IEEE_J_PTL = "{IEEE} Photon. Technol. Lett."} +@STRING{IEEE_J_JLT = "J. Lightw. Technol."} + + + +physics, electrons, nanotechnology, nuclear and quantum electronics +@STRING{IEEE_J_EDL = "{IEEE} Electron Device Lett."} +@STRING{IEEE_J_JQE = "{IEEE} J. Quantum Electron."} +@STRING{IEEE_J_JSTQE = "{IEEE} J. Sel. Topics Quantum Electron."} +@STRING{IEEE_J_ED = "{IEEE} Trans. Electron Devices"} +@STRING{IEEE_J_NANO = "{IEEE} Trans. Nanotechnol."} +@STRING{IEEE_J_NS = "{IEEE} Trans. Nucl. Sci."} +@STRING{IEEE_J_PS = "{IEEE} Trans. Plasma Sci."} + + + +reliability +IEEE seems to want "Mat." here, not "Mater." +@STRING{IEEE_J_DMR = "{IEEE} Trans. Device Mater. Rel."} +@STRING{IEEE_J_R = "{IEEE} Trans. Rel."} + + + +semiconductors, superconductors, electrochemical and solid state +@STRING{IEEE_J_ESSL = "{IEEE/ECS} Electrochem. Solid-State Lett."} +@STRING{IEEE_J_JSSC = "{IEEE} J. Solid-State Circuits"} +@STRING{IEEE_J_ASC = "{IEEE} Trans. Appl. Supercond."} +@STRING{IEEE_J_SM = "{IEEE} Trans. Semicond. Manuf."} + + + +sensors +@STRING{IEEE_J_SENSOR = "{IEEE} Sensors J."} + + + +VLSI +@STRING{IEEE_J_VLSI = "{IEEE} Trans. {VLSI} Syst."} + + + + + + +IEEE Magazines + + + +@STRING{IEEE_M_AES = "{IEEE} Aerosp. Electron. Syst. Mag."} +@STRING{IEEE_M_HIST = "{IEEE} Ann. Hist. Comput."} +@STRING{IEEE_M_AP = "{IEEE} Antennas Propag. Mag."} +@STRING{IEEE_M_ASSP = "{IEEE} {ASSP} Mag."} +@STRING{IEEE_M_CD = "{IEEE} Circuits Devices Mag."} +@STRING{IEEE_M_CAS = "{IEEE} Circuits Syst. Mag."} +@STRING{IEEE_M_COM = "{IEEE} Commun. Mag."} +@STRING{IEEE_M_COMSOC = "{IEEE} Commun. Soc. Mag."} +@STRING{IEEE_M_CIM = "{IEEE} Comput. Intell. Mag."} +CSEM changed to CSE in 1999 +@STRING{IEEE_M_CSE = "{IEEE} Comput. Sci. Eng."} +@STRING{IEEE_M_CSEM = "{IEEE} Comput. Sci. Eng. Mag."} +@STRING{IEEE_M_C = "{IEEE} Computer"} +@STRING{IEEE_M_CAP = "{IEEE} Comput. Appl. Power"} +@STRING{IEEE_M_CGA = "{IEEE} Comput. Graph. Appl."} +@STRING{IEEE_M_CONC = "{IEEE} Concurrency"} +@STRING{IEEE_M_CS = "{IEEE} Control Syst. Mag."} +@STRING{IEEE_M_DTC = "{IEEE} Des. Test. Comput."} +@STRING{IEEE_M_EI = "{IEEE} Electr. Insul. Mag."} +@STRING{IEEE_M_ETR = "{IEEE} ElectroTechnol. Rev."} +@STRING{IEEE_M_EMB = "{IEEE} Eng. Med. Biol. Mag."} +@STRING{IEEE_M_EMR = "{IEEE} Eng. Manag. Rev."} +@STRING{IEEE_M_EXP = "{IEEE} Expert"} +@STRING{IEEE_M_IA = "{IEEE} Ind. Appl. Mag."} +@STRING{IEEE_M_IM = "{IEEE} Instrum. Meas. Mag."} +@STRING{IEEE_M_IS = "{IEEE} Intell. Syst."} +@STRING{IEEE_M_IC = "{IEEE} Internet Comput."} +@STRING{IEEE_M_ITP = "{IEEE} {IT} Prof."} +@STRING{IEEE_M_MICRO = "{IEEE} Micro"} +@STRING{IEEE_M_MW = "{IEEE} Microw. Mag."} +@STRING{IEEE_M_MM = "{IEEE} Multimedia"} +@STRING{IEEE_M_NET = "{IEEE} Netw."} +IEEE's editorial manual lists "Pers. Commun.", +but "Personal Commun. Mag." seems to be what is used in the journals +@STRING{IEEE_M_PCOM = "{IEEE} Personal Commun. Mag."} +@STRING{IEEE_M_POT = "{IEEE} Potentials"} +CAP and PER merged to form PE in 2003 +@STRING{IEEE_M_PE = "{IEEE} Power Energy Mag."} +@STRING{IEEE_M_PER = "{IEEE} Power Eng. Rev."} +@STRING{IEEE_M_PVC = "{IEEE} Pervasive Comput."} +@STRING{IEEE_M_RA = "{IEEE} Robot. Autom. Mag."} +@STRING{IEEE_M_SAP = "{IEEE} Security Privacy"} +@STRING{IEEE_M_SP = "{IEEE} Signal Process. Mag."} +@STRING{IEEE_M_S = "{IEEE} Softw."} +@STRING{IEEE_M_SPECT = "{IEEE} Spectr."} +@STRING{IEEE_M_TS = "{IEEE} Technol. Soc. Mag."} +@STRING{IEEE_M_VT = "{IEEE} Veh. Technol. Mag."} +@STRING{IEEE_M_WC = "{IEEE} Wireless Commun. Mag."} +@STRING{IEEE_M_TODAY = "Today's Engineer"} + + + + + + +IEEE Online Publications + + + +@STRING{IEEE_O_CSTO = "{IEEE} Commun. Surveys Tuts."} +disabled till definition is verified +STRING{IEEE_O_DSO = "{IEEE} Distrib. Syst. Online"} + + + + + +-- +EOF diff --git a/standard/Report/IEEEtranBST2/IEEEexample.bib b/standard/Report/IEEEtranBST2/IEEEexample.bib new file mode 100644 index 0000000000000000000000000000000000000000..8e529a01c12a9781cef151a85e10b1388c74f72b --- /dev/null +++ b/standard/Report/IEEEtranBST2/IEEEexample.bib @@ -0,0 +1,1190 @@ + +IEEEexample.bib +V1.12 (2007/01/11) +Copyright (c) 2002-2007 by Michael Shell +See: http://www.michaelshell.org/ +for current contact information. + +This is an example BibTeX database for the official IEEEtran.bst +BibTeX style file. + +Some entries call strings that are defined in the IEEEabrv.bib file. +Therefore, IEEEabrv.bib should be loaded prior to this file. +Usage: + +\bibliographystyle{./IEEEtran} +\bibliography{./IEEEabrv,./IEEEexample} + + +Support sites: +http://www.michaelshell.org/tex/ieeetran/ +http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/ +and/or +http://www.ieee.org/ + +************************************************************************* +Legal Notice: +This code is offered as-is without any warranty either expressed or +implied; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE! +User assumes all risk. +In no event shall IEEE or any contributor to this code be liable for +any damages or losses, including, but not limited to, incidental, +consequential, or any other damages, resulting from the use or misuse +of any information contained here. + +All comments are the opinions of their respective authors and are not +necessarily endorsed by the IEEE. + +This work is distributed under the LaTeX Project Public License (LPPL) +( http://www.latex-project.org/ ) version 1.3, and may be freely used, +distributed and modified. A copy of the LPPL, version 1.3, is included +in the base LaTeX documentation of all distributions of LaTeX released +2003/12/01 or later. +Retain all contribution notices and credits. +** Modified files should be clearly indicated as such, including ** +** renaming them and changing author support contact information. ** + +File list of work: IEEEabrv.bib, IEEEfull.bib, IEEEexample.bib, + IEEEtran.bst, IEEEtranS.bst, IEEEtranSA.bst, + IEEEtranN.bst, IEEEtranSN.bst, IEEEtran_bst_HOWTO.pdf +************************************************************************* + + +Note that, because the example references were taken from actual IEEE +publications, these examples do not always contain the full amount +of information that may be desirable (for use with other BibTeX styles). +In particular, full names (not abbreviated with initials) should be +entered whenever possible as some (non-IEEE) bibliography styles use +full names. IEEEtran.bst will automatically abbreviate when it encounters +full names. + + + + +references for the IEEEtran.bst documentation +IEEEtran homepage +@electronic{IEEEhowto:IEEEtranpage, + author = "Michael Shell", + title = "{IEEE}tran Homepage", + url = "http://www.michaelshell.org/tex/ieeetran/", + year = "2007" +} + + +the distribution site for IEEEtran.bst +@electronic{IEEEexample:shellCTANpage, + author = "Michael Shell", + title = "{IEEE}tran Webpage on {CTAN}", + url = "http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/", + year = "2007" +} + + +the IEEE website +sort key is needed for sorting styles +@electronic{IEEEexample:IEEEwebsite, + title = "The {IEEE} Website", + url = "http://www.ieee.org/", + year = "2007", + key = "IEEE" +} + + +The BibTeX user's guide. +The filename could have been put in the URL instead. But, there might +be other interesting things for the user in the same directory - and +the filename might change before the directory that contains it. +@electronic{IEEEexample:bibtexuser, + author = "Oren Patashnik", + title = "{{\BibTeX}}ing", + howpublished = "{btxdoc.pdf}", + url = "http://www.ctan.org/tex-archive/biblio/bibtex/contrib/doc/", + month = feb, + year = "1988" +} + + +The BibTeX style designer's guide. +@electronic{IEEEexample:bibtexdesign, + author = "Oren Patashnik", + title = "Designing {{\BibTeX}} Styles", + howpublished = "{btxhak.pdf}", + url = "http://www.ctan.org/tex-archive/biblio/bibtex/contrib/doc/", + month = feb, + year = "1988" +} + + +A comprehensive BibTeX tutorial. +@electronic{IEEEexample:tamethebeast, + author = "Nicolas Markey", + title = "Tame the BeaST --- The B to X of {{\BibTeX}}", + url = "http://tug.ctan.org/tex-archive/info/bibtex/tamethebeast/", + month = oct, + year = "2005" +} + + +The BibTeX Tips and FAQ guide. +@electronic{IEEEexample:bibtexFAQ, + author = "David Hoadley and Michael Shell", + title = "{{\BibTeX}} Tips and {FAQ}", + howpublished = "{btxFAQ.pdf}", + url = "http://www.ctan.org/tex-archive/biblio/bibtex/contrib/doc/", + month = jan, + year = "2007" +} + + +The TeX FAQ +@electronic{IEEEexample:texfaq, + author = "Robin Fairbairns", + title = "The {{\TeX}} {FAQ}", + url = "http://www.tex.ac.uk/cgi-bin/texfaq2html/", + month = jan, + year = "2007" +} + + +A BibTeX Guide via Examples. +@electronic{IEEEexample:bibtexguide, + author = "Ki-Joo Kim", + title = "A {{\BibTeX}} Guide via Examples", + howpublished = "{bibtex\_guide.pdf}", + url = "http://www.geocities.com/kijoo2000/", + month = apr, + year = "2004" +} + + +TeX User Group Bibliography Archive +@electronic{IEEEexample:beebe_archive, + author = "Nelson H. F. Beebe", + title = "{{\TeX}} User Group Bibliography Archive", + url = "http://www.math.utah.edu:8080/pub/tex/bib/index-table.html", + month = aug, + year = "2006" +} + +The natbib.sty package. +@electronic{ctan:natbib, + author = "Patrick W. Daly", + title = "The natbib.sty package", + url = "http://www.ctan.org/tex-archive/macros/latex/contrib/natbib/", + month = sep, + year = "2006" +} + +The url.sty package. +@electronic{IEEEexample:urlsty, + author = "Donald Arseneau", + title = "The url.sty Package", + url = "http://www.ctan.org/tex-archive/macros/latex/contrib/misc/", + month = jun, + year = "2005", +} + + +The hyperref.sty package. +@electronic{IEEEexample:hyperrefsty, + author = "Sebastian Rahtz and Heiko Oberdiek", + title = "The hyperref.sty Package", + url = "http://www.ctan.org/tex-archive/macros/latex/contrib/hyperref/", + month = nov, + year = "2006", +} + + +The breakurl.sty package. +@electronic{IEEEexample:breakurl, + author = "Vilar Camara Neto", + title = "The breakurl.sty Package", + url = "http://www.ctan.org/tex-archive/macros/latex/contrib/breakurl/", + month = aug, + year = "2006", +} + + +The Babel package. +@electronic{IEEEexample:babel, + author = "Johannes Braams", + title = "The Babel Package", + url = "http://www.ctan.org/tex-archive/macros/latex/required/babel/", + month = nov, + year = "2005", +} + + +The multibib package. +@electronic{IEEEexample:multibibsty, + author = "Thorsten Hansen", + title = "The multibib.sty package", + url = "http://www.ctan.org/tex-archive/macros/latex/contrib/multibib/", + month = jan, + year = "2004" +} + + +The biblatex package. +@electronic{IEEEexample:biblatex, + author = "Philipp Lehman", + title = "The biblatex package", + url = "http://www.ctan.org/tex-archive/macros/latex/exptl/biblatex/", + month = jan, + year = "2007" +} + + + +The three most common and typical types of references used in +IEEE publications: + +an article in a journal +Note the use of the IEEE_J_EDL string, defined in the IEEEabrv.bib file, +for the journal name. IEEEtran.bst defines the BibTeX standard three +letter month codes per IEEE style. +From the June 2002 issue of "IEEE Transactions on Electron Devices", +page 996, reference #16. +@article{IEEEexample:article_typical, + author = "S. Zhang and C. Zhu and J. K. O. Sin and P. K. T. Mok", + title = "A Novel Ultrathin Elevated Channel Low-temperature + Poly-{Si} {TFT}", + journal = IEEE_J_EDL, + volume = "20", + month = nov, + year = "1999", + pages = "569-571" +} + + +journal article using et al. +The (five) authors are actually: F. Delorme, S. Slempkes, G. Alibert, +B. Rose, J. Brandon +The month (July) was not given here. +From the September 1998 issue of "IEEE Journal on Selected Areas in +Communications", page 1257, reference #28. +@article{IEEEexample:articleetal, + author = "F. Delorme and others", + title = "Butt-jointed {DBR} Laser With 15 {nm} Tunability Grown + in Three {MOVPE} Steps", + journal = "Electron. Lett.", + volume = "31", + number = "15", + year = "1995", + pages = "1244-1245" +} + + +a paper in a conference proceedings +"conference" can be used as an alias for "inproceedings" +From the June 2002 issue of "Journal of Microelectromechanical Systems", +page 205, reference #16. +@inproceedings{IEEEexample:conf_typical, + author = "R. K. Gupta and S. D. Senturia", + title = "Pull-in Time Dynamics as a Measure of Absolute Pressure", + booktitle = "Proc. {IEEE} International Workshop on + Microelectromechanical Systems ({MEMS}'97)", + address = "Nagoya, Japan", + month = jan, + year = "1997", + pages = "290-294" +} + + +a book +From the May 2002 issue of "IEEE Transactions on Magnetics", +page 1466, reference #4. +@book{IEEEexample:book_typical, + author = "B. D. Cullity", + title = "Introduction to Magnetic Materials", + publisher = "Addison-Wesley", + address = "Reading, MA", + year = "1972" +} + + + + +Other examples + +journal article with large page numbers, IEEE will divide numbers 5 digits +or longer into groups of three with small spaces between them. Page ranges +can be separated via either "-" or "--", IEEEtran.bst will automatically +convert the separator dash(es) to "--". +Authors and/or IEEE do not always provide/use the journal number, but it +was used in this case. IEEEtran.bst can be configured to ignore journal +numbers if desired. +From the August 2000 issue of "IEEE Photonics Technology Letters", +page 1039, reference #11. +@article{IEEEexample:articlelargepages, + author = "A. Castaldini and A. Cavallini and B. Fraboni + and P. Fernandez and J. Piqueras", + title = "Midgap Traps Related to Compensation Processes in + {CdTe} Alloys", + journal = "Phys. Rev. B.", + volume = "56", + number = "23", + year = "1997", + pages = "14897-14900" +} + + +journal article with dual months +use the BibTeX "#" concatenation operator +From the March 2002 issue of "IEEE Transactions on Mechatronics", +page 21, reference #8. +@article{IEEEexample:articledualmonths, + author = "Y. Okada and K. Dejima and T. Ohishi", + title = "Analysis and Comparison of {PM} Synchronous Motor and + Induction Motor Type Magnetic Bearings", + journal = IEEE_J_IA, + volume = "31", + month = sep # "/" # oct, + year = "1995", + pages = "1047-1053" +} + + +journal article to be published as a misc entry type +date information like month and year is optional +However, the article form like that below may be a better approach. +From the May 2002 issue of "IEEE Journal of Selected Areas in +Communication", page 725, reference #3. +@misc{IEEEexample:TBPmisc, + author = "M. Coates and A. Hero and R. Nowak and B. Yu", + title = "Internet Tomography", + howpublished = IEEE_M_SP, + month = may, + year = "2002", + note = "to be published" +} + + +journal article to be published as an article entry type +year is required, so if absent, use the year field to hold +the "submitted for publication" in order to avoid a warning for +the missing year field. +From the June 2002 issue of "IEEE Transactions on Information Theory", +page 1461, reference #21. +@article{IEEEexample:TBParticle, + author = "N. Kahale and R. Urbanke", + title = "On the Minimum Distance of Parallel and Serially + Concatenated Codes", + journal = IEEE_J_IT, + year = "submitted for publication" +} + + + + + +book with editor and no author +From the June 2002 issue of "IEEE Transactions on Information Theory", +page 1725, reference #1. +@book{IEEEexample:bookwitheditor, + editor = "J. C. Candy and G. C. Temes", + title = "Oversampling Delta-Sigma Data Converters Theory, + Design and Simulation", + publisher = "{IEEE} Press.", + address = "New York", + year = "1992" +} + + +book with edition, author and editor +Note that the standard BibTeX styles do not support book entries with both +author and editor fields, but IEEEtran.bst does. +The standard BibTeX way of specifying the edition is to use capitalized +ordinal words such as "First", "Second", etc. Most .bst files can convert +up to about "Fifth" into the format needed. IEEEtran.bst can convert up +to "Tenth" to the "Arabic ordinal" form IEEE uses (e.g., "10th"). For +editions over the tenth, it is best to use the "Arabic ordinal" form for +IEEE related work (e.g., "101st") +Note how "Jr." has to be entered. +From the May 2002 issue of "Journal of Lightwave Technology", page 856, +reference #17. +@book{IEEEexample:book, + author = "S. M. Metev and V. P. Veiko", + editor = "Osgood, Jr., R. M.", + title = "Laser Assisted Microtechnology", + edition = "Second", + publisher = "Springer-Verlag", + address = "Berlin, Germany", + year = "1998" +} + + +book with series and volume +From the January 2000 issue of "IEEE Transactions on Communications", +page 11, reference #31. +@book{IEEEexample:bookwithseriesvolume, + editor = "J. Breckling", + title = "The Analysis of Directional Time Series: Applications to + Wind Speed and Direction", + series = "Lecture Notes in Statistics", + publisher = "Springer", + address = "Berlin, Germany", + year = "1989", + volume = "61" +} + + +inbook with chapter number. The pages field could also have been given. +The chapter number could be changed to something else such as a section +number via the type field: type = "sec.". +From the May 2002 issue of "IEEE Transactions on Circuits and Systems---I: +Fundamental Applications and Theory", page 638, reference #22. +@inbook{IEEEexample:inbook, + author = "H. E. Rose", + title = "A Course in Number Theory", + publisher = "Oxford Univ. Press", + address = "New York, NY", + year = "1988", + chapter = "3" +} + + +inbook with pages and note. The language field is not set to Russian +because the title is presented here in its translated, English, form. +From the May 2002 issue of "IEEE Transactions on Magnetics", page 1533, +reference #5. +@inbook{IEEEexample:inbookpagesnote, + author = "B. K. Bul", + title = "Theory Principles and Design of Magnetic Circuits", + publisher = "Energia Press", + address = "Moscow", + year = "1964", + pages = "464", + note = "(in Russian)" +} + + + + + +incollection with author and editor +From the May 2002 issue of "Journal of Lightwave Technology", +page 807, reference #7. +@incollection{IEEEexample:incollection, + author = "W. V. Sorin", + editor = "D. Derickson", + title = "Optical Reflectometry for Component Characterization", + booktitle = "Fiber Optic Test and Measurement", + publisher = "Prentice-Hall", + address = "Englewood Cliffs, NJ", + year = "1998" +} + + +incollection with series +From the April 2000 issue of "IEEE Transactions on Communication", +page 609, reference #3. +@incollection{IEEEexample:incollectionwithseries, + author = "J. B. Anderson and K. Tepe", + title = "Properties of the Tailbiting {BCJR} Decoder", + booktitle = "Codes, Systems and Graphical Models", + series = "{IMA} Volumes in Mathematics and Its Applications", + publisher = "Springer-Verlag", + address = "New York", + year = "2000" + +} + + +incollection with author, editor, chapter and pages +From the January 2000 issue of "IEEE Transactions on Communications", +page 16, reference #9. +@incollection{IEEEexample:incollection_chpp, + author = "P. Hedelin and P. Knagenhjelm and M. Skoglund", + editor = "W. B. Kleijn and K. K. Paliwal", + title = "Theory for Transmission of Vector Quantization Data", + booktitle = "Speech Coding and Synthesis", + publisher = "Elsevier Science", + address = "Amsterdam, The Netherlands", + year = "1995", + chapter = "10", + pages = "347-396" +} + + +incollection with a large number of authors, some authors/journals will +use et al. for so many names. IEEEtran.bst can be configured to do this +if desired, or "R. M. A. Dawson and others" can be used instead. +Note that IEEE may not include the publisher for incollection entries - +IEEEtran.bst will not issue a warning if the publisher is missing for +incollections - but other .bst files often will. +From the June 2002 issue of "IEEE Transactions on Electron Devices", +page 996, reference #12. +@incollection{IEEEexample:incollectionmanyauthors, + author = "R. M. A. Dawson and Z. Shen and D. A. Furst and + S. Connor and J. Hsu and M. G. Kane and R. G. Stewart and + A. Ipri and C. N. King and P. J. Green and R. T. Flegal + and S. Pearson and W. A. Barrow and E. Dickey and K. Ping + and C. W. Tang and S. Van. Slyke and + F. Chen and J. Shi and J. C. Sturm and M. H. Lu", + title = "Design of an Improved Pixel for a Polysilicon + Active-Matrix Organic {LED} Display", + booktitle = "{SID} Tech. Dig.", + volume = "29", + year = "1998", + pages = "11-14" +} + + + + + +A Motorola data book as a manual +It is somewhat unusual to include the data book part number. +in the title. It might be more correct to put this information +in the howpublished field instead. +From the December 2000 issue of "IEEE Transactions on Communications", +page 1986, reference #10. +@manual{IEEEexample:motmanual, + title = "{FLEXChip} Signal Processor ({MC68175/D})", + organization = "Motorola", + year = "1996" +} + + +same reference, but using IEEEtran's howpublished extension +@manual{IEEEexample:motmanualhowpub, + title = "{FLEXChip} Signal Processor", + howpublished = "{MC68175/D}", + organization = "Motorola", + year = "1996" +} + + + + +conference paper with an address and days. Some journals capitalize the +letters in "Globecom", this one did not. +From the May 2002 issue of "IEEE Transactions on Communications", +page 697, reference #12. +@inproceedings{IEEEexample:confwithadddays, + author = "M. S. Yee and L. Hanzo", + title = "Radial Basis Function Decision Feedback Equaliser + Assisted Burst-by-burst Adaptive Modulation", + booktitle = "Proc. {IEEE} Globecom '99", + address = "Rio de Janeiro, Brazil", + month = dec # " 5--9,", + year = "1999", + pages = "2183-2187" +} + + +conference paper with volume number. A conference proceedings with a vol +number is a little uncommon, note that the vol number is placed +before the address in the formatted bibliography entry +From the April 2002 issue of "IEEE/ACM Transactions on Networking", +page 181, reference #26. +@inproceedings{IEEEexample:confwithvolume, + author = "M. Yajnik and S. B. Moon and J. Kurose and D. Towsley", + title = "Measurement and Modeling of the Temporal Dependence in + Packet Loss", + booktitle = "Proc. {IEEE} {INFOCOM}'99", + volume = "1", + address = "New York, NY", + month = mar, + year = "1999", + pages = "345-352" +} + + +conference paper with a paper number, the type field can be used to +override the word "paper", e.g., type = "postdeadline paper". A type +can be given even without a paper field. +Also, IEEEtran.bst can be configured to ignore paper numbers and types. +From the May 2002 issue of "Journal of Lightwave Technology", +page 807, reference #4. +@inproceedings{IEEEexample:confwithpaper, + author = "M. Wegmuller and J. P. von der Weid and P. Oberson + and N. Gisin", + title = "High Resolution Fiber Distributed Measurements With + Coherent {OFDR}", + booktitle = "Proc. {ECOC}'00", + year = "2000", + paper = "11.3.4", + pages = "109" +} + + +conference paper with a postdeadline type paper, the paper field is +optional. +From the August 2000 issue of "IEEE Photonics Technology Letters", +page 1087, reference #12. +@inproceedings{IEEEexample:confwithpapertype, + author = "B. Mikkelsen and G. Raybon and R.-J. Essiambre and + K. Dreyer and Y. Su. and L. E. Nelson and J. E. Johnson + and G. Shtengel and A. Bond and D. G. Moodie and + A. D. Ellis", + title = "160 {Gbit/s} Single-channel Transmission Over 300 km + Nonzero-dispersion Fiber With Semiconductor Based + Transmitter and Demultiplexer", + booktitle = "Proc. {ECOC}'99", + year = "1999", + paper = "2-3", + type = "postdeadline paper", + pages = "28-29" +} + + +presented at a conference +intype overrides the default "in" and causes the booktitle not to be +emphasized (rendered in italics). +From the February 2002 issue of "IEEE/ACM Transactions on Networking", +page 163, reference #6. +@inproceedings{IEEEexample:presentedatconf, + author = "S. G. Finn and M. M{\'e}dard and R. A. Barry", + title = "A Novel Approach to Automatic Protection Switching + Using Trees", + intype = "presented at the", + booktitle = "Proc. Int. Conf. Commun.", + year = "1997" +} + + + + + +master's thesis, often the University name will be abbreviated and the +state or country will be included in the address. The type field can +used to override the default type "Master's thesis" +From the June 2002 issue of "IEEE Transactions on Microelectromechanical +Systems", page 186, reference #11. +@mastersthesis{IEEEexample:masters, + author = "Nin C. Loh", + title = "High-Resolution Micromachined Interferometric + Accelerometer", + school = "Massachusetts Institute of Technology", + address = "Cambridge", + year = "1992" +} + + +master's thesis with a type field +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 391, reference #12. +@mastersthesis{IEEEexample:masterstype, + author = "A. Karnik", + title = "Performance of {TCP} Congestion Control with Rate + Feedback: {TCP/ABR} and Rate Adaptive {TCP/IP}", + school = "Indian Institute of Science", + type = "M. Eng. thesis", + address = "Bangalore, India", + month = jan, + year = "1999" +} + + + + + +Ph.D. dissertation with a URL field, the university is abbreviated +From the October 2001 issue of "IEEE/ACM Transactions on Networking", +page 590, reference #11. +@phdthesis{IEEEexample:phdurl, + author = "Q. Li", + title = "Delay Characterization and Performance Control of + Wide-area Networks", + school = "Univ. of Delaware", + address = "Newark", + month = may, + year = "2000", + url = "http://www.ece.udel.edu/~qli" +} + + + + + +technical report +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 490, reference #15. +@techreport{IEEEexample:techrep, + author = "R. Jain and K. K. Ramakrishnan and D. M. Chiu", + title = "Congestion Avoidance in Computer Networks with a + Connectionless Network Layer", + institution = "Digital Equipment Corporation", + address = "MA", + number = "DEC-TR-506", + month = aug, + year = "1987" +} + + +technical report with type +for those times when "Tech. Rep." needs to be modified +From the February 2001 issue of "IEEE/ACM Transactions on Networking", +page 46, reference #8. +@techreport{IEEEexample:techreptype, + author = "J. Padhye and V. Firoiu and D. Towsley", + title = "A Stochastic Model of {TCP} {R}eno Congestion Avoidance + and Control", + institution = "Univ. of Massachusetts", + address = "Amherst, MA", + type = "CMPSCI Tech. Rep.", + number = "99-02", + year = "1999" +} + + +technical report with type +for those times when "Tech. Rep." needs to be modified +This reference did not have an address. +From the January 2000 issue of "IEEE Transactions on Communications", +page 117, reference #6. +@techreport{IEEEexample:techreptypeii, + author = "D. Middleton and A. D. Spaulding", + title = "A Tutorial Review of Elements of Weak Signal Detection + in Non-{G}aussian {EMI} Environments", + institution = "National Telecommunications and Information + Administration ({NTIA}), U.S. Dept. of Commerce", + type = "NTIA Report", + number = "86-194", + month = may, + year = "1986" +} + + + + + +an unpublished work +for unpublished types, the note field is required. IEEE usually +just uses the word "unpublished" for the note. +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 391, reference #16. +@unpublished{IEEEexample:unpublished, + author = "T. J. Ott and N. Aggarwal", + title = "{TCP} over {ATM}: {ABR} or {UBR}", + note = "Unpublished" +} + + + + + +electronic with a howpublished information field +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 391, reference #7. +@electronic{IEEEexample:electronhowinfo, + author = "V. Jacobson", + title = "Modified {TCP} Congestion Avoidance Algorithm", + howpublished = "end2end-interest mailing list", + url = "ftp://ftp.isi.edu/end2end/end2end-interest-1990.mail", + month = apr, + year = "1990" +} + + +electronic with a howpublished information field +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 418, reference #31. +@electronic{IEEEexample:electronhowinfo2, + author = "V. Valloppillil and K. W. Ross", + title = "Cache Array Routing Protocol v1.1", + howpublished = "Internet draft", + url = "http://ds1.internic.net/internet-drafts/draft-vinod-carp-v1-03.txt", + year = "1998" +} + + +electronic with an organization and address +From the February 2002 issue of "IEEE/ACM Transactions on Networking", +page 114, reference #15. +@electronic{IEEEexample:electronorgadd, + author = "D. H. Lorenz and A. Orda", + title = "Optimal Partition of {QoS} Requirements on Unicast + Paths and Multicast Trees", + organization = "Dept. Elect. Eng., Technion", + address = "Haifa, Israel", + url = "ftp://ftp.technion.ac.il/pub/supported/ee/Network/lor.mopq98.ps", + month = jul, + year = "1998" +} + + + + + +U.S. patent +Use the type field to override the patent type. e.g., +type = "Patent Application" +The address is that of the assignee. Note that IEEE does not +display the assignee, the address, and only displays one date. +(if year is not present, the filed dates are used.) However, this +information should be entered as other BibTeX styles may use it. +alternatively, nationality could be entered as "U.S." +From the April 2000 issue of "IEEE Transactions on Communications", +page 542, reference #6. +@patent{IEEEexample:uspat, + author = "Ronald E. Sorace and Victor S. Reinhardt and + Steven A. Vaughn", + assignee = "Hughes Aircraft Company", + address = "Los Angeles, CA", + title = "High-Speed Digital-to-{RF} Converter", + nationality = "United States", + number = "5668842", + dayfiled = "28", + monthfiled = feb, + yearfiled = "1995", + day = "16", + month = sep, + year = "1997" +} + + +Japanese Patent +From the April 2000 issue of "IEEE Transactions on Communications", +page 556, reference #6. +@patent{IEEEexample:jppat, + author = "U. Hideki", + title = "Quadrature Modulation Circuit", + nationality = "Japanese", + number = "152932/92", + day = "20", + month = may, + year = "1992" +} + + +French Patent request, the language field must be entered in lower case +as this is the option name Babel uses. The nationality field needs to be +capitalized. Because this is a patent request, the date filed fields are +used while the date fields are left empty/missing. In other countries, +the words "Patent Application", etc. are used instead. +From the April 2000 issue of "IEEE Transactions on Communications", +page 556, reference #9. +@patent{IEEEexample:frenchpatreq, + author = "F. Kowalik and M. Isard", + title = "Estimateur d'un D{\'e}faut de Fonctionnement + d'un Modulateur en Quadrature et {\'E}tage de Modulation + l'Utilisant", + language = "french", + nationality = "French", + type = "Patent Request", + number = "9500261", + dayfiled = "11", + monthfiled = jan, + yearfiled = "1995" +} + + + + + +a periodical +From the April 2001 issue of "IEEE/ACM Transactions on Networking", +page 160, reference #1. +sort key is needed for sorting styles +@periodical{IEEEexample:periodical, + title = IEEE_M_PCOM # ", Special Issue on Wireless {ATM}", + volume = "3", + month = aug, + year = "1996", + key = "IEEE" +} + + + + + +standard, IEEE does not use the address for standards, but it is good +to provide one for BibTeX styles that use it. +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 451, reference #2. +@standard{IEEEexample:standard, + title = "Wireless {LAN} Medium Access Control {(MAC)} and + Physical Layer {(PHY)} Specification", + organization = "IEEE", + address = "Piscataway, NJ", + number = "802.11", + year = "1997" +} + + +standard with type and revision, the type overrides the word standard +(or std.). Here a standard number is not available and a revision number +is used. +From the August 2000 issue of "IEEE Photonics Technology Letters", +page 1048, reference #13. +@standard{IEEEexample:standardproposed, + title = "Fiber Channel Physical Interface ({FC-PI})", + institution = "NCITS", + address = "Washington, DC", + type = "Working Draft Proposed Standard", + revision = "5.2", + year = "1999" +} + + +standard draft as a misc with author +From the May 2002 issue of "IEEE Journal of Selected Areas in +Communication", page 725, reference #16. +@misc{IEEEexample:draftasmisc, + author = "I. Widjaja and A. Elwalid", + title = "{MATE}: {MPLS} Adaptive Traffic Engineering", + howpublished = "IETF Draft", + year = "1999" +} + + + + + +misc for a techreport like reference +techreport is not perfectly suitable because this entry lacks +an institution field +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 490, reference #22. +@misc{IEEEexample:miscforum, + author = "L. Roberts", + title = "Enhanced Proportional Rate Control Algorithm {PRCA}", + howpublished = "{ATM} Forum Contribution 94-0735R1", + month = aug, + year = "1994" +} + + +misc for a white paper +From the August 2001 issue of "IEEE/ACM Transactions on Networking", +page 478, reference #4 - Note that the reference there (improperly?) +used the author field for "Cisco". +@misc{IEEEexample:whitepaper, + title = "Advanced {QoS} Services for the Intelligent Internet", + howpublished = "White Paper", + organization = "Cisco", + month = may, + year = "1997" +} + + +misc for a data sheet +From the November 2000 issue of "IEEE Photonics Technology Letters", +page 1551, reference #6. +@misc{IEEEexample:datasheet, + title = "{PDCA12-70} Data Sheet", + organization = "Opto Speed SA", + address = "Mezzovico, Switzerland" +} + + + + + +Other unusual references + +a private communication as a misc entry type +sometimes the designation "personal communication" is used instead +From the June 2002 issue of "IEEE Transactions on Information Theory", +page 1725, reference #16. +@misc{IEEEexample:private, + author = "S. Konyagin", + howpublished = "private communication", + year = "1998" +} + + +an internet request for comments (RFC) as a misc entry type +It would also be nice to add a URL to these types of things. +RFCs can also be handled as electronic references. +From the April 2002 issue of "IEEE/ACM Transactions on Networking", +page 181, reference #14. +@misc{IEEEexample:miscrfc, + author = "K. K. Ramakrishnan and S. Floyd", + title = "A Proposal to Add Explicit Congestion + Notification ({ECN}) to {IP}", + howpublished = "RFC 2481", + month = jan, + year = "1999" +} + + +a software package as a manual +From the June 2002 issue of "IEEE/ASME Journal of Microelectromechanical +Systems", page 205, reference #20. +Sometimes they put the version/release information in the title. +@manual{IEEEexample:softmanual, + title = "SaberDesigner Reference Manual", + organization = "Analogy, Inc.", + address = "Beaverton, OR", + year = "1998", + note = "Release 4.3" +} + + +a software package as an electronic reference +From the February 2003 issue of "IEEE/ACM Transactions on Networking", +page 46, reference #24. If there is no author or organization, a sorting +key is required for sorting styles. It might be a good idea to include +month and year fields as well. +@electronic{IEEEexample:softonline, + title = "Ucb/lbnl/vint Network Simulator---ns (Version 2)", + url = "http://www-mash.cs.berkeley.edu/ns/", + key = "ns" +} + + +misc for a German regulation +In German, the first letters of nouns are capitalized, so we do so here. +From the June 2002 issue of "IEEE Journal in Selected Areas in +Communication", page 892, reference #9. +@misc{IEEEexample:miscgermanreg, + title = "{M}essung von {S}t{\"o}rfeldern an {A}nlagen + und {L}eitungen der {T}elekommunikation im + {F}requenzbereich 9 {kHz} bis 3 {GHz}", + language = "german", + howpublished = "{M}e{\ss}vorschrift {R}eg {TP} {MV} 05", + organization = "Regulierungsbeh{\"o}rde f{\"u}r {T}elekommunikation und + {P}ost ({R}eg {TP})" +} + + + +Ways to handle things like CCSDS's Blue Books +journal article with a URL. However, this is not a very good approach +because the Blue Books are not really journals and the author field has +to be abused. +From the June 2002 issue of "IEEE Transactions on Information Theory", +page 1461, reference #7. +@article{IEEEexample:bluebookarticle, + author = "{Consulative Committee for Space Data Systems (CCSDS)}", + title = "Telemetry Channel Coding", + journal = "Blue Book", + number = "4", + year = "1999", + url = "http://www.ccsds.org/documents/pdf/CCSDS-101.0-B-4.pdf" +} + + +CCSDS's Blue Book handled as a book +However, it is not a good idea to have to use the author field for +an organization (done here because the book entry type requires an +author field). +@book{IEEEexample:bluebookbook, + author = "{Consulative Committee for Space Data Systems (CCSDS)}", + title = "Telemetry Channel Coding", + series = "Blue Book", + number = "4", + publisher = "{CCSDS}", + address = "Newport Beach, {CA}", + year = "1999", + url = "http://www.ccsds.org/documents/pdf/CCSDS-101.0-B-4.pdf" +} + + +CCSDS's Blue Book handled as a manual +This is a much better approach, but uses the howpublished field. +@manual{IEEEexample:bluebookmanual, + title = "Telemetry Channel Coding", + howpublished = "ser. Blue Book, No. 4", + organization = "Consulative Committee for Space Data Systems (CCSDS)", + address = "Newport Beach, CA", + year = "1999", + url = "http://www.ccsds.org/documents/pdf/CCSDS-101.0-B-4.pdf" +} + + + +CCSDS's Blue Book handled as a standard +Probably the best approach for this particular case because the work +is standard related. Note that IEEE does not display the address for +standards. +@standard{IEEEexample:bluebookstandard, + title = "Telemetry Channel Coding", + howpublished = "ser. Blue Book, No. 4", + organization = "Consulative Committee for Space Data Systems (CCSDS)", + address = "Newport Beach, CA", + type = "Recommendation for Space Data System Standard", + number = "101.0-B-4", + month = May, + year = "1999", + url = "http://www.ccsds.org/documents/pdf/CCSDS-101.0-B-4.pdf" +} + + + + + + + + +An example of a IEEEtran control entry which can change some IEEEtran.bst +settings. An entry like this must be cited via \bstctlcite{} command +before the first real \cite{}. The same entry key cannot be called twice +(just like multiple \cite{} of the same entry key place only one entry +in the bibliography.) +The available control fields are: + +CTLuse_article_number +"no" turns off the display of the number for articles. +"yes" enables + +CTLuse_paper +"no" turns off the display of the paper and type fields in inproceedings. +"yes" enables + +CTLuse_forced_etal +"no" turns off the forced use of "et al." +"yes" enables + +CTLmax_names_forced_etal +The maximum number of names that can be present beyond which an "et al." +usage is forced. Be sure that CTLnames_show_etal (below) +is not greater than this value! + +CTLnames_show_etal +The number of names that will be shown with a forced "et al.". +Must be less than or equal to CTLmax_names_forced_etal + +CTLuse_alt_spacing +"no" turns off the alternate interword spacing for entries with URLs. +"yes" enables + +CTLalt_stretch_factor +If alternate interword spacing for entries with URLs is enabled, this is +the interword spacing stretch factor that will be used. For example, the +default "4" here means that the interword spacing in entries with URLs can +stretch to four times normal. Does not have to be an integer. + +CTLdash_repeated_names +"no" turns off the "dashification" of repeated (i.e., identical to those +of the previous entry) names. IEEE normally does this. +"yes" enables + +CTLname_format_string +The name format control string as explained in the BibTeX style hacking +guide. +IEEE style "{f.~}{vv~}{ll}{, jj}" is the default, + +CTLname_latex_cmd +A LaTeX command that each name will be fed to (e.g., "\textsc"). +Leave empty if no special font is desired for the names. +The default is empty. + +CTLname_url_prefix +The prefix text used before URLs. +The default is "[Online]. Available:" A space will be inserted after this +text. If this space is not wanted, just use \relax at the end of the +prefix text. + + +Those fields that are not to be changed can be left out. +@IEEEtranBSTCTL{IEEEexample:BSTcontrol, + CTLuse_article_number = "yes", + CTLuse_paper = "yes", + CTLuse_forced_etal = "no", + CTLmax_names_forced_etal = "10", + CTLnames_show_etal = "1", + CTLuse_alt_spacing = "yes", + CTLalt_stretch_factor = "4", + CTLdash_repeated_names = "yes", + CTLname_format_string = "{f.~}{vv~}{ll}{, jj}", + CTLname_latex_cmd = "", + CTLname_url_prefix = "[Online]. Available:" +} + + diff --git a/standard/Report/IEEEtranBST2/IEEEfull.bib b/standard/Report/IEEEtranBST2/IEEEfull.bib new file mode 100644 index 0000000000000000000000000000000000000000..4c3710d0cca5eb85b793111e2333924d1f2a9cf9 --- /dev/null +++ b/standard/Report/IEEEtranBST2/IEEEfull.bib @@ -0,0 +1,419 @@ + +IEEEfull.bib +V1.12 (2007/01/11) +Copyright (c) 2002-2007 by Michael Shell +See: http://www.michaelshell.org/ +for current contact information. + +BibTeX bibliography string definitions of the FULL titles of +IEEE journals and magazines and online publications. + +This file is designed for bibliography styles that require +full-length titles and is not for use in bibliographies that +abbreviate titles. + +Support sites: +http://www.michaelshell.org/tex/ieeetran/ +http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/ +and/or +http://www.ieee.org/ + +Special thanks to Laura Hyslop and ken Rawson of IEEE for their help +in obtaining the information needed to compile this file. Also, +Volker Kuhlmann and Moritz Borgmann kindly provided some corrections +and additions. + +************************************************************************* +Legal Notice: +This code is offered as-is without any warranty either expressed or +implied; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE! +User assumes all risk. +In no event shall IEEE or any contributor to this code be liable for +any damages or losses, including, but not limited to, incidental, +consequential, or any other damages, resulting from the use or misuse +of any information contained here. + +All comments are the opinions of their respective authors and are not +necessarily endorsed by the IEEE. + +This work is distributed under the LaTeX Project Public License (LPPL) +( http://www.latex-project.org/ ) version 1.3, and may be freely used, +distributed and modified. A copy of the LPPL, version 1.3, is included +in the base LaTeX documentation of all distributions of LaTeX released +2003/12/01 or later. +Retain all contribution notices and credits. +** Modified files should be clearly indicated as such, including ** +** renaming them and changing author support contact information. ** + +File list of work: IEEEabrv.bib, IEEEfull.bib, IEEEexample.bib, + IEEEtran.bst, IEEEtranS.bst, IEEEtranSA.bst, + IEEEtranN.bst, IEEEtranSN.bst, IEEEtran_bst_HOWTO.pdf +************************************************************************* + + +USAGE: + +\bibliographystyle{mybstfile} +\bibliography{IEEEfull,mybibfile} + +where the IEEE titles in the .bib database entries use the strings +defined here. e.g., + + + journal = IEEE_J_AC, + + +to yield "{IEEE} Transactions on Automatic Control" + + +WARNING: IEEE uses abbreviated journal titles in their bibliographies! +Because this file provides the full titles, you should NOT use this file +for work that is to be submitted to the IEEE. + +For IEEE work, you should use the abbreviated titles provided in the +companion file, IEEEabrv.bib. + + +** NOTES ** + + 1. Journals have been grouped according to subject in order to make it + easier to locate and extract the definitions for related journals - + as most works use references that are confined to a single topic. + Magazines are listed in straight alphabetical order. + + 2. String names are closely based on IEEE's own internal acronyms. + + 3. Older, out-of-print IEEE titles are included (but not including titles + dating prior to IEEE's formation from the IRE and AIEE in 1963). + + + + + + +IEEE Journals + + + +aerospace and military +@STRING{IEEE_J_AES = "{IEEE} Transactions on Aerospace and Electronic Systems"} +@STRING{IEEE_J_ANE = "{IEEE} Transactions on Aerospace and Navigational Electronics"} +@STRING{IEEE_J_ANNE = "{IEEE} Transactions on Aeronautical and Navigational Electronics"} +@STRING{IEEE_J_AS = "{IEEE} Transactions on Aerospace"} +@STRING{IEEE_J_AIRE = "{IEEE} Transactions on Airborne Electronics"} +@STRING{IEEE_J_MIL = "{IEEE} Transactions on Military Electronics"} + + + +autos, transportation and vehicles (non-aerospace) +@STRING{IEEE_J_ITS = "{IEEE} Transactions on Intelligent Transportation Systems"} +@STRING{IEEE_J_VT = "{IEEE} Transactions on Vehicular Technology"} +@STRING{IEEE_J_VC = "{IEEE} Transactions on Vehicular Communications"} + + + +circuits, signals, systems, audio and controls +@STRING{IEEE_J_SPL = "{IEEE} Signal Processing Letters"} +@STRING{IEEE_J_ASSP = "{IEEE} Transactions on Acoustics, Speech, and Signal Processing"} +@STRING{IEEE_J_AU = "{IEEE} Transactions on Audio"} +@STRING{IEEE_J_AUEA = "{IEEE} Transactions on Audio and Electroacoustics"} +@STRING{IEEE_J_AC = "{IEEE} Transactions on Automatic Control"} +@STRING{IEEE_J_CAS = "{IEEE} Transactions on Circuits and Systems"} +@STRING{IEEE_J_CASVT = "{IEEE} Transactions on Circuits and Systems for Video Technology"} +@STRING{IEEE_J_CASI = "{IEEE} Transactions on Circuits and Systems---Part {I}: Fundamental Theory and Applications"} +@STRING{IEEE_J_CASII = "{IEEE} Transactions on Circuits and Systems---Part {II}: Analog and Digital Signal Processing"} +in 2004 CASI and CASII renamed part title to CASI_RP and CASII_EB, respectively. +@STRING{IEEE_J_CASI_RP = "{IEEE} Transactions on Circuits and Systems---Part {I}: Regular Papers"} +@STRING{IEEE_J_CASII_EB = "{IEEE} Transactions on Circuits and Systems---Part {II}: Express Briefs"} +@STRING{IEEE_J_CT = "{IEEE} Transactions on Circuit Theory"} +@STRING{IEEE_J_CST = "{IEEE} Transactions on Control Systems Technology"} +@STRING{IEEE_J_SP = "{IEEE} Transactions on Signal Processing"} +@STRING{IEEE_J_SU = "{IEEE} Transactions on Sonics and Ultrasonics"} +@STRING{IEEE_J_SAP = "{IEEE} Transactions on Speech and Audio Processing"} +@STRING{IEEE_J_UE = "{IEEE} Transactions on Ultrasonics Engineering"} +@STRING{IEEE_J_UFFC = "{IEEE} Transactions on Ultrasonics, Ferroelectrics, and Frequency Control"} + + + +communications +@STRING{IEEE_J_COML = "{IEEE} Communications Letters"} +@STRING{IEEE_J_JSAC = "{IEEE} Journal on Selected Areas in Communications"} +@STRING{IEEE_J_COM = "{IEEE} Transactions on Communications"} +@STRING{IEEE_J_COMT = "{IEEE} Transactions on Communication Technology"} +@STRING{IEEE_J_WCOM = "{IEEE} Transactions on Wireless Communications"} + + + +components, packaging and manufacturing +@STRING{IEEE_J_ADVP = "{IEEE} Transactions on Advanced Packaging"} +@STRING{IEEE_J_CHMT = "{IEEE} Transactions on Components, Hybrids and Manufacturing Technology"} +@STRING{IEEE_J_CPMTA = "{IEEE} Transactions on Components, Packaging and Manufacturing Technology---Part {A}"} +@STRING{IEEE_J_CPMTB = "{IEEE} Transactions on Components, Packaging and Manufacturing Technology---Part {B}: Advanced Packaging"} +@STRING{IEEE_J_CPMTC = "{IEEE} Transactions on Components, Packaging and Manufacturing Technology---Part {C}: Manufacturing"} +@STRING{IEEE_J_CAPT = "{IEEE} Transactions on Components and Packaging Technology"} +@STRING{IEEE_J_CAPTS = "{IEEE} Transactions on Components and Packaging Technologies"} +@STRING{IEEE_J_CPART = "{IEEE} Transactions on Component Parts"} +@STRING{IEEE_J_EPM = "{IEEE} Transactions on Electronics Packaging Manufacturing"} +@STRING{IEEE_J_MFT = "{IEEE} Transactions on Manufacturing Technology"} +@STRING{IEEE_J_PHP = "{IEEE} Transactions on Parts, Hybrids and Packaging"} +@STRING{IEEE_J_PMP = "{IEEE} Transactions on Parts, Materials and Packaging"} + + + +CAD +@STRING{IEEE_J_TCAD = "{IEEE} Journal on Technology in Computer Aided Design"} +@STRING{IEEE_J_CAD = "{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems"} + + + +coding, data, information, knowledge +@STRING{IEEE_J_IT = "{IEEE} Transactions on Information Theory"} +@STRING{IEEE_J_KDE = "{IEEE} Transactions on Knowledge and Data Engineering"} + + + +computers, computation, networking and software +@STRING{IEEE_J_C = "{IEEE} Transactions on Computers"} +@STRING{IEEE_J_CAL = "{IEEE} Computer Architecture Letters"} +@STRING{IEEE_J_DSC = "{IEEE} Transactions on Dependable and Secure Computing"} +@STRING{IEEE_J_ECOMP = "{IEEE} Transactions on Electronic Computers"} +@STRING{IEEE_J_EVC = "{IEEE} Transactions on Evolutionary Computation"} +@STRING{IEEE_J_FUZZ = "{IEEE} Transactions on Fuzzy Systems"} +@STRING{IEEE_J_IFS = "{IEEE} Transactions on Information Forensics and Security"} +@STRING{IEEE_J_MC = "{IEEE} Transactions on Mobile Computing"} +@STRING{IEEE_J_NET = "{IEEE/ACM} Transactions on Networking"} +@STRING{IEEE_J_NN = "{IEEE} Transactions on Neural Networks"} +@STRING{IEEE_J_PDS = "{IEEE} Transactions on Parallel and Distributed Systems"} +@STRING{IEEE_J_SE = "{IEEE} Transactions on Software Engineering"} + + + +computer graphics, imaging, and multimedia +@STRING{IEEE_J_JDT = "{IEEE/OSA} Journal of Display Technology"} +@STRING{IEEE_J_IP = "{IEEE} Transactions on Image Processing"} +@STRING{IEEE_J_MM = "{IEEE} Transactions on Multimedia"} +@STRING{IEEE_J_VCG = "{IEEE} Transactions on Visualization and Computer Graphics"} + + + +cybernetics, ergonomics, robots, man-machine, and automation +@STRING{IEEE_J_ASE = "{IEEE} Transactions on Automation Science and Engineering"} +@STRING{IEEE_J_JRA = "{IEEE} Journal of Robotics and Automation"} +@STRING{IEEE_J_HFE = "{IEEE} Transactions on Human Factors in Electronics"} +@STRING{IEEE_J_MMS = "{IEEE} Transactions on Man-Machine Systems"} +@STRING{IEEE_J_PAMI = "{IEEE} Transactions on Pattern Analysis and Machine Intelligence"} +in 1989 JRA became RA +in August 2004, RA split into ASE and RO +@STRING{IEEE_J_RA = "{IEEE} Transactions on Robotics and Automation"} +@STRING{IEEE_J_RO = "{IEEE} Transactions on Robotics"} +@STRING{IEEE_J_SMC = "{IEEE} Transactions on Systems, Man, and Cybernetics"} +@STRING{IEEE_J_SMCA = "{IEEE} Transactions on Systems, Man, and Cybernetics---Part {A}: Systems and Humans"} +@STRING{IEEE_J_SMCB = "{IEEE} Transactions on Systems, Man, and Cybernetics---Part {B}: Cybernetics"} +@STRING{IEEE_J_SMCC = "{IEEE} Transactions on Systems, Man, and Cybernetics---Part {C}: Applications and Reviews"} +@STRING{IEEE_J_SSC = "{IEEE} Transactions on Systems Science and Cybernetics"} + + + +earth, wind, fire and water +@STRING{IEEE_J_GE = "{IEEE} Transactions on Geoscience Electronics"} +@STRING{IEEE_J_GRS = "{IEEE} Transactions on Geoscience and Remote Sensing"} +@STRING{IEEE_J_GRSL = "{IEEE} Geoscience and Remote Sensing Letters"} +@STRING{IEEE_J_OE = "{IEEE} Journal of Oceanic Engineering"} + + + +education, engineering, history, IEEE, professional +@STRING{IEEE_J_CJECE = "Canadian Journal of Electrical and Computer Engineering"} +@STRING{IEEE_J_PROC = "Proceedings of the {IEEE}"} +@STRING{IEEE_J_EDU = "{IEEE} Transactions on Education"} +@STRING{IEEE_J_EM = "{IEEE} Transactions on Engineering Management"} +@STRING{IEEE_J_EWS = "{IEEE} Transactions on Engineering Writing and Speech"} +@STRING{IEEE_J_PC = "{IEEE} Transactions on Professional Communication"} + + + +electromagnetics, antennas, EMI, magnetics and microwave +@STRING{IEEE_J_AWPL = "{IEEE} Antennas and Wireless Propagation Letters"} +@STRING{IEEE_J_MGWL = "{IEEE} Microwave and Guided Wave Letters"} +@STRING{IEEE_J_MWCL = "{IEEE} Microwave and Wireless Components Letters"} +@STRING{IEEE_J_AP = "{IEEE} Transactions on Antennas and Propagation"} +@STRING{IEEE_J_EMC = "{IEEE} Transactions on Electromagnetic Compatibility"} +@STRING{IEEE_J_MAG = "{IEEE} Transactions on Magnetics"} +@STRING{IEEE_J_MTT = "{IEEE} Transactions on Microwave Theory and Techniques"} +@STRING{IEEE_J_RFI = "{IEEE} Transactions on Radio Frequency Interference"} +@STRING{IEEE_J_TJMJ = "{IEEE} Translation Journal on Magnetics in Japan"} + + + +energy and power +@STRING{IEEE_J_EC = "{IEEE} Transactions on Energy Conversion"} +@STRING{IEEE_J_PEL = "{IEEE} Power Electronics Letters"} +@STRING{IEEE_J_PWRAS = "{IEEE} Transactions on Power Apparatus and Systems"} +@STRING{IEEE_J_PWRD = "{IEEE} Transactions on Power Delivery"} +@STRING{IEEE_J_PWRE = "{IEEE} Transactions on Power Electronics"} +@STRING{IEEE_J_PWRS = "{IEEE} Transactions on Power Systems"} + + + +industrial, commercial and consumer +@STRING{IEEE_J_APPIND = "{IEEE} Transactions on Applications and Industry"} +@STRING{IEEE_J_BC = "{IEEE} Transactions on Broadcasting"} +@STRING{IEEE_J_BCTV = "{IEEE} Transactions on Broadcast and Television Receivers"} +@STRING{IEEE_J_CE = "{IEEE} Transactions on Consumer Electronics"} +@STRING{IEEE_J_IE = "{IEEE} Transactions on Industrial Electronics"} +@STRING{IEEE_J_IECI = "{IEEE} Transactions on Industrial Electronics and Control Instrumentation"} +@STRING{IEEE_J_IA = "{IEEE} Transactions on Industry Applications"} +@STRING{IEEE_J_IGA = "{IEEE} Transactions on Industry and General Applications"} +@STRING{IEEE_J_IINF = "{IEEE} Transactions on Industrial Informatics"} +@STRING{IEEE_J_PSE = "{IEEE} Journal of Product Safety Engineering"} + + + +instrumentation and measurement +@STRING{IEEE_J_IM = "{IEEE} Transactions on Instrumentation and Measurement"} + + + +insulation and materials +@STRING{IEEE_J_JEM = "{IEEE/TMS} Journal of Electronic Materials"} +@STRING{IEEE_J_DEI = "{IEEE} Transactions on Dielectrics and Electrical Insulation"} +@STRING{IEEE_J_EI = "{IEEE} Transactions on Electrical Insulation"} + + + +mechanical +@STRING{IEEE_J_MECH = "{IEEE/ASME} Transactions on Mechatronics"} +@STRING{IEEE_J_MEMS = "{IEEE/ASME} Journal of Microelectromechanical Systems"} + + + +medical and biological +@STRING{IEEE_J_BME = "{IEEE} Transactions on Biomedical Engineering"} +Note: The B-ME journal later dropped the hyphen and became the BME. +@STRING{IEEE_J_B-ME = "{IEEE} Transactions on Bio-Medical Engineering"} +@STRING{IEEE_J_BMELC = "{IEEE} Transactions on Bio-Medical Electronics"} +@STRING{IEEE_J_CBB = "{IEEE/ACM} Transactions on Computational Biology and Bioinformatics"} +@STRING{IEEE_J_ITBM = "{IEEE} Transactions on Information Technology in Biomedicine"} +@STRING{IEEE_J_ME = "{IEEE} Transactions on Medical Electronics"} +@STRING{IEEE_J_MI = "{IEEE} Transactions on Medical Imaging"} +@STRING{IEEE_J_NB = "{IEEE} Transactions on NanoBioscience"} +@STRING{IEEE_J_NSRE = "{IEEE} Transactions on Neural Systems and Rehabilitation Engineering"} +@STRING{IEEE_J_RE = "{IEEE} Transactions on Rehabilitation Engineering"} + + + +optics, lightwave and photonics +@STRING{IEEE_J_PTL = "{IEEE} Photonics Technology Letters"} +@STRING{IEEE_J_JLT = "{IEEE/OSA} Journal of Lightwave Technology"} + + + +physics, electrons, nanotechnology, nuclear and quantum electronics +@STRING{IEEE_J_EDL = "{IEEE} Electron Device Letters"} +@STRING{IEEE_J_JQE = "{IEEE} Journal of Quantum Electronics"} +@STRING{IEEE_J_JSTQE = "{IEEE} Journal of Selected Topics in Quantum Electronics"} +@STRING{IEEE_J_ED = "{IEEE} Transactions on Electron Devices"} +@STRING{IEEE_J_NANO = "{IEEE} Transactions on Nanotechnology"} +@STRING{IEEE_J_NS = "{IEEE} Transactions on Nuclear Science"} +@STRING{IEEE_J_PS = "{IEEE} Transactions on Plasma Science"} + + + +reliability +@STRING{IEEE_J_DMR = "{IEEE} Transactions on Device and Materials Reliability"} +@STRING{IEEE_J_R = "{IEEE} Transactions on Reliability"} + + + +semiconductors, superconductors, electrochemical and solid state +@STRING{IEEE_J_ESSL = "{IEEE/ECS} Electrochemical and Solid-State Letters"} +@STRING{IEEE_J_JSSC = "{IEEE} Journal of Solid-State Circuits"} +@STRING{IEEE_J_ASC = "{IEEE} Transactions on Applied Superconductivity"} +@STRING{IEEE_J_SM = "{IEEE} Transactions on Semiconductor Manufacturing"} + + + +sensors +@STRING{IEEE_J_SENSOR = "{IEEE} Sensors Journal"} + + + +VLSI +@STRING{IEEE_J_VLSI = "{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems"} + + + + + + +IEEE Magazines + + + +@STRING{IEEE_M_AES = "{IEEE} Aerospace and Electronics Systems Magazine"} +@STRING{IEEE_M_HIST = "{IEEE} Annals of the History of Computing"} +@STRING{IEEE_M_AP = "{IEEE} Antennas and Propagation Magazine"} +@STRING{IEEE_M_ASSP = "{IEEE} {ASSP} Magazine"} +@STRING{IEEE_M_CD = "{IEEE} Circuits and Devices Magazine"} +@STRING{IEEE_M_CAS = "{IEEE} Circuits and Systems Magazine"} +@STRING{IEEE_M_COM = "{IEEE} Communications Magazine"} +@STRING{IEEE_M_COMSOC = "{IEEE} Communications Society Magazine"} +@STRING{IEEE_M_CIM = "{IEEE} Computational Intelligence Magazine"} +CSEM changed to CSE in 1999 +@STRING{IEEE_M_CSE = "{IEEE} Computing in Science and Engineering"} +@STRING{IEEE_M_CSEM = "{IEEE} Computational Science and Engineering Magazine"} +@STRING{IEEE_M_C = "{IEEE} Computer"} +@STRING{IEEE_M_CAP = "{IEEE} Computer Applications in Power"} +@STRING{IEEE_M_CGA = "{IEEE} Computer Graphics and Applications"} +@STRING{IEEE_M_CONC = "{IEEE} Concurrency"} +@STRING{IEEE_M_CS = "{IEEE} Control Systems Magazine"} +@STRING{IEEE_M_DTC = "{IEEE} Design and Test of Computers"} +@STRING{IEEE_M_EI = "{IEEE} Electrical Insulation Magazine"} +@STRING{IEEE_M_ETR = "{IEEE} ElectroTechnology Review"} +@STRING{IEEE_M_EMB = "{IEEE} Engineering in Medicine and Biology Magazine"} +@STRING{IEEE_M_EMR = "{IEEE} Engineering Management Review"} +@STRING{IEEE_M_EXP = "{IEEE} Expert"} +@STRING{IEEE_M_IA = "{IEEE} Industry Applications Magazine"} +@STRING{IEEE_M_IM = "{IEEE} Instrumentation and Measurement Magazine"} +@STRING{IEEE_M_IS = "{IEEE} Intelligent Systems"} +@STRING{IEEE_M_IC = "{IEEE} Internet Computing"} +@STRING{IEEE_M_ITP = "{IEEE} {IT} Professional"} +@STRING{IEEE_M_MICRO = "{IEEE} Micro"} +@STRING{IEEE_M_MW = "{IEEE} Microwave Magazine"} +@STRING{IEEE_M_MM = "{IEEE} Multimedia"} +@STRING{IEEE_M_NET = "{IEEE} Network"} +@STRING{IEEE_M_PCOM = "{IEEE} Personal Communications Magazine"} +@STRING{IEEE_M_POT = "{IEEE} Potentials"} +CAP and PER merged to form PE in 2003 +@STRING{IEEE_M_PE = "{IEEE} Power and Energy Magazine"} +@STRING{IEEE_M_PER = "{IEEE} Power Engineering Review"} +@STRING{IEEE_M_PVC = "{IEEE} Pervasive Computing"} +@STRING{IEEE_M_RA = "{IEEE} Robotics and Automation Magazine"} +@STRING{IEEE_M_SAP = "{IEEE} Security and Privacy"} +@STRING{IEEE_M_SP = "{IEEE} Signal Processing Magazine"} +@STRING{IEEE_M_S = "{IEEE} Software"} +@STRING{IEEE_M_SPECT = "{IEEE} Spectrum"} +@STRING{IEEE_M_TS = "{IEEE} Technology and Society Magazine"} +@STRING{IEEE_M_VT = "{IEEE} Vehicular Technology Magazine"} +@STRING{IEEE_M_WC = "{IEEE} Wireless Communications Magazine"} +@STRING{IEEE_M_TODAY = "Today's Engineer"} + + + + + + +IEEE Online Publications + + + +@STRING{IEEE_O_CSTO = "{IEEE} Communications Surveys and Tutorials"} +@STRING{IEEE_O_DSO = "{IEEE} Distributed Systems Online"} + + + + + +-- +EOF diff --git a/standard/Report/IEEEtranBST2/IEEEtran.bst b/standard/Report/IEEEtranBST2/IEEEtran.bst new file mode 100644 index 0000000000000000000000000000000000000000..4b841273417464521a85f05aea0f20b0cbe5aaf3 --- /dev/null +++ b/standard/Report/IEEEtranBST2/IEEEtran.bst @@ -0,0 +1,2417 @@ +%% +%% IEEEtran.bst +%% BibTeX Bibliography Style file for IEEE Journals and Conferences (unsorted) +%% Version 1.12 (2007/01/11) +%% +%% Copyright (c) 2003-2007 Michael Shell +%% +%% Original starting code base and algorithms obtained from the output of +%% Patrick W. Daly's makebst package as well as from prior versions of +%% IEEE BibTeX styles: +%% +%% 1. Howard Trickey and Oren Patashnik's ieeetr.bst (1985/1988) +%% 2. Silvano Balemi and Richard H. Roy's IEEEbib.bst (1993) +%% +%% Support sites: +%% http://www.michaelshell.org/tex/ieeetran/ +%% http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/ +%% and/or +%% http://www.ieee.org/ +%% +%% For use with BibTeX version 0.99a or later +%% +%% This is a numerical citation style. +%% +%%************************************************************************* +%% Legal Notice: +%% This code is offered as-is without any warranty either expressed or +%% implied; without even the implied warranty of MERCHANTABILITY or +%% FITNESS FOR A PARTICULAR PURPOSE! +%% User assumes all risk. +%% In no event shall IEEE or any contributor to this code be liable for +%% any damages or losses, including, but not limited to, incidental, +%% consequential, or any other damages, resulting from the use or misuse +%% of any information contained here. +%% +%% All comments are the opinions of their respective authors and are not +%% necessarily endorsed by the IEEE. +%% +%% This work is distributed under the LaTeX Project Public License (LPPL) +%% ( http://www.latex-project.org/ ) version 1.3, and may be freely used, +%% distributed and modified. A copy of the LPPL, version 1.3, is included +%% in the base LaTeX documentation of all distributions of LaTeX released +%% 2003/12/01 or later. +%% Retain all contribution notices and credits. +%% ** Modified files should be clearly indicated as such, including ** +%% ** renaming them and changing author support contact information. ** +%% +%% File list of work: IEEEabrv.bib, IEEEfull.bib, IEEEexample.bib, +%% IEEEtran.bst, IEEEtranS.bst, IEEEtranSA.bst, +%% IEEEtranN.bst, IEEEtranSN.bst, IEEEtran_bst_HOWTO.pdf +%%************************************************************************* +% +% +% Changelog: +% +% 1.00 (2002/08/13) Initial release +% +% 1.10 (2002/09/27) +% 1. Corrected minor bug for improperly formed warning message when a +% book was not given a title. Thanks to Ming Kin Lai for reporting this. +% 2. Added support for CTLname_format_string and CTLname_latex_cmd fields +% in the BST control entry type. +% +% 1.11 (2003/04/02) +% 1. Fixed bug with URLs containing underscores when using url.sty. Thanks +% to Ming Kin Lai for reporting this. +% +% 1.12 (2007/01/11) +% 1. Fixed bug with unwanted comma before "et al." when an entry contained +% more than two author names. Thanks to Pallav Gupta for reporting this. +% 2. Fixed bug with anomalous closing quote in tech reports that have a +% type, but without a number or address. Thanks to Mehrdad Mirreza for +% reporting this. +% 3. Use braces in \providecommand in begin.bib to better support +% latex2html. TeX style length assignments OK with recent versions +% of latex2html - 1.71 (2002/2/1) or later is strongly recommended. +% Use of the language field still causes trouble with latex2html. +% Thanks to Federico Beffa for reporting this. +% 4. Added IEEEtran.bst ID and version comment string to .bbl output. +% 5. Provide a \BIBdecl hook that allows the user to execute commands +% just prior to the first entry. +% 6. Use default urlstyle (is using url.sty) of "same" rather than rm to +% better work with a wider variety of bibliography styles. +% 7. Changed month abbreviations from Sept., July and June to Sep., Jul., +% and Jun., respectively, as IEEE now does. Thanks to Moritz Borgmann +% for reporting this. +% 8. Control entry types should not be considered when calculating longest +% label width. +% 9. Added alias www for electronic/online. +% 10. Added CTLname_url_prefix control entry type. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% DEFAULTS FOR THE CONTROLS OF THE BST STYLE %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% These are the defaults for the user adjustable controls. The values used +% here can be overridden by the user via IEEEtranBSTCTL entry type. + +% NOTE: The recommended LaTeX command to invoke a control entry type is: +% +%\makeatletter +%\def\bstctlcite{\@ifnextchar[{\@bstctlcite}{\@bstctlcite[@auxout]}} +%\def\@bstctlcite[#1]#2{\@bsphack +% \@for\@citeb:=#2\do{% +% \edef\@citeb{\expandafter\@firstofone\@citeb}% +% \if@filesw\immediate\write\csname #1\endcsname{\string\citation{\@citeb}}\fi}% +% \@esphack} +%\makeatother +% +% It is called at the start of the document, before the first \cite, like: +% \bstctlcite{IEEEexample:BSTcontrol} +% +% IEEEtran.cls V1.6 and later does provide this command. + + + +% #0 turns off the display of the number for articles. +% #1 enables +FUNCTION {default.is.use.number.for.article} { #1 } + + +% #0 turns off the display of the paper and type fields in @inproceedings. +% #1 enables +FUNCTION {default.is.use.paper} { #1 } + + +% #0 turns off the forced use of "et al." +% #1 enables +FUNCTION {default.is.forced.et.al} { #0 } + +% The maximum number of names that can be present beyond which an "et al." +% usage is forced. Be sure that num.names.shown.with.forced.et.al (below) +% is not greater than this value! +% Note: There are many instances of references in IEEE journals which have +% a very large number of authors as well as instances in which "et al." is +% used profusely. +FUNCTION {default.max.num.names.before.forced.et.al} { #10 } + +% The number of names that will be shown with a forced "et al.". +% Must be less than or equal to max.num.names.before.forced.et.al +FUNCTION {default.num.names.shown.with.forced.et.al} { #1 } + + +% #0 turns off the alternate interword spacing for entries with URLs. +% #1 enables +FUNCTION {default.is.use.alt.interword.spacing} { #1 } + +% If alternate interword spacing for entries with URLs is enabled, this is +% the interword spacing stretch factor that will be used. For example, the +% default "4" here means that the interword spacing in entries with URLs can +% stretch to four times normal. Does not have to be an integer. Note that +% the value specified here can be overridden by the user in their LaTeX +% code via a command such as: +% "\providecommand\BIBentryALTinterwordstretchfactor{1.5}" in addition to +% that via the IEEEtranBSTCTL entry type. +FUNCTION {default.ALTinterwordstretchfactor} { "4" } + + +% #0 turns off the "dashification" of repeated (i.e., identical to those +% of the previous entry) names. IEEE normally does this. +% #1 enables +FUNCTION {default.is.dash.repeated.names} { #1 } + + +% The default name format control string. +FUNCTION {default.name.format.string}{ "{f.~}{vv~}{ll}{, jj}" } + + +% The default LaTeX font command for the names. +FUNCTION {default.name.latex.cmd}{ "" } + + +% The default URL prefix. +FUNCTION {default.name.url.prefix}{ "[Online]. Available:" } + + +% Other controls that cannot be accessed via IEEEtranBSTCTL entry type. + +% #0 turns off the terminal startup banner/completed message so as to +% operate more quietly. +% #1 enables +FUNCTION {is.print.banners.to.terminal} { #1 } + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% FILE VERSION AND BANNER %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION{bst.file.version} { "1.12" } +FUNCTION{bst.file.date} { "2007/01/11" } +FUNCTION{bst.file.website} { "http://www.michaelshell.org/tex/ieeetran/bibtex/" } + +FUNCTION {banner.message} +{ is.print.banners.to.terminal + { "-- IEEEtran.bst version" " " * bst.file.version * + " (" * bst.file.date * ") " * "by Michael Shell." * + top$ + "-- " bst.file.website * + top$ + "-- See the " quote$ * "IEEEtran_bst_HOWTO.pdf" * quote$ * " manual for usage information." * + top$ + } + { skip$ } + if$ +} + +FUNCTION {completed.message} +{ is.print.banners.to.terminal + { "" + top$ + "Done." + top$ + } + { skip$ } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%%% +%% STRING CONSTANTS %% +%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {bbl.and}{ "and" } +FUNCTION {bbl.etal}{ "et~al." } +FUNCTION {bbl.editors}{ "eds." } +FUNCTION {bbl.editor}{ "ed." } +FUNCTION {bbl.edition}{ "ed." } +FUNCTION {bbl.volume}{ "vol." } +FUNCTION {bbl.of}{ "of" } +FUNCTION {bbl.number}{ "no." } +FUNCTION {bbl.in}{ "in" } +FUNCTION {bbl.pages}{ "pp." } +FUNCTION {bbl.page}{ "p." } +FUNCTION {bbl.chapter}{ "ch." } +FUNCTION {bbl.paper}{ "paper" } +FUNCTION {bbl.part}{ "pt." } +FUNCTION {bbl.patent}{ "Patent" } +FUNCTION {bbl.patentUS}{ "U.S." } +FUNCTION {bbl.revision}{ "Rev." } +FUNCTION {bbl.series}{ "ser." } +FUNCTION {bbl.standard}{ "Std." } +FUNCTION {bbl.techrep}{ "Tech. Rep." } +FUNCTION {bbl.mthesis}{ "Master's thesis" } +FUNCTION {bbl.phdthesis}{ "Ph.D. dissertation" } +FUNCTION {bbl.st}{ "st" } +FUNCTION {bbl.nd}{ "nd" } +FUNCTION {bbl.rd}{ "rd" } +FUNCTION {bbl.th}{ "th" } + + +% This is the LaTeX spacer that is used when a larger than normal space +% is called for (such as just before the address:publisher). +FUNCTION {large.space} { "\hskip 1em plus 0.5em minus 0.4em\relax " } + +% The LaTeX code for dashes that are used to represent repeated names. +% Note: Some older IEEE journals used something like +% "\rule{0.275in}{0.5pt}\," which is fairly thick and runs right along +% the baseline. However, IEEE now uses a thinner, above baseline, +% six dash long sequence. +FUNCTION {repeated.name.dashes} { "------" } + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% PREDEFINED STRING MACROS %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +MACRO {jan} {"Jan."} +MACRO {feb} {"Feb."} +MACRO {mar} {"Mar."} +MACRO {apr} {"Apr."} +MACRO {may} {"May"} +MACRO {jun} {"Jun."} +MACRO {jul} {"Jul."} +MACRO {aug} {"Aug."} +MACRO {sep} {"Sep."} +MACRO {oct} {"Oct."} +MACRO {nov} {"Nov."} +MACRO {dec} {"Dec."} + + + +%%%%%%%%%%%%%%%%%% +%% ENTRY FIELDS %% +%%%%%%%%%%%%%%%%%% + +ENTRY + { address + assignee + author + booktitle + chapter + day + dayfiled + edition + editor + howpublished + institution + intype + journal + key + language + month + monthfiled + nationality + note + number + organization + pages + paper + publisher + school + series + revision + title + type + url + volume + year + yearfiled + CTLuse_article_number + CTLuse_paper + CTLuse_forced_etal + CTLmax_names_forced_etal + CTLnames_show_etal + CTLuse_alt_spacing + CTLalt_stretch_factor + CTLdash_repeated_names + CTLname_format_string + CTLname_latex_cmd + CTLname_url_prefix + } + {} + { label } + + + + +%%%%%%%%%%%%%%%%%%%%%%% +%% INTEGER VARIABLES %% +%%%%%%%%%%%%%%%%%%%%%%% + +INTEGERS { prev.status.punct this.status.punct punct.std + punct.no punct.comma punct.period + prev.status.space this.status.space space.std + space.no space.normal space.large + prev.status.quote this.status.quote quote.std + quote.no quote.close + prev.status.nline this.status.nline nline.std + nline.no nline.newblock + status.cap cap.std + cap.no cap.yes} + +INTEGERS { longest.label.width multiresult nameptr namesleft number.label numnames } + +INTEGERS { is.use.number.for.article + is.use.paper + is.forced.et.al + max.num.names.before.forced.et.al + num.names.shown.with.forced.et.al + is.use.alt.interword.spacing + is.dash.repeated.names} + + +%%%%%%%%%%%%%%%%%%%%%% +%% STRING VARIABLES %% +%%%%%%%%%%%%%%%%%%%%%% + +STRINGS { bibinfo + longest.label + oldname + s + t + ALTinterwordstretchfactor + name.format.string + name.latex.cmd + name.url.prefix} + + + + +%%%%%%%%%%%%%%%%%%%%%%%%% +%% LOW LEVEL FUNCTIONS %% +%%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {initialize.controls} +{ default.is.use.number.for.article 'is.use.number.for.article := + default.is.use.paper 'is.use.paper := + default.is.forced.et.al 'is.forced.et.al := + default.max.num.names.before.forced.et.al 'max.num.names.before.forced.et.al := + default.num.names.shown.with.forced.et.al 'num.names.shown.with.forced.et.al := + default.is.use.alt.interword.spacing 'is.use.alt.interword.spacing := + default.is.dash.repeated.names 'is.dash.repeated.names := + default.ALTinterwordstretchfactor 'ALTinterwordstretchfactor := + default.name.format.string 'name.format.string := + default.name.latex.cmd 'name.latex.cmd := + default.name.url.prefix 'name.url.prefix := +} + + +% This IEEEtran.bst features a very powerful and flexible mechanism for +% controlling the capitalization, punctuation, spacing, quotation, and +% newlines of the formatted entry fields. (Note: IEEEtran.bst does not need +% or use the newline/newblock feature, but it has been implemented for +% possible future use.) The output states of IEEEtran.bst consist of +% multiple independent attributes and, as such, can be thought of as being +% vectors, rather than the simple scalar values ("before.all", +% "mid.sentence", etc.) used in most other .bst files. +% +% The more flexible and complex design used here was motivated in part by +% IEEE's rather unusual bibliography style. For example, IEEE ends the +% previous field item with a period and large space prior to the publisher +% address; the @electronic entry types use periods as inter-item punctuation +% rather than the commas used by the other entry types; and URLs are never +% followed by periods even though they are the last item in the entry. +% Although it is possible to accommodate these features with the conventional +% output state system, the seemingly endless exceptions make for convoluted, +% unreliable and difficult to maintain code. +% +% IEEEtran.bst's output state system can be easily understood via a simple +% illustration of two most recently formatted entry fields (on the stack): +% +% CURRENT_ITEM +% "PREVIOUS_ITEM +% +% which, in this example, is to eventually appear in the bibliography as: +% +% "PREVIOUS_ITEM," CURRENT_ITEM +% +% It is the job of the output routine to take the previous item off of the +% stack (while leaving the current item at the top of the stack), apply its +% trailing punctuation (including closing quote marks) and spacing, and then +% to write the result to BibTeX's output buffer: +% +% "PREVIOUS_ITEM," +% +% Punctuation (and spacing) between items is often determined by both of the +% items rather than just the first one. The presence of quotation marks +% further complicates the situation because, in standard English, trailing +% punctuation marks are supposed to be contained within the quotes. +% +% IEEEtran.bst maintains two output state (aka "status") vectors which +% correspond to the previous and current (aka "this") items. Each vector +% consists of several independent attributes which track punctuation, +% spacing, quotation, and newlines. Capitalization status is handled by a +% separate scalar because the format routines, not the output routine, +% handle capitalization and, therefore, there is no need to maintain the +% capitalization attribute for both the "previous" and "this" items. +% +% When a format routine adds a new item, it copies the current output status +% vector to the previous output status vector and (usually) resets the +% current (this) output status vector to a "standard status" vector. Using a +% "standard status" vector in this way allows us to redefine what we mean by +% "standard status" at the start of each entry handler and reuse the same +% format routines under the various inter-item separation schemes. For +% example, the standard status vector for the @book entry type may use +% commas for item separators, while the @electronic type may use periods, +% yet both entry handlers exploit many of the exact same format routines. +% +% Because format routines have write access to the output status vector of +% the previous item, they can override the punctuation choices of the +% previous format routine! Therefore, it becomes trivial to implement rules +% such as "Always use a period and a large space before the publisher." By +% pushing the generation of the closing quote mark to the output routine, we +% avoid all the problems caused by having to close a quote before having all +% the information required to determine what the punctuation should be. +% +% The IEEEtran.bst output state system can easily be expanded if needed. +% For instance, it is easy to add a "space.tie" attribute value if the +% bibliography rules mandate that two items have to be joined with an +% unbreakable space. + +FUNCTION {initialize.status.constants} +{ #0 'punct.no := + #1 'punct.comma := + #2 'punct.period := + #0 'space.no := + #1 'space.normal := + #2 'space.large := + #0 'quote.no := + #1 'quote.close := + #0 'cap.no := + #1 'cap.yes := + #0 'nline.no := + #1 'nline.newblock := +} + +FUNCTION {std.status.using.comma} +{ punct.comma 'punct.std := + space.normal 'space.std := + quote.no 'quote.std := + nline.no 'nline.std := + cap.no 'cap.std := +} + +FUNCTION {std.status.using.period} +{ punct.period 'punct.std := + space.normal 'space.std := + quote.no 'quote.std := + nline.no 'nline.std := + cap.yes 'cap.std := +} + +FUNCTION {initialize.prev.this.status} +{ punct.no 'prev.status.punct := + space.no 'prev.status.space := + quote.no 'prev.status.quote := + nline.no 'prev.status.nline := + punct.no 'this.status.punct := + space.no 'this.status.space := + quote.no 'this.status.quote := + nline.no 'this.status.nline := + cap.yes 'status.cap := +} + +FUNCTION {this.status.std} +{ punct.std 'this.status.punct := + space.std 'this.status.space := + quote.std 'this.status.quote := + nline.std 'this.status.nline := +} + +FUNCTION {cap.status.std}{ cap.std 'status.cap := } + +FUNCTION {this.to.prev.status} +{ this.status.punct 'prev.status.punct := + this.status.space 'prev.status.space := + this.status.quote 'prev.status.quote := + this.status.nline 'prev.status.nline := +} + + +FUNCTION {not} +{ { #0 } + { #1 } + if$ +} + +FUNCTION {and} +{ { skip$ } + { pop$ #0 } + if$ +} + +FUNCTION {or} +{ { pop$ #1 } + { skip$ } + if$ +} + + +% convert the strings "yes" or "no" to #1 or #0 respectively +FUNCTION {yes.no.to.int} +{ "l" change.case$ duplicate$ + "yes" = + { pop$ #1 } + { duplicate$ "no" = + { pop$ #0 } + { "unknown boolean " quote$ * swap$ * quote$ * + " in " * cite$ * warning$ + #0 + } + if$ + } + if$ +} + + +% pushes true if the single char string on the stack is in the +% range of "0" to "9" +FUNCTION {is.num} +{ chr.to.int$ + duplicate$ "0" chr.to.int$ < not + swap$ "9" chr.to.int$ > not and +} + +% multiplies the integer on the stack by a factor of 10 +FUNCTION {bump.int.mag} +{ #0 'multiresult := + { duplicate$ #0 > } + { #1 - + multiresult #10 + + 'multiresult := + } + while$ +pop$ +multiresult +} + +% converts a single character string on the stack to an integer +FUNCTION {char.to.integer} +{ duplicate$ + is.num + { chr.to.int$ "0" chr.to.int$ - } + {"noninteger character " quote$ * swap$ * quote$ * + " in integer field of " * cite$ * warning$ + #0 + } + if$ +} + +% converts a string on the stack to an integer +FUNCTION {string.to.integer} +{ duplicate$ text.length$ 'namesleft := + #1 'nameptr := + #0 'numnames := + { nameptr namesleft > not } + { duplicate$ nameptr #1 substring$ + char.to.integer numnames bump.int.mag + + 'numnames := + nameptr #1 + + 'nameptr := + } + while$ +pop$ +numnames +} + + + + +% The output routines write out the *next* to the top (previous) item on the +% stack, adding punctuation and such as needed. Since IEEEtran.bst maintains +% the output status for the top two items on the stack, these output +% routines have to consider the previous output status (which corresponds to +% the item that is being output). Full independent control of punctuation, +% closing quote marks, spacing, and newblock is provided. +% +% "output.nonnull" does not check for the presence of a previous empty +% item. +% +% "output" does check for the presence of a previous empty item and will +% remove an empty item rather than outputing it. +% +% "output.warn" is like "output", but will issue a warning if it detects +% an empty item. + +FUNCTION {output.nonnull} +{ swap$ + prev.status.punct punct.comma = + { "," * } + { skip$ } + if$ + prev.status.punct punct.period = + { add.period$ } + { skip$ } + if$ + prev.status.quote quote.close = + { "''" * } + { skip$ } + if$ + prev.status.space space.normal = + { " " * } + { skip$ } + if$ + prev.status.space space.large = + { large.space * } + { skip$ } + if$ + write$ + prev.status.nline nline.newblock = + { newline$ "\newblock " write$ } + { skip$ } + if$ +} + +FUNCTION {output} +{ duplicate$ empty$ + 'pop$ + 'output.nonnull + if$ +} + +FUNCTION {output.warn} +{ 't := + duplicate$ empty$ + { pop$ "empty " t * " in " * cite$ * warning$ } + 'output.nonnull + if$ +} + +% "fin.entry" is the output routine that handles the last item of the entry +% (which will be on the top of the stack when "fin.entry" is called). + +FUNCTION {fin.entry} +{ this.status.punct punct.no = + { skip$ } + { add.period$ } + if$ + this.status.quote quote.close = + { "''" * } + { skip$ } + if$ +write$ +newline$ +} + + +FUNCTION {is.last.char.not.punct} +{ duplicate$ + "}" * add.period$ + #-1 #1 substring$ "." = +} + +FUNCTION {is.multiple.pages} +{ 't := + #0 'multiresult := + { multiresult not + t empty$ not + and + } + { t #1 #1 substring$ + duplicate$ "-" = + swap$ duplicate$ "," = + swap$ "+" = + or or + { #1 'multiresult := } + { t #2 global.max$ substring$ 't := } + if$ + } + while$ + multiresult +} + +FUNCTION {capitalize}{ "u" change.case$ "t" change.case$ } + +FUNCTION {emphasize} +{ duplicate$ empty$ + { pop$ "" } + { "\emph{" swap$ * "}" * } + if$ +} + +FUNCTION {do.name.latex.cmd} +{ name.latex.cmd + empty$ + { skip$ } + { name.latex.cmd "{" * swap$ * "}" * } + if$ +} + +% IEEEtran.bst uses its own \BIBforeignlanguage command which directly +% invokes the TeX hyphenation patterns without the need of the Babel +% package. Babel does a lot more than switch hyphenation patterns and +% its loading can cause unintended effects in many class files (such as +% IEEEtran.cls). +FUNCTION {select.language} +{ duplicate$ empty$ 'pop$ + { language empty$ 'skip$ + { "\BIBforeignlanguage{" language * "}{" * swap$ * "}" * } + if$ + } + if$ +} + +FUNCTION {tie.or.space.prefix} +{ duplicate$ text.length$ #3 < + { "~" } + { " " } + if$ + swap$ +} + +FUNCTION {get.bbl.editor} +{ editor num.names$ #1 > 'bbl.editors 'bbl.editor if$ } + +FUNCTION {space.word}{ " " swap$ * " " * } + + +% Field Conditioners, Converters, Checkers and External Interfaces + +FUNCTION {empty.field.to.null.string} +{ duplicate$ empty$ + { pop$ "" } + { skip$ } + if$ +} + +FUNCTION {either.or.check} +{ empty$ + { pop$ } + { "can't use both " swap$ * " fields in " * cite$ * warning$ } + if$ +} + +FUNCTION {empty.entry.warn} +{ author empty$ title empty$ howpublished empty$ + month empty$ year empty$ note empty$ url empty$ + and and and and and and + { "all relevant fields are empty in " cite$ * warning$ } + 'skip$ + if$ +} + + +% The bibinfo system provides a way for the electronic parsing/acquisition +% of a bibliography's contents as is done by ReVTeX. For example, a field +% could be entered into the bibliography as: +% \bibinfo{volume}{2} +% Only the "2" would show up in the document, but the LaTeX \bibinfo command +% could do additional things with the information. IEEEtran.bst does provide +% a \bibinfo command via "\providecommand{\bibinfo}[2]{#2}". However, it is +% currently not used as the bogus bibinfo functions defined here output the +% entry values directly without the \bibinfo wrapper. The bibinfo functions +% themselves (and the calls to them) are retained for possible future use. +% +% bibinfo.check avoids acting on missing fields while bibinfo.warn will +% issue a warning message if a missing field is detected. Prior to calling +% the bibinfo functions, the user should push the field value and then its +% name string, in that order. + +FUNCTION {bibinfo.check} +{ swap$ duplicate$ missing$ + { pop$ pop$ "" } + { duplicate$ empty$ + { swap$ pop$ } + { swap$ pop$ } + if$ + } + if$ +} + +FUNCTION {bibinfo.warn} +{ swap$ duplicate$ missing$ + { swap$ "missing " swap$ * " in " * cite$ * warning$ pop$ "" } + { duplicate$ empty$ + { swap$ "empty " swap$ * " in " * cite$ * warning$ } + { swap$ pop$ } + if$ + } + if$ +} + + +% IEEE separates large numbers with more than 4 digits into groups of +% three. IEEE uses a small space to separate these number groups. +% Typical applications include patent and page numbers. + +% number of consecutive digits required to trigger the group separation. +FUNCTION {large.number.trigger}{ #5 } + +% For numbers longer than the trigger, this is the blocksize of the groups. +% The blocksize must be less than the trigger threshold, and 2 * blocksize +% must be greater than the trigger threshold (can't do more than one +% separation on the initial trigger). +FUNCTION {large.number.blocksize}{ #3 } + +% What is actually inserted between the number groups. +FUNCTION {large.number.separator}{ "\," } + +% So as to save on integer variables by reusing existing ones, numnames +% holds the current number of consecutive digits read and nameptr holds +% the number that will trigger an inserted space. +FUNCTION {large.number.separate} +{ 't := + "" + #0 'numnames := + large.number.trigger 'nameptr := + { t empty$ not } + { t #-1 #1 substring$ is.num + { numnames #1 + 'numnames := } + { #0 'numnames := + large.number.trigger 'nameptr := + } + if$ + t #-1 #1 substring$ swap$ * + t #-2 global.max$ substring$ 't := + numnames nameptr = + { duplicate$ #1 nameptr large.number.blocksize - substring$ swap$ + nameptr large.number.blocksize - #1 + global.max$ substring$ + large.number.separator swap$ * * + nameptr large.number.blocksize - 'numnames := + large.number.blocksize #1 + 'nameptr := + } + { skip$ } + if$ + } + while$ +} + +% Converts all single dashes "-" to double dashes "--". +FUNCTION {n.dashify} +{ large.number.separate + 't := + "" + { t empty$ not } + { t #1 #1 substring$ "-" = + { t #1 #2 substring$ "--" = not + { "--" * + t #2 global.max$ substring$ 't := + } + { { t #1 #1 substring$ "-" = } + { "-" * + t #2 global.max$ substring$ 't := + } + while$ + } + if$ + } + { t #1 #1 substring$ * + t #2 global.max$ substring$ 't := + } + if$ + } + while$ +} + + +% This function detects entries with names that are identical to that of +% the previous entry and replaces the repeated names with dashes (if the +% "is.dash.repeated.names" user control is nonzero). +FUNCTION {name.or.dash} +{ 's := + oldname empty$ + { s 'oldname := s } + { s oldname = + { is.dash.repeated.names + { repeated.name.dashes } + { s 'oldname := s } + if$ + } + { s 'oldname := s } + if$ + } + if$ +} + +% Converts the number string on the top of the stack to +% "numerical ordinal form" (e.g., "7" to "7th"). There is +% no artificial limit to the upper bound of the numbers as the +% least significant digit always determines the ordinal form. +FUNCTION {num.to.ordinal} +{ duplicate$ #-1 #1 substring$ "1" = + { bbl.st * } + { duplicate$ #-1 #1 substring$ "2" = + { bbl.nd * } + { duplicate$ #-1 #1 substring$ "3" = + { bbl.rd * } + { bbl.th * } + if$ + } + if$ + } + if$ +} + +% If the string on the top of the stack begins with a number, +% (e.g., 11th) then replace the string with the leading number +% it contains. Otherwise retain the string as-is. s holds the +% extracted number, t holds the part of the string that remains +% to be scanned. +FUNCTION {extract.num} +{ duplicate$ 't := + "" 's := + { t empty$ not } + { t #1 #1 substring$ + t #2 global.max$ substring$ 't := + duplicate$ is.num + { s swap$ * 's := } + { pop$ "" 't := } + if$ + } + while$ + s empty$ + 'skip$ + { pop$ s } + if$ +} + +% Converts the word number string on the top of the stack to +% Arabic string form. Will be successful up to "tenth". +FUNCTION {word.to.num} +{ duplicate$ "l" change.case$ 's := + s "first" = + { pop$ "1" } + { skip$ } + if$ + s "second" = + { pop$ "2" } + { skip$ } + if$ + s "third" = + { pop$ "3" } + { skip$ } + if$ + s "fourth" = + { pop$ "4" } + { skip$ } + if$ + s "fifth" = + { pop$ "5" } + { skip$ } + if$ + s "sixth" = + { pop$ "6" } + { skip$ } + if$ + s "seventh" = + { pop$ "7" } + { skip$ } + if$ + s "eighth" = + { pop$ "8" } + { skip$ } + if$ + s "ninth" = + { pop$ "9" } + { skip$ } + if$ + s "tenth" = + { pop$ "10" } + { skip$ } + if$ +} + + +% Converts the string on the top of the stack to numerical +% ordinal (e.g., "11th") form. +FUNCTION {convert.edition} +{ duplicate$ empty$ 'skip$ + { duplicate$ #1 #1 substring$ is.num + { extract.num + num.to.ordinal + } + { word.to.num + duplicate$ #1 #1 substring$ is.num + { num.to.ordinal } + { "edition ordinal word " quote$ * edition * quote$ * + " may be too high (or improper) for conversion" * " in " * cite$ * warning$ + } + if$ + } + if$ + } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% LATEX BIBLIOGRAPHY CODE %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {start.entry} +{ newline$ + "\bibitem{" write$ + cite$ write$ + "}" write$ + newline$ + "" + initialize.prev.this.status +} + +% Here we write out all the LaTeX code that we will need. The most involved +% code sequences are those that control the alternate interword spacing and +% foreign language hyphenation patterns. The heavy use of \providecommand +% gives users a way to override the defaults. Special thanks to Javier Bezos, +% Johannes Braams, Robin Fairbairns, Heiko Oberdiek, Donald Arseneau and all +% the other gurus on comp.text.tex for their help and advice on the topic of +% \selectlanguage, Babel and BibTeX. +FUNCTION {begin.bib} +{ "% Generated by IEEEtran.bst, version: " bst.file.version * " (" * bst.file.date * ")" * + write$ newline$ + preamble$ empty$ 'skip$ + { preamble$ write$ newline$ } + if$ + "\begin{thebibliography}{" longest.label * "}" * + write$ newline$ + "\providecommand{\url}[1]{#1}" + write$ newline$ + "\csname url@samestyle\endcsname" + write$ newline$ + "\providecommand{\newblock}{\relax}" + write$ newline$ + "\providecommand{\bibinfo}[2]{#2}" + write$ newline$ + "\providecommand{\BIBentrySTDinterwordspacing}{\spaceskip=0pt\relax}" + write$ newline$ + "\providecommand{\BIBentryALTinterwordstretchfactor}{" + ALTinterwordstretchfactor * "}" * + write$ newline$ + "\providecommand{\BIBentryALTinterwordspacing}{\spaceskip=\fontdimen2\font plus " + write$ newline$ + "\BIBentryALTinterwordstretchfactor\fontdimen3\font minus \fontdimen4\font\relax}" + write$ newline$ + "\providecommand{\BIBforeignlanguage}[2]{{%" + write$ newline$ + "\expandafter\ifx\csname l@#1\endcsname\relax" + write$ newline$ + "\typeout{** WARNING: IEEEtran.bst: No hyphenation pattern has been}%" + write$ newline$ + "\typeout{** loaded for the language `#1'. Using the pattern for}%" + write$ newline$ + "\typeout{** the default language instead.}%" + write$ newline$ + "\else" + write$ newline$ + "\language=\csname l@#1\endcsname" + write$ newline$ + "\fi" + write$ newline$ + "#2}}" + write$ newline$ + "\providecommand{\BIBdecl}{\relax}" + write$ newline$ + "\BIBdecl" + write$ newline$ +} + +FUNCTION {end.bib} +{ newline$ "\end{thebibliography}" write$ newline$ } + +FUNCTION {if.url.alt.interword.spacing} +{ is.use.alt.interword.spacing + {url empty$ 'skip$ {"\BIBentryALTinterwordspacing" write$ newline$} if$} + { skip$ } + if$ +} + +FUNCTION {if.url.std.interword.spacing} +{ is.use.alt.interword.spacing + {url empty$ 'skip$ {"\BIBentrySTDinterwordspacing" write$ newline$} if$} + { skip$ } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%%%%% +%% LONGEST LABEL PASS %% +%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {initialize.longest.label} +{ "" 'longest.label := + #1 'number.label := + #0 'longest.label.width := +} + +FUNCTION {longest.label.pass} +{ type$ "ieeetranbstctl" = + { skip$ } + { number.label int.to.str$ 'label := + number.label #1 + 'number.label := + label width$ longest.label.width > + { label 'longest.label := + label width$ 'longest.label.width := + } + { skip$ } + if$ + } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%% +%% FORMAT HANDLERS %% +%%%%%%%%%%%%%%%%%%%%% + +%% Lower Level Formats (used by higher level formats) + +FUNCTION {format.address.org.or.pub.date} +{ 't := + "" + year empty$ + { "empty year in " cite$ * warning$ } + { skip$ } + if$ + address empty$ t empty$ and + year empty$ and month empty$ and + { skip$ } + { this.to.prev.status + this.status.std + cap.status.std + address "address" bibinfo.check * + t empty$ + { skip$ } + { punct.period 'prev.status.punct := + space.large 'prev.status.space := + address empty$ + { skip$ } + { ": " * } + if$ + t * + } + if$ + year empty$ month empty$ and + { skip$ } + { t empty$ address empty$ and + { skip$ } + { ", " * } + if$ + month empty$ + { year empty$ + { skip$ } + { year "year" bibinfo.check * } + if$ + } + { month "month" bibinfo.check * + year empty$ + { skip$ } + { " " * year "year" bibinfo.check * } + if$ + } + if$ + } + if$ + } + if$ +} + + +FUNCTION {format.names} +{ 'bibinfo := + duplicate$ empty$ 'skip$ { + this.to.prev.status + this.status.std + 's := + "" 't := + #1 'nameptr := + s num.names$ 'numnames := + numnames 'namesleft := + { namesleft #0 > } + { s nameptr + name.format.string + format.name$ + bibinfo bibinfo.check + 't := + nameptr #1 > + { nameptr num.names.shown.with.forced.et.al #1 + = + numnames max.num.names.before.forced.et.al > + is.forced.et.al and and + { "others" 't := + #1 'namesleft := + } + { skip$ } + if$ + namesleft #1 > + { ", " * t do.name.latex.cmd * } + { s nameptr "{ll}" format.name$ duplicate$ "others" = + { 't := } + { pop$ } + if$ + t "others" = + { " " * bbl.etal emphasize * } + { numnames #2 > + { "," * } + { skip$ } + if$ + bbl.and + space.word * t do.name.latex.cmd * + } + if$ + } + if$ + } + { t do.name.latex.cmd } + if$ + nameptr #1 + 'nameptr := + namesleft #1 - 'namesleft := + } + while$ + cap.status.std + } if$ +} + + + + +%% Higher Level Formats + +%% addresses/locations + +FUNCTION {format.address} +{ address duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + + + +%% author/editor names + +FUNCTION {format.authors}{ author "author" format.names } + +FUNCTION {format.editors} +{ editor "editor" format.names duplicate$ empty$ 'skip$ + { ", " * + get.bbl.editor + capitalize + * + } + if$ +} + + + +%% date + +FUNCTION {format.date} +{ + month "month" bibinfo.check duplicate$ empty$ + year "year" bibinfo.check duplicate$ empty$ + { swap$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + "there's a month but no year in " cite$ * warning$ } + if$ + * + } + { this.to.prev.status + this.status.std + cap.status.std + swap$ 'skip$ + { + swap$ + " " * swap$ + } + if$ + * + } + if$ +} + +FUNCTION {format.date.electronic} +{ month "month" bibinfo.check duplicate$ empty$ + year "year" bibinfo.check duplicate$ empty$ + { swap$ + { pop$ } + { "there's a month but no year in " cite$ * warning$ + pop$ ")" * "(" swap$ * + this.to.prev.status + punct.no 'this.status.punct := + space.normal 'this.status.space := + quote.no 'this.status.quote := + cap.yes 'status.cap := + } + if$ + } + { swap$ + { swap$ pop$ ")" * "(" swap$ * } + { "(" swap$ * ", " * swap$ * ")" * } + if$ + this.to.prev.status + punct.no 'this.status.punct := + space.normal 'this.status.space := + quote.no 'this.status.quote := + cap.yes 'status.cap := + } + if$ +} + + + +%% edition/title + +% Note: IEEE considers the edition to be closely associated with +% the title of a book. So, in IEEEtran.bst the edition is normally handled +% within the formatting of the title. The format.edition function is +% retained here for possible future use. +FUNCTION {format.edition} +{ edition duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + convert.edition + status.cap + { "t" } + { "l" } + if$ change.case$ + "edition" bibinfo.check + "~" * bbl.edition * + cap.status.std + } + if$ +} + +% This is used to format the booktitle of a conference proceedings. +% Here we use the "intype" field to provide the user a way to +% override the word "in" (e.g., with things like "presented at") +% Use of intype stops the emphasis of the booktitle to indicate that +% we no longer mean the written conference proceedings, but the +% conference itself. +FUNCTION {format.in.booktitle} +{ booktitle "booktitle" bibinfo.check duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + select.language + intype missing$ + { emphasize + bbl.in " " * + } + { intype " " * } + if$ + swap$ * + cap.status.std + } + if$ +} + +% This is used to format the booktitle of collection. +% Here the "intype" field is not supported, but "edition" is. +FUNCTION {format.in.booktitle.edition} +{ booktitle "booktitle" bibinfo.check duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + select.language + emphasize + edition empty$ 'skip$ + { ", " * + edition + convert.edition + "l" change.case$ + * "~" * bbl.edition * + } + if$ + bbl.in " " * swap$ * + cap.status.std + } + if$ +} + +FUNCTION {format.article.title} +{ title duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + "t" change.case$ + } + if$ + "title" bibinfo.check + duplicate$ empty$ 'skip$ + { quote.close 'this.status.quote := + is.last.char.not.punct + { punct.std 'this.status.punct := } + { punct.no 'this.status.punct := } + if$ + select.language + "``" swap$ * + cap.status.std + } + if$ +} + +FUNCTION {format.article.title.electronic} +{ title duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + "t" change.case$ + } + if$ + "title" bibinfo.check + duplicate$ empty$ + { skip$ } + { select.language } + if$ +} + +FUNCTION {format.book.title.edition} +{ title "title" bibinfo.check + duplicate$ empty$ + { "empty title in " cite$ * warning$ } + { this.to.prev.status + this.status.std + select.language + emphasize + edition empty$ 'skip$ + { ", " * + edition + convert.edition + status.cap + { "t" } + { "l" } + if$ + change.case$ + * "~" * bbl.edition * + } + if$ + cap.status.std + } + if$ +} + +FUNCTION {format.book.title} +{ title "title" bibinfo.check + duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + select.language + emphasize + } + if$ +} + + + +%% journal + +FUNCTION {format.journal} +{ journal duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + select.language + emphasize + } + if$ +} + + + +%% how published + +FUNCTION {format.howpublished} +{ howpublished duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + + + +%% institutions/organization/publishers/school + +FUNCTION {format.institution} +{ institution duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + +FUNCTION {format.organization} +{ organization duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + +FUNCTION {format.address.publisher.date} +{ publisher "publisher" bibinfo.warn format.address.org.or.pub.date } + +FUNCTION {format.address.publisher.date.nowarn} +{ publisher "publisher" bibinfo.check format.address.org.or.pub.date } + +FUNCTION {format.address.organization.date} +{ organization "organization" bibinfo.check format.address.org.or.pub.date } + +FUNCTION {format.school} +{ school duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + + + +%% volume/number/series/chapter/pages + +FUNCTION {format.volume} +{ volume empty.field.to.null.string + duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + bbl.volume + status.cap + { capitalize } + { skip$ } + if$ + swap$ tie.or.space.prefix + "volume" bibinfo.check + * * + cap.status.std + } + if$ +} + +FUNCTION {format.number} +{ number empty.field.to.null.string + duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + status.cap + { bbl.number capitalize } + { bbl.number } + if$ + swap$ tie.or.space.prefix + "number" bibinfo.check + * * + cap.status.std + } + if$ +} + +FUNCTION {format.number.if.use.for.article} +{ is.use.number.for.article + { format.number } + { "" } + if$ +} + +% IEEE does not seem to tie the series so closely with the volume +% and number as is done in other bibliography styles. Instead the +% series is treated somewhat like an extension of the title. +FUNCTION {format.series} +{ series empty$ + { "" } + { this.to.prev.status + this.status.std + bbl.series " " * + series "series" bibinfo.check * + cap.status.std + } + if$ +} + + +FUNCTION {format.chapter} +{ chapter empty$ + { "" } + { this.to.prev.status + this.status.std + type empty$ + { bbl.chapter } + { type "l" change.case$ + "type" bibinfo.check + } + if$ + chapter tie.or.space.prefix + "chapter" bibinfo.check + * * + cap.status.std + } + if$ +} + + +% The intended use of format.paper is for paper numbers of inproceedings. +% The paper type can be overridden via the type field. +% We allow the type to be displayed even if the paper number is absent +% for things like "postdeadline paper" +FUNCTION {format.paper} +{ is.use.paper + { paper empty$ + { type empty$ + { "" } + { this.to.prev.status + this.status.std + type "type" bibinfo.check + cap.status.std + } + if$ + } + { this.to.prev.status + this.status.std + type empty$ + { bbl.paper } + { type "type" bibinfo.check } + if$ + " " * paper + "paper" bibinfo.check + * + cap.status.std + } + if$ + } + { "" } + if$ +} + + +FUNCTION {format.pages} +{ pages duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + duplicate$ is.multiple.pages + { + bbl.pages swap$ + n.dashify + } + { + bbl.page swap$ + } + if$ + tie.or.space.prefix + "pages" bibinfo.check + * * + cap.status.std + } + if$ +} + + + +%% technical report number + +FUNCTION {format.tech.report.number} +{ number "number" bibinfo.check + this.to.prev.status + this.status.std + cap.status.std + type duplicate$ empty$ + { pop$ + bbl.techrep + } + { skip$ } + if$ + "type" bibinfo.check + swap$ duplicate$ empty$ + { pop$ } + { tie.or.space.prefix * * } + if$ +} + + + +%% note + +FUNCTION {format.note} +{ note empty$ + { "" } + { this.to.prev.status + this.status.std + punct.period 'this.status.punct := + note #1 #1 substring$ + duplicate$ "{" = + { skip$ } + { status.cap + { "u" } + { "l" } + if$ + change.case$ + } + if$ + note #2 global.max$ substring$ * "note" bibinfo.check + cap.yes 'status.cap := + } + if$ +} + + + +%% patent + +FUNCTION {format.patent.date} +{ this.to.prev.status + this.status.std + year empty$ + { monthfiled duplicate$ empty$ + { "monthfiled" bibinfo.check pop$ "" } + { "monthfiled" bibinfo.check } + if$ + dayfiled duplicate$ empty$ + { "dayfiled" bibinfo.check pop$ "" * } + { "dayfiled" bibinfo.check + monthfiled empty$ + { "dayfiled without a monthfiled in " cite$ * warning$ + * + } + { " " swap$ * * } + if$ + } + if$ + yearfiled empty$ + { "no year or yearfiled in " cite$ * warning$ } + { yearfiled "yearfiled" bibinfo.check + swap$ + duplicate$ empty$ + { pop$ } + { ", " * swap$ * } + if$ + } + if$ + } + { month duplicate$ empty$ + { "month" bibinfo.check pop$ "" } + { "month" bibinfo.check } + if$ + day duplicate$ empty$ + { "day" bibinfo.check pop$ "" * } + { "day" bibinfo.check + month empty$ + { "day without a month in " cite$ * warning$ + * + } + { " " swap$ * * } + if$ + } + if$ + year "year" bibinfo.check + swap$ + duplicate$ empty$ + { pop$ } + { ", " * swap$ * } + if$ + } + if$ + cap.status.std +} + +FUNCTION {format.patent.nationality.type.number} +{ this.to.prev.status + this.status.std + nationality duplicate$ empty$ + { "nationality" bibinfo.warn pop$ "" } + { "nationality" bibinfo.check + duplicate$ "l" change.case$ "united states" = + { pop$ bbl.patentUS } + { skip$ } + if$ + " " * + } + if$ + type empty$ + { bbl.patent "type" bibinfo.check } + { type "type" bibinfo.check } + if$ + * + number duplicate$ empty$ + { "number" bibinfo.warn pop$ } + { "number" bibinfo.check + large.number.separate + swap$ " " * swap$ * + } + if$ + cap.status.std +} + + + +%% standard + +FUNCTION {format.organization.institution.standard.type.number} +{ this.to.prev.status + this.status.std + organization duplicate$ empty$ + { pop$ + institution duplicate$ empty$ + { "institution" bibinfo.warn } + { "institution" bibinfo.warn " " * } + if$ + } + { "organization" bibinfo.warn " " * } + if$ + type empty$ + { bbl.standard "type" bibinfo.check } + { type "type" bibinfo.check } + if$ + * + number duplicate$ empty$ + { "number" bibinfo.check pop$ } + { "number" bibinfo.check + large.number.separate + swap$ " " * swap$ * + } + if$ + cap.status.std +} + +FUNCTION {format.revision} +{ revision empty$ + { "" } + { this.to.prev.status + this.status.std + bbl.revision + revision tie.or.space.prefix + "revision" bibinfo.check + * * + cap.status.std + } + if$ +} + + +%% thesis + +FUNCTION {format.master.thesis.type} +{ this.to.prev.status + this.status.std + type empty$ + { + bbl.mthesis + } + { + type "type" bibinfo.check + } + if$ +cap.status.std +} + +FUNCTION {format.phd.thesis.type} +{ this.to.prev.status + this.status.std + type empty$ + { + bbl.phdthesis + } + { + type "type" bibinfo.check + } + if$ +cap.status.std +} + + + +%% URL + +FUNCTION {format.url} +{ url empty$ + { "" } + { this.to.prev.status + this.status.std + cap.yes 'status.cap := + name.url.prefix " " * + "\url{" * url * "}" * + punct.no 'this.status.punct := + punct.period 'prev.status.punct := + space.normal 'this.status.space := + space.normal 'prev.status.space := + quote.no 'this.status.quote := + } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%% +%% ENTRY HANDLERS %% +%%%%%%%%%%%%%%%%%%%% + + +% Note: In many journals, IEEE (or the authors) tend not to show the number +% for articles, so the display of the number is controlled here by the +% switch "is.use.number.for.article" +FUNCTION {article} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.journal "journal" bibinfo.check "journal" output.warn + format.volume output + format.number.if.use.for.article output + format.pages output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {book} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + author empty$ + { format.editors "author and editor" output.warn } + { format.authors output.nonnull } + if$ + name.or.dash + format.book.title.edition output + format.series output + author empty$ + { skip$ } + { format.editors output } + if$ + format.address.publisher.date output + format.volume output + format.number output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {booklet} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.article.title "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.date output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {electronic} +{ std.status.using.period + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.date.electronic output + format.article.title.electronic output + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.note output + format.url output + fin.entry + empty.entry.warn + if.url.std.interword.spacing +} + +FUNCTION {inbook} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + author empty$ + { format.editors "author and editor" output.warn } + { format.authors output.nonnull } + if$ + name.or.dash + format.book.title.edition output + format.series output + format.address.publisher.date output + format.volume output + format.number output + format.chapter output + format.pages output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {incollection} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.in.booktitle.edition "booktitle" output.warn + format.series output + format.editors output + format.address.publisher.date.nowarn output + format.volume output + format.number output + format.chapter output + format.pages output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {inproceedings} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.in.booktitle "booktitle" output.warn + format.series output + format.editors output + format.volume output + format.number output + publisher empty$ + { format.address.organization.date output } + { format.organization "organization" bibinfo.check output + format.address.publisher.date output + } + if$ + format.paper output + format.pages output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {manual} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.book.title.edition "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.date output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {mastersthesis} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.master.thesis.type output.nonnull + format.school "school" bibinfo.warn output + format.address "address" bibinfo.check output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {misc} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.article.title output + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.pages output + format.date output + format.note output + format.url output + fin.entry + empty.entry.warn + if.url.std.interword.spacing +} + +FUNCTION {patent} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.article.title output + format.patent.nationality.type.number output + format.patent.date output + format.note output + format.url output + fin.entry + empty.entry.warn + if.url.std.interword.spacing +} + +FUNCTION {periodical} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.editors output + name.or.dash + format.book.title "title" output.warn + format.series output + format.volume output + format.number output + format.organization "organization" bibinfo.check output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {phdthesis} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.phd.thesis.type output.nonnull + format.school "school" bibinfo.warn output + format.address "address" bibinfo.check output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {proceedings} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.editors output + name.or.dash + format.book.title "title" output.warn + format.series output + format.volume output + format.number output + publisher empty$ + { format.address.organization.date output } + { format.organization "organization" bibinfo.check output + format.address.publisher.date output + } + if$ + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {standard} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.book.title "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.organization.institution.standard.type.number output + format.revision output + format.date output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {techreport} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.institution "institution" bibinfo.warn output + format.address "address" bibinfo.check output + format.tech.report.number output.nonnull + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {unpublished} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.date output + format.note "note" output.warn + format.url output + fin.entry + if.url.std.interword.spacing +} + + +% The special entry type which provides the user interface to the +% BST controls +FUNCTION {IEEEtranBSTCTL} +{ is.print.banners.to.terminal + { "** IEEEtran BST control entry " quote$ * cite$ * quote$ * " detected." * + top$ + } + { skip$ } + if$ + CTLuse_article_number + empty$ + { skip$ } + { CTLuse_article_number + yes.no.to.int + 'is.use.number.for.article := + } + if$ + CTLuse_paper + empty$ + { skip$ } + { CTLuse_paper + yes.no.to.int + 'is.use.paper := + } + if$ + CTLuse_forced_etal + empty$ + { skip$ } + { CTLuse_forced_etal + yes.no.to.int + 'is.forced.et.al := + } + if$ + CTLmax_names_forced_etal + empty$ + { skip$ } + { CTLmax_names_forced_etal + string.to.integer + 'max.num.names.before.forced.et.al := + } + if$ + CTLnames_show_etal + empty$ + { skip$ } + { CTLnames_show_etal + string.to.integer + 'num.names.shown.with.forced.et.al := + } + if$ + CTLuse_alt_spacing + empty$ + { skip$ } + { CTLuse_alt_spacing + yes.no.to.int + 'is.use.alt.interword.spacing := + } + if$ + CTLalt_stretch_factor + empty$ + { skip$ } + { CTLalt_stretch_factor + 'ALTinterwordstretchfactor := + "\renewcommand{\BIBentryALTinterwordstretchfactor}{" + ALTinterwordstretchfactor * "}" * + write$ newline$ + } + if$ + CTLdash_repeated_names + empty$ + { skip$ } + { CTLdash_repeated_names + yes.no.to.int + 'is.dash.repeated.names := + } + if$ + CTLname_format_string + empty$ + { skip$ } + { CTLname_format_string + 'name.format.string := + } + if$ + CTLname_latex_cmd + empty$ + { skip$ } + { CTLname_latex_cmd + 'name.latex.cmd := + } + if$ + CTLname_url_prefix + missing$ + { skip$ } + { CTLname_url_prefix + 'name.url.prefix := + } + if$ + + + num.names.shown.with.forced.et.al max.num.names.before.forced.et.al > + { "CTLnames_show_etal cannot be greater than CTLmax_names_forced_etal in " cite$ * warning$ + max.num.names.before.forced.et.al 'num.names.shown.with.forced.et.al := + } + { skip$ } + if$ +} + + +%%%%%%%%%%%%%%%%%%% +%% ENTRY ALIASES %% +%%%%%%%%%%%%%%%%%%% +FUNCTION {conference}{inproceedings} +FUNCTION {online}{electronic} +FUNCTION {internet}{electronic} +FUNCTION {webpage}{electronic} +FUNCTION {www}{electronic} +FUNCTION {default.type}{misc} + + + +%%%%%%%%%%%%%%%%%% +%% MAIN PROGRAM %% +%%%%%%%%%%%%%%%%%% + +READ + +EXECUTE {initialize.controls} +EXECUTE {initialize.status.constants} +EXECUTE {banner.message} + +EXECUTE {initialize.longest.label} +ITERATE {longest.label.pass} + +EXECUTE {begin.bib} +ITERATE {call.type$} +EXECUTE {end.bib} + +EXECUTE{completed.message} + + +%% That's all folks, mds. diff --git a/standard/Report/IEEEtranBST2/IEEEtranS.bst b/standard/Report/IEEEtranBST2/IEEEtranS.bst new file mode 100644 index 0000000000000000000000000000000000000000..13ecf8b19b437e206b27f81bebff8d84be3726d3 --- /dev/null +++ b/standard/Report/IEEEtranBST2/IEEEtranS.bst @@ -0,0 +1,2607 @@ +%% +%% IEEEtranS.bst +%% BibTeX Bibliography Style file +%% Sorting version of IEEEtran.bst +%% *** Not for normal IEEE work *** +%% Version 1.12 (2007/01/11) +%% +%% Copyright (c) 2003-2007 Michael Shell +%% +%% Original starting code base and algorithms obtained from the output of +%% Patrick W. Daly's makebst package as well as from prior versions of +%% IEEE BibTeX styles: +%% +%% 1. Howard Trickey and Oren Patashnik's ieeetr.bst (1985/1988) +%% 2. Silvano Balemi and Richard H. Roy's IEEEbib.bst (1993) +%% +%% Added sorting code is from plain.bst. +%% +%% Support sites: +%% http://www.michaelshell.org/tex/ieeetran/ +%% http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/ +%% and/or +%% http://www.ieee.org/ +%% +%% For use with BibTeX version 0.99a or later +%% +%% This is a numerical citation style. +%% +%%************************************************************************* +%% Legal Notice: +%% This code is offered as-is without any warranty either expressed or +%% implied; without even the implied warranty of MERCHANTABILITY or +%% FITNESS FOR A PARTICULAR PURPOSE! +%% User assumes all risk. +%% In no event shall IEEE or any contributor to this code be liable for +%% any damages or losses, including, but not limited to, incidental, +%% consequential, or any other damages, resulting from the use or misuse +%% of any information contained here. +%% +%% All comments are the opinions of their respective authors and are not +%% necessarily endorsed by the IEEE. +%% +%% This work is distributed under the LaTeX Project Public License (LPPL) +%% ( http://www.latex-project.org/ ) version 1.3, and may be freely used, +%% distributed and modified. A copy of the LPPL, version 1.3, is included +%% in the base LaTeX documentation of all distributions of LaTeX released +%% 2003/12/01 or later. +%% Retain all contribution notices and credits. +%% ** Modified files should be clearly indicated as such, including ** +%% ** renaming them and changing author support contact information. ** +%% +%% File list of work: IEEEabrv.bib, IEEEfull.bib, IEEEexample.bib, +%% IEEEtran.bst, IEEEtranS.bst, IEEEtranSA.bst, +%% IEEEtranN.bst, IEEEtranSN.bst, IEEEtran_bst_HOWTO.pdf +%%************************************************************************* +% +% +% Changelog: +% +% 1.10 (2002/09/27) Initial release +% +% 1.11 (2003/04/02) +% 1. Fixed bug with URLs containing underscores when using url.sty. Thanks +% to Ming Kin Lai for reporting this. +% +% 1.12 (2007/01/11) +% 1. Fixed bug with unwanted comma before "et al." when an entry contained +% more than two author names. Thanks to Pallav Gupta for reporting this. +% 2. Fixed bug with anomalous closing quote in tech reports that have a +% type, but without a number or address. Thanks to Mehrdad Mirreza for +% reporting this. +% 3. Use braces in \providecommand in begin.bib to better support +% latex2html. TeX style length assignments OK with recent versions +% of latex2html - 1.71 (2002/2/1) or later is strongly recommended. +% Use of the language field still causes trouble with latex2html. +% Thanks to Federico Beffa for reporting this. +% 4. Added IEEEtran.bst ID and version comment string to .bbl output. +% 5. Provide a \BIBdecl hook that allows the user to execute commands +% just prior to the first entry. +% 6. Use default urlstyle (is using url.sty) of "same" rather than rm to +% better work with a wider variety of bibliography styles. +% 7. Changed month abbreviations from Sept., July and June to Sep., Jul., +% and Jun., respectively, as IEEE now does. Thanks to Moritz Borgmann +% for reporting this. +% 8. Control entry types should not be considered when calculating longest +% label width. +% 9. Added alias www for electronic/online. +% 10. Added CTLname_url_prefix control entry type. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% DEFAULTS FOR THE CONTROLS OF THE BST STYLE %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% These are the defaults for the user adjustable controls. The values used +% here can be overridden by the user via IEEEtranBSTCTL entry type. + +% NOTE: The recommended LaTeX command to invoke a control entry type is: +% +%\makeatletter +%\def\bstctlcite{\@ifnextchar[{\@bstctlcite}{\@bstctlcite[@auxout]}} +%\def\@bstctlcite[#1]#2{\@bsphack +% \@for\@citeb:=#2\do{% +% \edef\@citeb{\expandafter\@firstofone\@citeb}% +% \if@filesw\immediate\write\csname #1\endcsname{\string\citation{\@citeb}}\fi}% +% \@esphack} +%\makeatother +% +% It is called at the start of the document, before the first \cite, like: +% \bstctlcite{IEEEexample:BSTcontrol} +% +% IEEEtran.cls V1.6 and later does provide this command. + + + +% #0 turns off the display of the number for articles. +% #1 enables +FUNCTION {default.is.use.number.for.article} { #1 } + + +% #0 turns off the display of the paper and type fields in @inproceedings. +% #1 enables +FUNCTION {default.is.use.paper} { #1 } + + +% #0 turns off the forced use of "et al." +% #1 enables +FUNCTION {default.is.forced.et.al} { #0 } + +% The maximum number of names that can be present beyond which an "et al." +% usage is forced. Be sure that num.names.shown.with.forced.et.al (below) +% is not greater than this value! +% Note: There are many instances of references in IEEE journals which have +% a very large number of authors as well as instances in which "et al." is +% used profusely. +FUNCTION {default.max.num.names.before.forced.et.al} { #10 } + +% The number of names that will be shown with a forced "et al.". +% Must be less than or equal to max.num.names.before.forced.et.al +FUNCTION {default.num.names.shown.with.forced.et.al} { #1 } + + +% #0 turns off the alternate interword spacing for entries with URLs. +% #1 enables +FUNCTION {default.is.use.alt.interword.spacing} { #1 } + +% If alternate interword spacing for entries with URLs is enabled, this is +% the interword spacing stretch factor that will be used. For example, the +% default "4" here means that the interword spacing in entries with URLs can +% stretch to four times normal. Does not have to be an integer. Note that +% the value specified here can be overridden by the user in their LaTeX +% code via a command such as: +% "\providecommand\BIBentryALTinterwordstretchfactor{1.5}" in addition to +% that via the IEEEtranBSTCTL entry type. +FUNCTION {default.ALTinterwordstretchfactor} { "4" } + + +% #0 turns off the "dashification" of repeated (i.e., identical to those +% of the previous entry) names. IEEE normally does this. +% #1 enables +FUNCTION {default.is.dash.repeated.names} { #1 } + + +% The default name format control string. +FUNCTION {default.name.format.string}{ "{f.~}{vv~}{ll}{, jj}" } + + +% The default LaTeX font command for the names. +FUNCTION {default.name.latex.cmd}{ "" } + + +% The default URL prefix. +FUNCTION {default.name.url.prefix}{ "[Online]. Available:" } + + +% Other controls that cannot be accessed via IEEEtranBSTCTL entry type. + +% #0 turns off the terminal startup banner/completed message so as to +% operate more quietly. +% #1 enables +FUNCTION {is.print.banners.to.terminal} { #1 } + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% FILE VERSION AND BANNER %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION{bst.file.version} { "1.12" } +FUNCTION{bst.file.date} { "2007/01/11" } +FUNCTION{bst.file.website} { "http://www.michaelshell.org/tex/ieeetran/bibtex/" } + +FUNCTION {banner.message} +{ is.print.banners.to.terminal + { "-- IEEEtranS.bst version" " " * bst.file.version * + " (" * bst.file.date * ") " * "by Michael Shell." * + top$ + "-- " bst.file.website * + top$ + "-- See the " quote$ * "IEEEtran_bst_HOWTO.pdf" * quote$ * " manual for usage information." * + top$ + "** Sorting version - not for normal IEEE work." + top$ + } + { skip$ } + if$ +} + +FUNCTION {completed.message} +{ is.print.banners.to.terminal + { "" + top$ + "Done." + top$ + } + { skip$ } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%%% +%% STRING CONSTANTS %% +%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {bbl.and}{ "and" } +FUNCTION {bbl.etal}{ "et~al." } +FUNCTION {bbl.editors}{ "eds." } +FUNCTION {bbl.editor}{ "ed." } +FUNCTION {bbl.edition}{ "ed." } +FUNCTION {bbl.volume}{ "vol." } +FUNCTION {bbl.of}{ "of" } +FUNCTION {bbl.number}{ "no." } +FUNCTION {bbl.in}{ "in" } +FUNCTION {bbl.pages}{ "pp." } +FUNCTION {bbl.page}{ "p." } +FUNCTION {bbl.chapter}{ "ch." } +FUNCTION {bbl.paper}{ "paper" } +FUNCTION {bbl.part}{ "pt." } +FUNCTION {bbl.patent}{ "Patent" } +FUNCTION {bbl.patentUS}{ "U.S." } +FUNCTION {bbl.revision}{ "Rev." } +FUNCTION {bbl.series}{ "ser." } +FUNCTION {bbl.standard}{ "Std." } +FUNCTION {bbl.techrep}{ "Tech. Rep." } +FUNCTION {bbl.mthesis}{ "Master's thesis" } +FUNCTION {bbl.phdthesis}{ "Ph.D. dissertation" } +FUNCTION {bbl.st}{ "st" } +FUNCTION {bbl.nd}{ "nd" } +FUNCTION {bbl.rd}{ "rd" } +FUNCTION {bbl.th}{ "th" } + + +% This is the LaTeX spacer that is used when a larger than normal space +% is called for (such as just before the address:publisher). +FUNCTION {large.space} { "\hskip 1em plus 0.5em minus 0.4em\relax " } + +% The LaTeX code for dashes that are used to represent repeated names. +% Note: Some older IEEE journals used something like +% "\rule{0.275in}{0.5pt}\," which is fairly thick and runs right along +% the baseline. However, IEEE now uses a thinner, above baseline, +% six dash long sequence. +FUNCTION {repeated.name.dashes} { "------" } + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% PREDEFINED STRING MACROS %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +MACRO {jan} {"Jan."} +MACRO {feb} {"Feb."} +MACRO {mar} {"Mar."} +MACRO {apr} {"Apr."} +MACRO {may} {"May"} +MACRO {jun} {"Jun."} +MACRO {jul} {"Jul."} +MACRO {aug} {"Aug."} +MACRO {sep} {"Sep."} +MACRO {oct} {"Oct."} +MACRO {nov} {"Nov."} +MACRO {dec} {"Dec."} + + + +%%%%%%%%%%%%%%%%%% +%% ENTRY FIELDS %% +%%%%%%%%%%%%%%%%%% + +ENTRY + { address + assignee + author + booktitle + chapter + day + dayfiled + edition + editor + howpublished + institution + intype + journal + key + language + month + monthfiled + nationality + note + number + organization + pages + paper + publisher + school + series + revision + title + type + url + volume + year + yearfiled + CTLuse_article_number + CTLuse_paper + CTLuse_forced_etal + CTLmax_names_forced_etal + CTLnames_show_etal + CTLuse_alt_spacing + CTLalt_stretch_factor + CTLdash_repeated_names + CTLname_format_string + CTLname_latex_cmd + CTLname_url_prefix + } + {} + { label } + + + + +%%%%%%%%%%%%%%%%%%%%%%% +%% INTEGER VARIABLES %% +%%%%%%%%%%%%%%%%%%%%%%% + +INTEGERS { prev.status.punct this.status.punct punct.std + punct.no punct.comma punct.period + prev.status.space this.status.space space.std + space.no space.normal space.large + prev.status.quote this.status.quote quote.std + quote.no quote.close + prev.status.nline this.status.nline nline.std + nline.no nline.newblock + status.cap cap.std + cap.no cap.yes} + +INTEGERS { longest.label.width multiresult nameptr namesleft number.label numnames } + +INTEGERS { is.use.number.for.article + is.use.paper + is.forced.et.al + max.num.names.before.forced.et.al + num.names.shown.with.forced.et.al + is.use.alt.interword.spacing + is.dash.repeated.names} + + +%%%%%%%%%%%%%%%%%%%%%% +%% STRING VARIABLES %% +%%%%%%%%%%%%%%%%%%%%%% + +STRINGS { bibinfo + longest.label + oldname + s + t + ALTinterwordstretchfactor + name.format.string + name.latex.cmd + name.url.prefix} + + + + +%%%%%%%%%%%%%%%%%%%%%%%%% +%% LOW LEVEL FUNCTIONS %% +%%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {initialize.controls} +{ default.is.use.number.for.article 'is.use.number.for.article := + default.is.use.paper 'is.use.paper := + default.is.forced.et.al 'is.forced.et.al := + default.max.num.names.before.forced.et.al 'max.num.names.before.forced.et.al := + default.num.names.shown.with.forced.et.al 'num.names.shown.with.forced.et.al := + default.is.use.alt.interword.spacing 'is.use.alt.interword.spacing := + default.is.dash.repeated.names 'is.dash.repeated.names := + default.ALTinterwordstretchfactor 'ALTinterwordstretchfactor := + default.name.format.string 'name.format.string := + default.name.latex.cmd 'name.latex.cmd := + default.name.url.prefix 'name.url.prefix := +} + + +% This IEEEtran.bst features a very powerful and flexible mechanism for +% controlling the capitalization, punctuation, spacing, quotation, and +% newlines of the formatted entry fields. (Note: IEEEtran.bst does not need +% or use the newline/newblock feature, but it has been implemented for +% possible future use.) The output states of IEEEtran.bst consist of +% multiple independent attributes and, as such, can be thought of as being +% vectors, rather than the simple scalar values ("before.all", +% "mid.sentence", etc.) used in most other .bst files. +% +% The more flexible and complex design used here was motivated in part by +% IEEE's rather unusual bibliography style. For example, IEEE ends the +% previous field item with a period and large space prior to the publisher +% address; the @electronic entry types use periods as inter-item punctuation +% rather than the commas used by the other entry types; and URLs are never +% followed by periods even though they are the last item in the entry. +% Although it is possible to accommodate these features with the conventional +% output state system, the seemingly endless exceptions make for convoluted, +% unreliable and difficult to maintain code. +% +% IEEEtran.bst's output state system can be easily understood via a simple +% illustration of two most recently formatted entry fields (on the stack): +% +% CURRENT_ITEM +% "PREVIOUS_ITEM +% +% which, in this example, is to eventually appear in the bibliography as: +% +% "PREVIOUS_ITEM," CURRENT_ITEM +% +% It is the job of the output routine to take the previous item off of the +% stack (while leaving the current item at the top of the stack), apply its +% trailing punctuation (including closing quote marks) and spacing, and then +% to write the result to BibTeX's output buffer: +% +% "PREVIOUS_ITEM," +% +% Punctuation (and spacing) between items is often determined by both of the +% items rather than just the first one. The presence of quotation marks +% further complicates the situation because, in standard English, trailing +% punctuation marks are supposed to be contained within the quotes. +% +% IEEEtran.bst maintains two output state (aka "status") vectors which +% correspond to the previous and current (aka "this") items. Each vector +% consists of several independent attributes which track punctuation, +% spacing, quotation, and newlines. Capitalization status is handled by a +% separate scalar because the format routines, not the output routine, +% handle capitalization and, therefore, there is no need to maintain the +% capitalization attribute for both the "previous" and "this" items. +% +% When a format routine adds a new item, it copies the current output status +% vector to the previous output status vector and (usually) resets the +% current (this) output status vector to a "standard status" vector. Using a +% "standard status" vector in this way allows us to redefine what we mean by +% "standard status" at the start of each entry handler and reuse the same +% format routines under the various inter-item separation schemes. For +% example, the standard status vector for the @book entry type may use +% commas for item separators, while the @electronic type may use periods, +% yet both entry handlers exploit many of the exact same format routines. +% +% Because format routines have write access to the output status vector of +% the previous item, they can override the punctuation choices of the +% previous format routine! Therefore, it becomes trivial to implement rules +% such as "Always use a period and a large space before the publisher." By +% pushing the generation of the closing quote mark to the output routine, we +% avoid all the problems caused by having to close a quote before having all +% the information required to determine what the punctuation should be. +% +% The IEEEtran.bst output state system can easily be expanded if needed. +% For instance, it is easy to add a "space.tie" attribute value if the +% bibliography rules mandate that two items have to be joined with an +% unbreakable space. + +FUNCTION {initialize.status.constants} +{ #0 'punct.no := + #1 'punct.comma := + #2 'punct.period := + #0 'space.no := + #1 'space.normal := + #2 'space.large := + #0 'quote.no := + #1 'quote.close := + #0 'cap.no := + #1 'cap.yes := + #0 'nline.no := + #1 'nline.newblock := +} + +FUNCTION {std.status.using.comma} +{ punct.comma 'punct.std := + space.normal 'space.std := + quote.no 'quote.std := + nline.no 'nline.std := + cap.no 'cap.std := +} + +FUNCTION {std.status.using.period} +{ punct.period 'punct.std := + space.normal 'space.std := + quote.no 'quote.std := + nline.no 'nline.std := + cap.yes 'cap.std := +} + +FUNCTION {initialize.prev.this.status} +{ punct.no 'prev.status.punct := + space.no 'prev.status.space := + quote.no 'prev.status.quote := + nline.no 'prev.status.nline := + punct.no 'this.status.punct := + space.no 'this.status.space := + quote.no 'this.status.quote := + nline.no 'this.status.nline := + cap.yes 'status.cap := +} + +FUNCTION {this.status.std} +{ punct.std 'this.status.punct := + space.std 'this.status.space := + quote.std 'this.status.quote := + nline.std 'this.status.nline := +} + +FUNCTION {cap.status.std}{ cap.std 'status.cap := } + +FUNCTION {this.to.prev.status} +{ this.status.punct 'prev.status.punct := + this.status.space 'prev.status.space := + this.status.quote 'prev.status.quote := + this.status.nline 'prev.status.nline := +} + + +FUNCTION {not} +{ { #0 } + { #1 } + if$ +} + +FUNCTION {and} +{ { skip$ } + { pop$ #0 } + if$ +} + +FUNCTION {or} +{ { pop$ #1 } + { skip$ } + if$ +} + + +% convert the strings "yes" or "no" to #1 or #0 respectively +FUNCTION {yes.no.to.int} +{ "l" change.case$ duplicate$ + "yes" = + { pop$ #1 } + { duplicate$ "no" = + { pop$ #0 } + { "unknown boolean " quote$ * swap$ * quote$ * + " in " * cite$ * warning$ + #0 + } + if$ + } + if$ +} + + +% pushes true if the single char string on the stack is in the +% range of "0" to "9" +FUNCTION {is.num} +{ chr.to.int$ + duplicate$ "0" chr.to.int$ < not + swap$ "9" chr.to.int$ > not and +} + +% multiplies the integer on the stack by a factor of 10 +FUNCTION {bump.int.mag} +{ #0 'multiresult := + { duplicate$ #0 > } + { #1 - + multiresult #10 + + 'multiresult := + } + while$ +pop$ +multiresult +} + +% converts a single character string on the stack to an integer +FUNCTION {char.to.integer} +{ duplicate$ + is.num + { chr.to.int$ "0" chr.to.int$ - } + {"noninteger character " quote$ * swap$ * quote$ * + " in integer field of " * cite$ * warning$ + #0 + } + if$ +} + +% converts a string on the stack to an integer +FUNCTION {string.to.integer} +{ duplicate$ text.length$ 'namesleft := + #1 'nameptr := + #0 'numnames := + { nameptr namesleft > not } + { duplicate$ nameptr #1 substring$ + char.to.integer numnames bump.int.mag + + 'numnames := + nameptr #1 + + 'nameptr := + } + while$ +pop$ +numnames +} + + + + +% The output routines write out the *next* to the top (previous) item on the +% stack, adding punctuation and such as needed. Since IEEEtran.bst maintains +% the output status for the top two items on the stack, these output +% routines have to consider the previous output status (which corresponds to +% the item that is being output). Full independent control of punctuation, +% closing quote marks, spacing, and newblock is provided. +% +% "output.nonnull" does not check for the presence of a previous empty +% item. +% +% "output" does check for the presence of a previous empty item and will +% remove an empty item rather than outputing it. +% +% "output.warn" is like "output", but will issue a warning if it detects +% an empty item. + +FUNCTION {output.nonnull} +{ swap$ + prev.status.punct punct.comma = + { "," * } + { skip$ } + if$ + prev.status.punct punct.period = + { add.period$ } + { skip$ } + if$ + prev.status.quote quote.close = + { "''" * } + { skip$ } + if$ + prev.status.space space.normal = + { " " * } + { skip$ } + if$ + prev.status.space space.large = + { large.space * } + { skip$ } + if$ + write$ + prev.status.nline nline.newblock = + { newline$ "\newblock " write$ } + { skip$ } + if$ +} + +FUNCTION {output} +{ duplicate$ empty$ + 'pop$ + 'output.nonnull + if$ +} + +FUNCTION {output.warn} +{ 't := + duplicate$ empty$ + { pop$ "empty " t * " in " * cite$ * warning$ } + 'output.nonnull + if$ +} + +% "fin.entry" is the output routine that handles the last item of the entry +% (which will be on the top of the stack when "fin.entry" is called). + +FUNCTION {fin.entry} +{ this.status.punct punct.no = + { skip$ } + { add.period$ } + if$ + this.status.quote quote.close = + { "''" * } + { skip$ } + if$ +write$ +newline$ +} + + +FUNCTION {is.last.char.not.punct} +{ duplicate$ + "}" * add.period$ + #-1 #1 substring$ "." = +} + +FUNCTION {is.multiple.pages} +{ 't := + #0 'multiresult := + { multiresult not + t empty$ not + and + } + { t #1 #1 substring$ + duplicate$ "-" = + swap$ duplicate$ "," = + swap$ "+" = + or or + { #1 'multiresult := } + { t #2 global.max$ substring$ 't := } + if$ + } + while$ + multiresult +} + +FUNCTION {capitalize}{ "u" change.case$ "t" change.case$ } + +FUNCTION {emphasize} +{ duplicate$ empty$ + { pop$ "" } + { "\emph{" swap$ * "}" * } + if$ +} + +FUNCTION {do.name.latex.cmd} +{ name.latex.cmd + empty$ + { skip$ } + { name.latex.cmd "{" * swap$ * "}" * } + if$ +} + +% IEEEtran.bst uses its own \BIBforeignlanguage command which directly +% invokes the TeX hyphenation patterns without the need of the Babel +% package. Babel does a lot more than switch hyphenation patterns and +% its loading can cause unintended effects in many class files (such as +% IEEEtran.cls). +FUNCTION {select.language} +{ duplicate$ empty$ 'pop$ + { language empty$ 'skip$ + { "\BIBforeignlanguage{" language * "}{" * swap$ * "}" * } + if$ + } + if$ +} + +FUNCTION {tie.or.space.prefix} +{ duplicate$ text.length$ #3 < + { "~" } + { " " } + if$ + swap$ +} + +FUNCTION {get.bbl.editor} +{ editor num.names$ #1 > 'bbl.editors 'bbl.editor if$ } + +FUNCTION {space.word}{ " " swap$ * " " * } + + +% Field Conditioners, Converters, Checkers and External Interfaces + +FUNCTION {empty.field.to.null.string} +{ duplicate$ empty$ + { pop$ "" } + { skip$ } + if$ +} + +FUNCTION {either.or.check} +{ empty$ + { pop$ } + { "can't use both " swap$ * " fields in " * cite$ * warning$ } + if$ +} + +FUNCTION {empty.entry.warn} +{ author empty$ title empty$ howpublished empty$ + month empty$ year empty$ note empty$ url empty$ + and and and and and and + { "all relevant fields are empty in " cite$ * warning$ } + 'skip$ + if$ +} + + +% The bibinfo system provides a way for the electronic parsing/acquisition +% of a bibliography's contents as is done by ReVTeX. For example, a field +% could be entered into the bibliography as: +% \bibinfo{volume}{2} +% Only the "2" would show up in the document, but the LaTeX \bibinfo command +% could do additional things with the information. IEEEtran.bst does provide +% a \bibinfo command via "\providecommand{\bibinfo}[2]{#2}". However, it is +% currently not used as the bogus bibinfo functions defined here output the +% entry values directly without the \bibinfo wrapper. The bibinfo functions +% themselves (and the calls to them) are retained for possible future use. +% +% bibinfo.check avoids acting on missing fields while bibinfo.warn will +% issue a warning message if a missing field is detected. Prior to calling +% the bibinfo functions, the user should push the field value and then its +% name string, in that order. + +FUNCTION {bibinfo.check} +{ swap$ duplicate$ missing$ + { pop$ pop$ "" } + { duplicate$ empty$ + { swap$ pop$ } + { swap$ pop$ } + if$ + } + if$ +} + +FUNCTION {bibinfo.warn} +{ swap$ duplicate$ missing$ + { swap$ "missing " swap$ * " in " * cite$ * warning$ pop$ "" } + { duplicate$ empty$ + { swap$ "empty " swap$ * " in " * cite$ * warning$ } + { swap$ pop$ } + if$ + } + if$ +} + + +% IEEE separates large numbers with more than 4 digits into groups of +% three. IEEE uses a small space to separate these number groups. +% Typical applications include patent and page numbers. + +% number of consecutive digits required to trigger the group separation. +FUNCTION {large.number.trigger}{ #5 } + +% For numbers longer than the trigger, this is the blocksize of the groups. +% The blocksize must be less than the trigger threshold, and 2 * blocksize +% must be greater than the trigger threshold (can't do more than one +% separation on the initial trigger). +FUNCTION {large.number.blocksize}{ #3 } + +% What is actually inserted between the number groups. +FUNCTION {large.number.separator}{ "\," } + +% So as to save on integer variables by reusing existing ones, numnames +% holds the current number of consecutive digits read and nameptr holds +% the number that will trigger an inserted space. +FUNCTION {large.number.separate} +{ 't := + "" + #0 'numnames := + large.number.trigger 'nameptr := + { t empty$ not } + { t #-1 #1 substring$ is.num + { numnames #1 + 'numnames := } + { #0 'numnames := + large.number.trigger 'nameptr := + } + if$ + t #-1 #1 substring$ swap$ * + t #-2 global.max$ substring$ 't := + numnames nameptr = + { duplicate$ #1 nameptr large.number.blocksize - substring$ swap$ + nameptr large.number.blocksize - #1 + global.max$ substring$ + large.number.separator swap$ * * + nameptr large.number.blocksize - 'numnames := + large.number.blocksize #1 + 'nameptr := + } + { skip$ } + if$ + } + while$ +} + +% Converts all single dashes "-" to double dashes "--". +FUNCTION {n.dashify} +{ large.number.separate + 't := + "" + { t empty$ not } + { t #1 #1 substring$ "-" = + { t #1 #2 substring$ "--" = not + { "--" * + t #2 global.max$ substring$ 't := + } + { { t #1 #1 substring$ "-" = } + { "-" * + t #2 global.max$ substring$ 't := + } + while$ + } + if$ + } + { t #1 #1 substring$ * + t #2 global.max$ substring$ 't := + } + if$ + } + while$ +} + + +% This function detects entries with names that are identical to that of +% the previous entry and replaces the repeated names with dashes (if the +% "is.dash.repeated.names" user control is nonzero). +FUNCTION {name.or.dash} +{ 's := + oldname empty$ + { s 'oldname := s } + { s oldname = + { is.dash.repeated.names + { repeated.name.dashes } + { s 'oldname := s } + if$ + } + { s 'oldname := s } + if$ + } + if$ +} + +% Converts the number string on the top of the stack to +% "numerical ordinal form" (e.g., "7" to "7th"). There is +% no artificial limit to the upper bound of the numbers as the +% least significant digit always determines the ordinal form. +FUNCTION {num.to.ordinal} +{ duplicate$ #-1 #1 substring$ "1" = + { bbl.st * } + { duplicate$ #-1 #1 substring$ "2" = + { bbl.nd * } + { duplicate$ #-1 #1 substring$ "3" = + { bbl.rd * } + { bbl.th * } + if$ + } + if$ + } + if$ +} + +% If the string on the top of the stack begins with a number, +% (e.g., 11th) then replace the string with the leading number +% it contains. Otherwise retain the string as-is. s holds the +% extracted number, t holds the part of the string that remains +% to be scanned. +FUNCTION {extract.num} +{ duplicate$ 't := + "" 's := + { t empty$ not } + { t #1 #1 substring$ + t #2 global.max$ substring$ 't := + duplicate$ is.num + { s swap$ * 's := } + { pop$ "" 't := } + if$ + } + while$ + s empty$ + 'skip$ + { pop$ s } + if$ +} + +% Converts the word number string on the top of the stack to +% Arabic string form. Will be successful up to "tenth". +FUNCTION {word.to.num} +{ duplicate$ "l" change.case$ 's := + s "first" = + { pop$ "1" } + { skip$ } + if$ + s "second" = + { pop$ "2" } + { skip$ } + if$ + s "third" = + { pop$ "3" } + { skip$ } + if$ + s "fourth" = + { pop$ "4" } + { skip$ } + if$ + s "fifth" = + { pop$ "5" } + { skip$ } + if$ + s "sixth" = + { pop$ "6" } + { skip$ } + if$ + s "seventh" = + { pop$ "7" } + { skip$ } + if$ + s "eighth" = + { pop$ "8" } + { skip$ } + if$ + s "ninth" = + { pop$ "9" } + { skip$ } + if$ + s "tenth" = + { pop$ "10" } + { skip$ } + if$ +} + + +% Converts the string on the top of the stack to numerical +% ordinal (e.g., "11th") form. +FUNCTION {convert.edition} +{ duplicate$ empty$ 'skip$ + { duplicate$ #1 #1 substring$ is.num + { extract.num + num.to.ordinal + } + { word.to.num + duplicate$ #1 #1 substring$ is.num + { num.to.ordinal } + { "edition ordinal word " quote$ * edition * quote$ * + " may be too high (or improper) for conversion" * " in " * cite$ * warning$ + } + if$ + } + if$ + } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% LATEX BIBLIOGRAPHY CODE %% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {start.entry} +{ newline$ + "\bibitem{" write$ + cite$ write$ + "}" write$ + newline$ + "" + initialize.prev.this.status +} + +% Here we write out all the LaTeX code that we will need. The most involved +% code sequences are those that control the alternate interword spacing and +% foreign language hyphenation patterns. The heavy use of \providecommand +% gives users a way to override the defaults. Special thanks to Javier Bezos, +% Johannes Braams, Robin Fairbairns, Heiko Oberdiek, Donald Arseneau and all +% the other gurus on comp.text.tex for their help and advice on the topic of +% \selectlanguage, Babel and BibTeX. +FUNCTION {begin.bib} +{ "% Generated by IEEEtranS.bst, version: " bst.file.version * " (" * bst.file.date * ")" * + write$ newline$ + preamble$ empty$ 'skip$ + { preamble$ write$ newline$ } + if$ + "\begin{thebibliography}{" longest.label * "}" * + write$ newline$ + "\providecommand{\url}[1]{#1}" + write$ newline$ + "\csname url@samestyle\endcsname" + write$ newline$ + "\providecommand{\newblock}{\relax}" + write$ newline$ + "\providecommand{\bibinfo}[2]{#2}" + write$ newline$ + "\providecommand{\BIBentrySTDinterwordspacing}{\spaceskip=0pt\relax}" + write$ newline$ + "\providecommand{\BIBentryALTinterwordstretchfactor}{" + ALTinterwordstretchfactor * "}" * + write$ newline$ + "\providecommand{\BIBentryALTinterwordspacing}{\spaceskip=\fontdimen2\font plus " + write$ newline$ + "\BIBentryALTinterwordstretchfactor\fontdimen3\font minus \fontdimen4\font\relax}" + write$ newline$ + "\providecommand{\BIBforeignlanguage}[2]{{%" + write$ newline$ + "\expandafter\ifx\csname l@#1\endcsname\relax" + write$ newline$ + "\typeout{** WARNING: IEEEtranS.bst: No hyphenation pattern has been}%" + write$ newline$ + "\typeout{** loaded for the language `#1'. Using the pattern for}%" + write$ newline$ + "\typeout{** the default language instead.}%" + write$ newline$ + "\else" + write$ newline$ + "\language=\csname l@#1\endcsname" + write$ newline$ + "\fi" + write$ newline$ + "#2}}" + write$ newline$ + "\providecommand{\BIBdecl}{\relax}" + write$ newline$ + "\BIBdecl" + write$ newline$ +} + +FUNCTION {end.bib} +{ newline$ "\end{thebibliography}" write$ newline$ } + +FUNCTION {if.url.alt.interword.spacing} +{ is.use.alt.interword.spacing + {url empty$ 'skip$ {"\BIBentryALTinterwordspacing" write$ newline$} if$} + { skip$ } + if$ +} + +FUNCTION {if.url.std.interword.spacing} +{ is.use.alt.interword.spacing + {url empty$ 'skip$ {"\BIBentrySTDinterwordspacing" write$ newline$} if$} + { skip$ } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%%%%% +%% LONGEST LABEL PASS %% +%%%%%%%%%%%%%%%%%%%%%%%% + +FUNCTION {initialize.longest.label} +{ "" 'longest.label := + #1 'number.label := + #0 'longest.label.width := +} + +FUNCTION {longest.label.pass} +{ type$ "ieeetranbstctl" = + { skip$ } + { number.label int.to.str$ 'label := + number.label #1 + 'number.label := + label width$ longest.label.width > + { label 'longest.label := + label width$ 'longest.label.width := + } + { skip$ } + if$ + } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%%% +%% FORMAT HANDLERS %% +%%%%%%%%%%%%%%%%%%%%% + +%% Lower Level Formats (used by higher level formats) + +FUNCTION {format.address.org.or.pub.date} +{ 't := + "" + year empty$ + { "empty year in " cite$ * warning$ } + { skip$ } + if$ + address empty$ t empty$ and + year empty$ and month empty$ and + { skip$ } + { this.to.prev.status + this.status.std + cap.status.std + address "address" bibinfo.check * + t empty$ + { skip$ } + { punct.period 'prev.status.punct := + space.large 'prev.status.space := + address empty$ + { skip$ } + { ": " * } + if$ + t * + } + if$ + year empty$ month empty$ and + { skip$ } + { t empty$ address empty$ and + { skip$ } + { ", " * } + if$ + month empty$ + { year empty$ + { skip$ } + { year "year" bibinfo.check * } + if$ + } + { month "month" bibinfo.check * + year empty$ + { skip$ } + { " " * year "year" bibinfo.check * } + if$ + } + if$ + } + if$ + } + if$ +} + + +FUNCTION {format.names} +{ 'bibinfo := + duplicate$ empty$ 'skip$ { + this.to.prev.status + this.status.std + 's := + "" 't := + #1 'nameptr := + s num.names$ 'numnames := + numnames 'namesleft := + { namesleft #0 > } + { s nameptr + name.format.string + format.name$ + bibinfo bibinfo.check + 't := + nameptr #1 > + { nameptr num.names.shown.with.forced.et.al #1 + = + numnames max.num.names.before.forced.et.al > + is.forced.et.al and and + { "others" 't := + #1 'namesleft := + } + { skip$ } + if$ + namesleft #1 > + { ", " * t do.name.latex.cmd * } + { s nameptr "{ll}" format.name$ duplicate$ "others" = + { 't := } + { pop$ } + if$ + t "others" = + { " " * bbl.etal emphasize * } + { numnames #2 > + { "," * } + { skip$ } + if$ + bbl.and + space.word * t do.name.latex.cmd * + } + if$ + } + if$ + } + { t do.name.latex.cmd } + if$ + nameptr #1 + 'nameptr := + namesleft #1 - 'namesleft := + } + while$ + cap.status.std + } if$ +} + + + + +%% Higher Level Formats + +%% addresses/locations + +FUNCTION {format.address} +{ address duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + + + +%% author/editor names + +FUNCTION {format.authors}{ author "author" format.names } + +FUNCTION {format.editors} +{ editor "editor" format.names duplicate$ empty$ 'skip$ + { ", " * + get.bbl.editor + capitalize + * + } + if$ +} + + + +%% date + +FUNCTION {format.date} +{ + month "month" bibinfo.check duplicate$ empty$ + year "year" bibinfo.check duplicate$ empty$ + { swap$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + "there's a month but no year in " cite$ * warning$ } + if$ + * + } + { this.to.prev.status + this.status.std + cap.status.std + swap$ 'skip$ + { + swap$ + " " * swap$ + } + if$ + * + } + if$ +} + +FUNCTION {format.date.electronic} +{ month "month" bibinfo.check duplicate$ empty$ + year "year" bibinfo.check duplicate$ empty$ + { swap$ + { pop$ } + { "there's a month but no year in " cite$ * warning$ + pop$ ")" * "(" swap$ * + this.to.prev.status + punct.no 'this.status.punct := + space.normal 'this.status.space := + quote.no 'this.status.quote := + cap.yes 'status.cap := + } + if$ + } + { swap$ + { swap$ pop$ ")" * "(" swap$ * } + { "(" swap$ * ", " * swap$ * ")" * } + if$ + this.to.prev.status + punct.no 'this.status.punct := + space.normal 'this.status.space := + quote.no 'this.status.quote := + cap.yes 'status.cap := + } + if$ +} + + + +%% edition/title + +% Note: IEEE considers the edition to be closely associated with +% the title of a book. So, in IEEEtran.bst the edition is normally handled +% within the formatting of the title. The format.edition function is +% retained here for possible future use. +FUNCTION {format.edition} +{ edition duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + convert.edition + status.cap + { "t" } + { "l" } + if$ change.case$ + "edition" bibinfo.check + "~" * bbl.edition * + cap.status.std + } + if$ +} + +% This is used to format the booktitle of a conference proceedings. +% Here we use the "intype" field to provide the user a way to +% override the word "in" (e.g., with things like "presented at") +% Use of intype stops the emphasis of the booktitle to indicate that +% we no longer mean the written conference proceedings, but the +% conference itself. +FUNCTION {format.in.booktitle} +{ booktitle "booktitle" bibinfo.check duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + select.language + intype missing$ + { emphasize + bbl.in " " * + } + { intype " " * } + if$ + swap$ * + cap.status.std + } + if$ +} + +% This is used to format the booktitle of collection. +% Here the "intype" field is not supported, but "edition" is. +FUNCTION {format.in.booktitle.edition} +{ booktitle "booktitle" bibinfo.check duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + select.language + emphasize + edition empty$ 'skip$ + { ", " * + edition + convert.edition + "l" change.case$ + * "~" * bbl.edition * + } + if$ + bbl.in " " * swap$ * + cap.status.std + } + if$ +} + +FUNCTION {format.article.title} +{ title duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + "t" change.case$ + } + if$ + "title" bibinfo.check + duplicate$ empty$ 'skip$ + { quote.close 'this.status.quote := + is.last.char.not.punct + { punct.std 'this.status.punct := } + { punct.no 'this.status.punct := } + if$ + select.language + "``" swap$ * + cap.status.std + } + if$ +} + +FUNCTION {format.article.title.electronic} +{ title duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + "t" change.case$ + } + if$ + "title" bibinfo.check + duplicate$ empty$ + { skip$ } + { select.language } + if$ +} + +FUNCTION {format.book.title.edition} +{ title "title" bibinfo.check + duplicate$ empty$ + { "empty title in " cite$ * warning$ } + { this.to.prev.status + this.status.std + select.language + emphasize + edition empty$ 'skip$ + { ", " * + edition + convert.edition + status.cap + { "t" } + { "l" } + if$ + change.case$ + * "~" * bbl.edition * + } + if$ + cap.status.std + } + if$ +} + +FUNCTION {format.book.title} +{ title "title" bibinfo.check + duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + select.language + emphasize + } + if$ +} + + + +%% journal + +FUNCTION {format.journal} +{ journal duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + select.language + emphasize + } + if$ +} + + + +%% how published + +FUNCTION {format.howpublished} +{ howpublished duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + + + +%% institutions/organization/publishers/school + +FUNCTION {format.institution} +{ institution duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + +FUNCTION {format.organization} +{ organization duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + +FUNCTION {format.address.publisher.date} +{ publisher "publisher" bibinfo.warn format.address.org.or.pub.date } + +FUNCTION {format.address.publisher.date.nowarn} +{ publisher "publisher" bibinfo.check format.address.org.or.pub.date } + +FUNCTION {format.address.organization.date} +{ organization "organization" bibinfo.check format.address.org.or.pub.date } + +FUNCTION {format.school} +{ school duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + cap.status.std + } + if$ +} + + + +%% volume/number/series/chapter/pages + +FUNCTION {format.volume} +{ volume empty.field.to.null.string + duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + bbl.volume + status.cap + { capitalize } + { skip$ } + if$ + swap$ tie.or.space.prefix + "volume" bibinfo.check + * * + cap.status.std + } + if$ +} + +FUNCTION {format.number} +{ number empty.field.to.null.string + duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + status.cap + { bbl.number capitalize } + { bbl.number } + if$ + swap$ tie.or.space.prefix + "number" bibinfo.check + * * + cap.status.std + } + if$ +} + +FUNCTION {format.number.if.use.for.article} +{ is.use.number.for.article + { format.number } + { "" } + if$ +} + +% IEEE does not seem to tie the series so closely with the volume +% and number as is done in other bibliography styles. Instead the +% series is treated somewhat like an extension of the title. +FUNCTION {format.series} +{ series empty$ + { "" } + { this.to.prev.status + this.status.std + bbl.series " " * + series "series" bibinfo.check * + cap.status.std + } + if$ +} + + +FUNCTION {format.chapter} +{ chapter empty$ + { "" } + { this.to.prev.status + this.status.std + type empty$ + { bbl.chapter } + { type "l" change.case$ + "type" bibinfo.check + } + if$ + chapter tie.or.space.prefix + "chapter" bibinfo.check + * * + cap.status.std + } + if$ +} + + +% The intended use of format.paper is for paper numbers of inproceedings. +% The paper type can be overridden via the type field. +% We allow the type to be displayed even if the paper number is absent +% for things like "postdeadline paper" +FUNCTION {format.paper} +{ is.use.paper + { paper empty$ + { type empty$ + { "" } + { this.to.prev.status + this.status.std + type "type" bibinfo.check + cap.status.std + } + if$ + } + { this.to.prev.status + this.status.std + type empty$ + { bbl.paper } + { type "type" bibinfo.check } + if$ + " " * paper + "paper" bibinfo.check + * + cap.status.std + } + if$ + } + { "" } + if$ +} + + +FUNCTION {format.pages} +{ pages duplicate$ empty$ 'skip$ + { this.to.prev.status + this.status.std + duplicate$ is.multiple.pages + { + bbl.pages swap$ + n.dashify + } + { + bbl.page swap$ + } + if$ + tie.or.space.prefix + "pages" bibinfo.check + * * + cap.status.std + } + if$ +} + + + +%% technical report number + +FUNCTION {format.tech.report.number} +{ number "number" bibinfo.check + this.to.prev.status + this.status.std + cap.status.std + type duplicate$ empty$ + { pop$ + bbl.techrep + } + { skip$ } + if$ + "type" bibinfo.check + swap$ duplicate$ empty$ + { pop$ } + { tie.or.space.prefix * * } + if$ +} + + + +%% note + +FUNCTION {format.note} +{ note empty$ + { "" } + { this.to.prev.status + this.status.std + punct.period 'this.status.punct := + note #1 #1 substring$ + duplicate$ "{" = + { skip$ } + { status.cap + { "u" } + { "l" } + if$ + change.case$ + } + if$ + note #2 global.max$ substring$ * "note" bibinfo.check + cap.yes 'status.cap := + } + if$ +} + + + +%% patent + +FUNCTION {format.patent.date} +{ this.to.prev.status + this.status.std + year empty$ + { monthfiled duplicate$ empty$ + { "monthfiled" bibinfo.check pop$ "" } + { "monthfiled" bibinfo.check } + if$ + dayfiled duplicate$ empty$ + { "dayfiled" bibinfo.check pop$ "" * } + { "dayfiled" bibinfo.check + monthfiled empty$ + { "dayfiled without a monthfiled in " cite$ * warning$ + * + } + { " " swap$ * * } + if$ + } + if$ + yearfiled empty$ + { "no year or yearfiled in " cite$ * warning$ } + { yearfiled "yearfiled" bibinfo.check + swap$ + duplicate$ empty$ + { pop$ } + { ", " * swap$ * } + if$ + } + if$ + } + { month duplicate$ empty$ + { "month" bibinfo.check pop$ "" } + { "month" bibinfo.check } + if$ + day duplicate$ empty$ + { "day" bibinfo.check pop$ "" * } + { "day" bibinfo.check + month empty$ + { "day without a month in " cite$ * warning$ + * + } + { " " swap$ * * } + if$ + } + if$ + year "year" bibinfo.check + swap$ + duplicate$ empty$ + { pop$ } + { ", " * swap$ * } + if$ + } + if$ + cap.status.std +} + +FUNCTION {format.patent.nationality.type.number} +{ this.to.prev.status + this.status.std + nationality duplicate$ empty$ + { "nationality" bibinfo.warn pop$ "" } + { "nationality" bibinfo.check + duplicate$ "l" change.case$ "united states" = + { pop$ bbl.patentUS } + { skip$ } + if$ + " " * + } + if$ + type empty$ + { bbl.patent "type" bibinfo.check } + { type "type" bibinfo.check } + if$ + * + number duplicate$ empty$ + { "number" bibinfo.warn pop$ } + { "number" bibinfo.check + large.number.separate + swap$ " " * swap$ * + } + if$ + cap.status.std +} + + + +%% standard + +FUNCTION {format.organization.institution.standard.type.number} +{ this.to.prev.status + this.status.std + organization duplicate$ empty$ + { pop$ + institution duplicate$ empty$ + { "institution" bibinfo.warn } + { "institution" bibinfo.warn " " * } + if$ + } + { "organization" bibinfo.warn " " * } + if$ + type empty$ + { bbl.standard "type" bibinfo.check } + { type "type" bibinfo.check } + if$ + * + number duplicate$ empty$ + { "number" bibinfo.check pop$ } + { "number" bibinfo.check + large.number.separate + swap$ " " * swap$ * + } + if$ + cap.status.std +} + +FUNCTION {format.revision} +{ revision empty$ + { "" } + { this.to.prev.status + this.status.std + bbl.revision + revision tie.or.space.prefix + "revision" bibinfo.check + * * + cap.status.std + } + if$ +} + + +%% thesis + +FUNCTION {format.master.thesis.type} +{ this.to.prev.status + this.status.std + type empty$ + { + bbl.mthesis + } + { + type "type" bibinfo.check + } + if$ +cap.status.std +} + +FUNCTION {format.phd.thesis.type} +{ this.to.prev.status + this.status.std + type empty$ + { + bbl.phdthesis + } + { + type "type" bibinfo.check + } + if$ +cap.status.std +} + + + +%% URL + +FUNCTION {format.url} +{ url empty$ + { "" } + { this.to.prev.status + this.status.std + cap.yes 'status.cap := + name.url.prefix " " * + "\url{" * url * "}" * + punct.no 'this.status.punct := + punct.period 'prev.status.punct := + space.normal 'this.status.space := + space.normal 'prev.status.space := + quote.no 'this.status.quote := + } + if$ +} + + + + +%%%%%%%%%%%%%%%%%%%% +%% ENTRY HANDLERS %% +%%%%%%%%%%%%%%%%%%%% + + +% Note: In many journals, IEEE (or the authors) tend not to show the number +% for articles, so the display of the number is controlled here by the +% switch "is.use.number.for.article" +FUNCTION {article} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.journal "journal" bibinfo.check "journal" output.warn + format.volume output + format.number.if.use.for.article output + format.pages output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {book} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + author empty$ + { format.editors "author and editor" output.warn } + { format.authors output.nonnull } + if$ + name.or.dash + format.book.title.edition output + format.series output + author empty$ + { skip$ } + { format.editors output } + if$ + format.address.publisher.date output + format.volume output + format.number output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {booklet} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.article.title "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.date output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {electronic} +{ std.status.using.period + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.date.electronic output + format.article.title.electronic output + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.note output + format.url output + fin.entry + empty.entry.warn + if.url.std.interword.spacing +} + +FUNCTION {inbook} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + author empty$ + { format.editors "author and editor" output.warn } + { format.authors output.nonnull } + if$ + name.or.dash + format.book.title.edition output + format.series output + format.address.publisher.date output + format.volume output + format.number output + format.chapter output + format.pages output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {incollection} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.in.booktitle.edition "booktitle" output.warn + format.series output + format.editors output + format.address.publisher.date.nowarn output + format.volume output + format.number output + format.chapter output + format.pages output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {inproceedings} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.in.booktitle "booktitle" output.warn + format.series output + format.editors output + format.volume output + format.number output + publisher empty$ + { format.address.organization.date output } + { format.organization "organization" bibinfo.check output + format.address.publisher.date output + } + if$ + format.paper output + format.pages output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {manual} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.book.title.edition "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.date output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {mastersthesis} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.master.thesis.type output.nonnull + format.school "school" bibinfo.warn output + format.address "address" bibinfo.check output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {misc} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.article.title output + format.howpublished "howpublished" bibinfo.check output + format.organization "organization" bibinfo.check output + format.address "address" bibinfo.check output + format.pages output + format.date output + format.note output + format.url output + fin.entry + empty.entry.warn + if.url.std.interword.spacing +} + +FUNCTION {patent} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.article.title output + format.patent.nationality.type.number output + format.patent.date output + format.note output + format.url output + fin.entry + empty.entry.warn + if.url.std.interword.spacing +} + +FUNCTION {periodical} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.editors output + name.or.dash + format.book.title "title" output.warn + format.series output + format.volume output + format.number output + format.organization "organization" bibinfo.check output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {phdthesis} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.phd.thesis.type output.nonnull + format.school "school" bibinfo.warn output + format.address "address" bibinfo.check output + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {proceedings} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.editors output + name.or.dash + format.book.title "title" output.warn + format.series output + format.volume output + format.number output + publisher empty$ + { format.address.organization.date output } + { format.organization "organization" bibinfo.check output + format.address.publisher.date output + } + if$ + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {standard} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors output + name.or.dash + format.book.title "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.organization.institution.standard.type.number output + format.revision output + format.date output + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {techreport} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.howpublished "howpublished" bibinfo.check output + format.institution "institution" bibinfo.warn output + format.address "address" bibinfo.check output + format.tech.report.number output.nonnull + format.date "year" output.warn + format.note output + format.url output + fin.entry + if.url.std.interword.spacing +} + +FUNCTION {unpublished} +{ std.status.using.comma + start.entry + if.url.alt.interword.spacing + format.authors "author" output.warn + name.or.dash + format.article.title "title" output.warn + format.date output + format.note "note" output.warn + format.url output + fin.entry + if.url.std.interword.spacing +} + + +% The special entry type which provides the user interface to the +% BST controls +FUNCTION {IEEEtranBSTCTL} +{ is.print.banners.to.terminal + { "** IEEEtran BST control entry " quote$ * cite$ * quote$ * " detected." * + top$ + } + { skip$ } + if$ + CTLuse_article_number + empty$ + { skip$ } + { CTLuse_article_number + yes.no.to.int + 'is.use.number.for.article := + } + if$ + CTLuse_paper + empty$ + { skip$ } + { CTLuse_paper + yes.no.to.int + 'is.use.paper := + } + if$ + CTLuse_forced_etal + empty$ + { skip$ } + { CTLuse_forced_etal + yes.no.to.int + 'is.forced.et.al := + } + if$ + CTLmax_names_forced_etal + empty$ + { skip$ } + { CTLmax_names_forced_etal + string.to.integer + 'max.num.names.before.forced.et.al := + } + if$ + CTLnames_show_etal + empty$ + { skip$ } + { CTLnames_show_etal + string.to.integer + 'num.names.shown.with.forced.et.al := + } + if$ + CTLuse_alt_spacing + empty$ + { skip$ } + { CTLuse_alt_spacing + yes.no.to.int + 'is.use.alt.interword.spacing := + } + if$ + CTLalt_stretch_factor + empty$ + { skip$ } + { CTLalt_stretch_factor + 'ALTinterwordstretchfactor := + "\renewcommand{\BIBentryALTinterwordstretchfactor}{" + ALTinterwordstretchfactor * "}" * + write$ newline$ + } + if$ + CTLdash_repeated_names + empty$ + { skip$ } + { CTLdash_repeated_names + yes.no.to.int + 'is.dash.repeated.names := + } + if$ + CTLname_format_string + empty$ + { skip$ } + { CTLname_format_string + 'name.format.string := + } + if$ + CTLname_latex_cmd + empty$ + { skip$ } + { CTLname_latex_cmd + 'name.latex.cmd := + } + if$ + CTLname_url_prefix + missing$ + { skip$ } + { CTLname_url_prefix + 'name.url.prefix := + } + if$ + + + num.names.shown.with.forced.et.al max.num.names.before.forced.et.al > + { "CTLnames_show_etal cannot be greater than CTLmax_names_forced_etal in " cite$ * warning$ + max.num.names.before.forced.et.al 'num.names.shown.with.forced.et.al := + } + { skip$ } + if$ +} + + +%%%%%%%%%%%%%%%%%%% +%% ENTRY ALIASES %% +%%%%%%%%%%%%%%%%%%% +FUNCTION {conference}{inproceedings} +FUNCTION {online}{electronic} +FUNCTION {internet}{electronic} +FUNCTION {webpage}{electronic} +FUNCTION {www}{electronic} +FUNCTION {default.type}{misc} + + + +%%%%%%%%%%%%%%%%%% +%% MAIN PROGRAM %% +%%%%%%%%%%%%%%%%%% + +READ + +EXECUTE {initialize.controls} +EXECUTE {initialize.status.constants} +EXECUTE {banner.message} + + + +% BEGIN sort code based on that of plain.bst + +FUNCTION {sortify} +{ purify$ + "l" change.case$ +} + +INTEGERS { len } + +FUNCTION {chop.word} +{ 's := + 'len := + s #1 len substring$ = + { s len #1 + global.max$ substring$ } + { s } + if$ +} + +FUNCTION {sort.format.names} +{ 's := + #1 'nameptr := + "" + s num.names$ 'numnames := + numnames 'namesleft := + { namesleft #0 > } + { nameptr #1 > + { " " * } + { skip$ } + if$ + s nameptr "{vv{ } }{ll{ }}{ ff{ }}{ jj{ }}" format.name$ 't := + nameptr numnames = t "others" = and + { "et al" * } + { t sortify * } + if$ + nameptr #1 + 'nameptr := + namesleft #1 - 'namesleft := + } + while$ +} + +FUNCTION {sort.format.title} +{ 't := + "A " #2 + "An " #3 + "The " #4 t chop.word + chop.word + chop.word + sortify + #1 global.max$ substring$ +} + +FUNCTION {author.sort} +{ author empty$ + { key empty$ + { "to sort, need author or key in " cite$ * warning$ "" } + { key sortify } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {author.editor.sort} +{ author empty$ + { editor empty$ + { key empty$ + { "to sort, need author, editor, or key in " cite$ * warning$ "" } + { key sortify } + if$ + } + { editor sort.format.names } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {author.organization.sort} +{ author empty$ + { organization empty$ + { key empty$ + { "to sort, need author, organization, or key in " cite$ * warning$ "" } + { key sortify } + if$ + } + { "The " #4 organization chop.word sortify } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {editor.organization.sort} +{ editor empty$ + { organization empty$ + { key empty$ + { "to sort, need editor, organization, or key in " cite$ * warning$ "" } + { key sortify } + if$ + } + { "The " #4 organization chop.word sortify } + if$ + } + { editor sort.format.names } + if$ +} + +FUNCTION {author.organization.institution.sort} +{ author empty$ + { organization empty$ + { institution empty$ + { key empty$ + { "to sort, need author, organization, institution or key in " cite$ * warning$ "" } + { key sortify } + if$ + } + { "The " #4 institution chop.word sortify } + if$ + } + { "The " #4 organization chop.word sortify } + if$ + } + { author sort.format.names } + if$ +} + + +FUNCTION {presort} +{ type$ "ieeetranbstctl" = + { key empty$ + { "_" } + { key sortify } + if$ + } + { type$ "book" = + type$ "inbook" = + or + { author.editor.sort } + { type$ "proceedings" = + type$ "periodical" = + or + { editor.organization.sort } + { type$ "manual" = + type$ "electronic" = + type$ "misc" = + or or + { author.organization.sort } + { type$ "standard" = + { author.organization.institution.sort } + { author.sort } + if$ + } + if$ + } + if$ + } + if$ + " " + * + type$ "patent" = + { year empty$ + { yearfiled } + { year } + if$ + } + { year } + if$ + empty.field.to.null.string sortify + * + " " + * + title empty.field.to.null.string + sort.format.title + * + } + if$ + #1 entry.max$ substring$ + 'sort.key$ := +} + +ITERATE {presort} + +SORT + +% END sort code based on that of plain.bst + + + +EXECUTE {initialize.longest.label} +ITERATE {longest.label.pass} + +EXECUTE {begin.bib} +ITERATE {call.type$} +EXECUTE {end.bib} + +EXECUTE{completed.message} + + +%% That's all folks, mds. diff --git a/standard/Report/IEEEtranBST2/IEEEtran_bst_HOWTO.pdf b/standard/Report/IEEEtranBST2/IEEEtran_bst_HOWTO.pdf new file mode 100644 index 0000000000000000000000000000000000000000..c3af20e2bee036486291076fd4b318d891bf3f77 Binary files /dev/null and b/standard/Report/IEEEtranBST2/IEEEtran_bst_HOWTO.pdf differ diff --git a/standard/Report/IEEEtranBST2/README b/standard/Report/IEEEtranBST2/README new file mode 100644 index 0000000000000000000000000000000000000000..e31ebb8766d0846a0cb6776ef283239897d8f216 --- /dev/null +++ b/standard/Report/IEEEtranBST2/README @@ -0,0 +1,144 @@ + +January 11, 2007 + + +IEEEtran.bst is the official BibTeX style for authors of the Institute of +Electrical and Electronics Engineers (IEEE) Transactions journals and +conferences. + +It also may have applications for other academic work such as theses and +technical reports. The alphanumeric and natbib variants extend the +applicability of the IEEEtran bibstyle family to the natural sciences +and beyond. + +The IEEEtran bibstyle is a very comprehensive BibTeX style which provides +many features beyond the standard BibTeX styles, including full support +for references of online documents, patents, periodicals and standards. +See the provided user manual for detailed usage information. + +The latest version of the IEEEtran BibTeX style can be found at CTAN: + +http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/bibtex/ + +as well as within IEEE's site: + +http://www.ieee.org/ + +Note that the packages at IEEE's site do not contain the natbib and +alphanumeric variants (e.g., IEEEtranN.bst, etc.) as these are not used +for IEEE related work. These files can be obtained on CTAN. + +For helpful tips, answers to frequently asked questions and other support, +visit the IEEEtran home page at my website: + +http://www.michaelshell.org/tex/ieeetran/ + + +Enjoy! + +Michael Shell +http://www.michaelshell.org/ + +******* +Version 1.12 (2007/01/11) changes: + + 1. Fixed bug with unwanted comma before "et al." when an entry contained + more than two author names. Thanks to Pallav Gupta for reporting this. + + 2. Fixed bug with anomalous closing quote in tech reports that have a + type, but without a number or address. Thanks to Mehrdad Mirreza for + reporting this. + + 3. Use braces in \providecommand in begin.bib to better support + latex2html. TeX style length assignments OK with recent versions + of latex2html - 1.71 (2002/2/1) or later is strongly recommended. + Use of the language field still causes trouble with latex2html. + Thanks to Federico Beffa for reporting this. + + 4. Added IEEEtran.bst ID and version comment string to .bbl output. + + 5. Provide a \BIBdecl hook that allows the user to execute commands + just prior to the first entry. + + 6. Use default urlstyle (is using url.sty) of "same" rather than rm to + better work with a wider variety of bibliography styles. + + 7. Changed month abbreviations from Sept., July and June to Sep., Jul., + and Jun., respectively, as IEEE now does. Thanks to Moritz Borgmann + for reporting this. + + 8. Control entry types should not be considered when calculating longest + label width. + + 9. Added alias www for electronic/online. + +10. Updated full and abbreviated journal name string definitions in + IEEEfull.bib and IEEEabrv.bib. + +11. New IEEEtranSA.bst, IEEEtranN.bst, and IEEEtranSN.bst variants for + alphanumeric citation tags and natbib compatibility. + + +********************************** Files ********************************** + +README - This file. + +IEEEtran_bst_HOWTO.pdf - The user manual. + +IEEEtran.bst - The standard IEEEtran BibTeX style file. For use + with IEEE work. + +IEEEtranS.bst - A version of IEEEtran.bst that sorts the entries. + Some IEEE conferences/publications may use/allow + sorted bibliographies. + +IEEEexample.bib - An example BibTeX database that contains the + references shown in the user manual. + +IEEEabrv.bib - String definitions for the abbreviated names of + IEEE journals. (For use with IEEE work.) + +IEEEfull.bib - String definitions for the full names of IEEE + journals. (Do not use for IEEE work.) + + +Carried on CTAN only, for non-IEEE related work: + +IEEEtranSA.bst - Like IEEEtranS.bst, but with alphanumeric citation + tags like alpha.bst. Not for normal IEEE use. + +EEEtranN.bst - Like IEEEtran.bst, but based on plainnat.bst and + is compatible with Patrick W. Daly's natbib + package. Not for normal IEEE use. + +IEEEtranSN.bst - Sorting version of IEEEtranN.bst. Not for normal + IEEE use + +*************************************************************************** +Legal Notice: +This code is offered as-is without any warranty either expressed or +implied; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE! +User assumes all risk. +In no event shall IEEE or any contributor to this code be liable for +any damages or losses, including, but not limited to, incidental, +consequential, or any other damages, resulting from the use or misuse +of any information contained here. + +All comments are the opinions of their respective authors and are not +necessarily endorsed by the IEEE. + +This work is distributed under the LaTeX Project Public License (LPPL) +( http://www.latex-project.org/ ) version 1.3, and may be freely used, +distributed and modified. A copy of the LPPL, version 1.3, is included +in the base LaTeX documentation of all distributions of LaTeX released +2003/12/01 or later. +Retain all contribution notices and credits. +** Modified files should be clearly indicated as such, including ** +** renaming them and changing author support contact information. ** + +File list of work: IEEEtran_bst_HOWTO.pdf, IEEEtran.bst, IEEEtranS.bst, + IEEEtranSA.bst, IEEEtranN.bst, IEEEtranSN.bst, + IEEEexample.bib, IEEEabrv.bib, IEEEfull.bib + +*************************************************************************** diff --git a/standard/Report/figures/4x4_multiplier.png b/standard/Report/figures/4x4_multiplier.png new file mode 100644 index 0000000000000000000000000000000000000000..fa4401d8511386776b5488b3290d2d65ab7a43c2 Binary files /dev/null and b/standard/Report/figures/4x4_multiplier.png differ diff --git a/standard/Report/figures/full_adder.jpeg b/standard/Report/figures/full_adder.jpeg new file mode 100644 index 0000000000000000000000000000000000000000..0ab1d445596bad66a49f9be551f32bdc3dcb4859 Binary files /dev/null and b/standard/Report/figures/full_adder.jpeg differ diff --git a/standard/Report/figures/full_adder.png b/standard/Report/figures/full_adder.png new file mode 100644 index 0000000000000000000000000000000000000000..0c0f73aac056d8c1a848be88d1fdc7e7a9c47148 Binary files /dev/null and b/standard/Report/figures/full_adder.png differ diff --git a/standard/Report/figures/half_adder.png b/standard/Report/figures/half_adder.png new file mode 100644 index 0000000000000000000000000000000000000000..27de84a07236f764fa25322fd7b9c577bd49cc3f Binary files /dev/null and b/standard/Report/figures/half_adder.png differ