Commit 14583cb2 authored by 袁通's avatar 袁通
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### Design of Basic Gates

<center>
  <figure>
    <img src="Design/Design_figures/inv_schematic.png" style="zoom:30%;" />
    <img src="Design/Design_figures/inv_layout.png" style="zoom:30%;" />
  <figure>
<center>





### Design of Adders



### Design of the multiplier

## Performance

### Area of the Layout

As we tested, the area of the layout is **((-11.2, -95)(53.2, 2)), 6246.8$\mu m^2$**
As we tested, the area of the layout is **((-11.2, -95)(53.2, 2)), 6246.8 um2**

## Propagation delay

Here we will compare the post-layout delay measurements with the schematic level delay measurement 50f F cap is attached to the output. We apply two set of input to the multiplier so we can get the transfer data of all output. The first set is $ 0000 \times 1111 = 11100001$ and the second set is $ 0010 \times 1111 = 00011110$. As we measure, the maxmun down-to-up delay is **1ns** and uo-to-down delay is **0.75ns**, the plots are shown in Appendix.
Here we will compare the post-layout delay measurements with the schematic level delay measurement 50f F cap is attached to the output. We apply two set of input to the multiplier so we can get the transfer data of all output. The first set is  0000 x 1111 = 11100001 and the second set is  0010 x 1111 = 00011110. As we measure, the maxmun down-to-up delay is **1ns** and uo-to-down delay is **0.75ns**, the plots are shown in Appendix.

## Layout Technic